sim/testsuite/bfin/c_br_preg_stall_ex1.s

   1 //Original:/testcases/seq/c_br_preg_stall_ex1/c_br_preg_stall_ex1.dsp
   2 // Spec Reference: brcc kills  data cache hits
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8         imm32 r0, 0x00000000;
   9         imm32 r1, 0x00000001;
  10         imm32 r2, 0x00000002;
  11         imm32 r3, 0x00000003;
  12         imm32 r4, 0x00000004;
  13         imm32 r5, 0x00000005;
  14         imm32 r6, 0x00000006;
  15         imm32 r7, 0x00000007;
  16         imm32 p1, 0x00000011;
  17         imm32 p2, 0x00000012;
  18 .ifndef BFIN_HOST
  19         imm32 p3, 0x00000013;
  20 .endif
  21         imm32 p4, 0x00000014;
  22
  23         P1 = 4;
  24         P2 = 6;
  25         loadsym p5, DATA0;
  26         loadsym I0, DATA1;
  27
  28 begin:
  29         ASTAT = R0;     // clear CC
  30         R0 = CC;
  31         IF CC R1 = R0;
  32         IF !CC JUMP LABEL1;
  33         R0 = LC0;
  34         R2 = R1 + R0;
  35 LABEL1:
  36         JUMP ( PC + P1 );       // EX1 relative to 'brf LABEL1'
  37         CC = ! CC;
  38 LABEL2:
  39         JUMP ( PC + P1 );       //brf LABEL3;
  40         JUMP ( PC + P2 );       //BAD1;              // UJUMP     killed
  41 LABEL3:
  42         JUMP ( PC + P1 );       //brf LABELCHK1;
  43 BAD1:
  44         R7 = [ P5 ];    // LDST      killed
  45
  46 LABELCHK1:
  47         CHECKREG r0, 0x00000000;
  48         CHECKREG r1, 0x00000001;
  49         CHECKREG r2, 0x00000002;
  50         CHECKREG r3, 0x00000003;
  51         CHECKREG r4, 0x00000004;
  52         CHECKREG r5, 0x00000005;
  53         CHECKREG r6, 0x00000006;
  54         CHECKREG r7, 0x00000007;
  55
  56         pass
  57
  58         .data
  59 DATA0:
  60         .dd 0x000a0000
  61         .dd 0x000b0001
  62         .dd 0x000c0002
  63         .dd 0x000d0003
  64         .dd 0x000e0004
  65
  66 DATA1:
  67         .dd 0x00f00100
  68         .dd 0x00e00101
  69         .dd 0x00d00102
  70         .dd 0x00c00103