sim/testsuite/bfin/c_compi2opd_dr_add_i7_n.s

   1 //Original:/testcases/core/c_compi2opd_dr_add_i7_n/c_compi2opd_dr_add_i7_n.dsp
   2 // Spec Reference: compi2opd dregs += imm7 negative
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9 INIT_R_REGS 0;
  10
  11 R0 += 0;
  12 R1 += -1;
  13 R2 += -2;
  14 R3 += -3;
  15 R4 += -4;
  16 R5 += -5;
  17 R6 += -6;
  18 R7 += -7;
  19 CHECKREG r0, 0x00000000;
  20 CHECKREG r1, 0xFFFFFFFF;
  21 CHECKREG r2, 0xFFFFFFFE;
  22 CHECKREG r3, 0xFFFFFFFD;
  23 CHECKREG r4, 0xFFFFFFFC;
  24 CHECKREG r5, 0xFFFFFFFB;
  25 CHECKREG r6, 0xFFFFFFFA;
  26 CHECKREG r7, 0xFFFFFFF9;
  27
  28 R0 += -8;
  29 R1 += -9;
  30 R2 += -10;
  31 R3 += -11;
  32 R4 += -12;
  33 R5 += -13;
  34 R6 += -14;
  35 R7 += -15;
  36 CHECKREG r0, 0xFFFFFFF8;
  37 CHECKREG r1, 0xFFFFFFF6;
  38 CHECKREG r2, 0xFFFFFFF4;
  39 CHECKREG r3, 0xFFFFFFF2;
  40 CHECKREG r4, 0xFFFFFFF0;
  41 CHECKREG r5, 0xFFFFFFEE;
  42 CHECKREG r6, 0xFFFFFFEC;
  43 CHECKREG r7, 0xFFFFFFEA;
  44
  45 R0 += -16;
  46 R1 += -17;
  47 R2 += -18;
  48 R3 += -19;
  49 R4 += -20;
  50 R5 += -21;
  51 R6 += -22;
  52 R7 += -23;
  53 CHECKREG r0, 0xFFFFFFE8;
  54 CHECKREG r1, 0xFFFFFFE5;
  55 CHECKREG r2, 0xFFFFFFE2;
  56 CHECKREG r3, 0xFFFFFFDF;
  57 CHECKREG r4, 0xFFFFFFDC;
  58 CHECKREG r5, 0xFFFFFFD9;
  59 CHECKREG r6, 0xFFFFFFD6;
  60 CHECKREG r7, 0xFFFFFFD3;
  61
  62 R0 += -24;
  63 R1 += -25;
  64 R2 += -26;
  65 R3 += -27;
  66 R4 += -28;
  67 R5 += -29;
  68 R6 += -30;
  69 R7 += -31;
  70 CHECKREG r0, 0xFFFFFFD0;
  71 CHECKREG r1, 0xFFFFFFCC;
  72 CHECKREG r2, 0xFFFFFFC8;
  73 CHECKREG r3, 0xFFFFFFC4;
  74 CHECKREG r4, 0xFFFFFFC0;
  75 CHECKREG r5, 0xFFFFFFBC;
  76 CHECKREG r6, 0xFFFFFFB8;
  77 CHECKREG r7, 0xFFFFFFB4;
  78
  79 R0 += -32;
  80 R1 += -33;
  81 R2 += -34;
  82 R3 += -35;
  83 R4 += -36;
  84 R5 += -37;
  85 R6 += -38;
  86 R7 += -39;
  87 CHECKREG r0, 0xFFFFFFB0;
  88 CHECKREG r1, 0xFFFFFFAB;
  89 CHECKREG r2, 0xFFFFFFA6;
  90 CHECKREG r3, 0xFFFFFFA1;
  91 CHECKREG r4, 0xFFFFFF9C;
  92 CHECKREG r5, 0xFFFFFF97;
  93 CHECKREG r6, 0xFFFFFF92;
  94 CHECKREG r7, 0xFFFFFF8D;
  95
  96 R0 += -40;
  97 R1 += -41;
  98 R2 += -42;
  99 R3 += -43;
 100 R4 += -44;
 101 R5 += -45;
 102 R6 += -46;
 103 R7 += -47;
 104 CHECKREG r0, 0xFFFFFF88;
 105 CHECKREG r1, 0xFFFFFF82;
 106 CHECKREG r2, 0xFFFFFF7C;
 107 CHECKREG r3, 0xFFFFFF76;
 108 CHECKREG r4, 0xFFFFFF70;
 109 CHECKREG r5, 0xFFFFFF6A;
 110 CHECKREG r6, 0xFFFFFF64;
 111 CHECKREG r7, 0xFFFFFF5E;
 112
 113 R0 += -48;
 114 R1 += -49;
 115 R2 += -50;
 116 R3 += -51;
 117 R4 += -52;
 118 R5 += -53;
 119 R6 += -54;
 120 R7 += -55;
 121 CHECKREG r0, 0xFFFFFF58;
 122 CHECKREG r1, 0xFFFFFF51;
 123 CHECKREG r2, 0xFFFFFF4A;
 124 CHECKREG r3, 0xFFFFFF43;
 125 CHECKREG r4, 0xFFFFFF3C;
 126 CHECKREG r5, 0xFFFFFF35;
 127 CHECKREG r6, 0xFFFFFF2E;
 128 CHECKREG r7, 0xFFFFFF27;
 129
 130 R0 += -56;
 131 R1 += -57;
 132 R2 += -58;
 133 R3 += -59;
 134 R4 += -60;
 135 R5 += -61;
 136 R6 += -62;
 137 R7 += -63;
 138 CHECKREG r0, 0xFFFFFF20;
 139 CHECKREG r1, 0xFFFFFF18;
 140 CHECKREG r2, 0xFFFFFF10;
 141 CHECKREG r3, 0xFFFFFF08;
 142 CHECKREG r4, 0xFFFFFF00;
 143 CHECKREG r5, 0xFFFFFEF8;
 144 CHECKREG r6, 0xFFFFFEF0;
 145 CHECKREG r7, 0xFFFFFEE8;
 146
 147 R0 += -64;
 148 R1 += -64;
 149 R2 += -64;
 150 R3 += -64;
 151 R4 += -64;
 152 R5 += -64;
 153 R6 += -64;
 154 R7 += -64;
 155 CHECKREG r0, 0xFFFFFEE0;
 156 CHECKREG r1, 0xFFFFFED8;
 157 CHECKREG r2, 0xFFFFFED0;
 158 CHECKREG r3, 0xFFFFFEC8;
 159 CHECKREG r4, 0xFFFFFEC0;
 160 CHECKREG r5, 0xFFFFFEB8;
 161 CHECKREG r6, 0xFFFFFEB0;
 162 CHECKREG r7, 0xFFFFFEA8;
 163
 164 pass