sim/testsuite/bfin/c_compi2opd_dr_eq_i7_p.s

   1 //Original:/testcases/core/c_compi2opd_dr_eq_i7_p/c_compi2opd_dr_eq_i7_p.dsp
   2 // Spec Reference: compi2opd dregs = imm7 positive
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9 INIT_R_REGS 0;
  10
  11 R0 = 0;
  12 R1 = 1;
  13 R2 = 2;
  14 R3 = 3;
  15 R4 = 4;
  16 R5 = 5;
  17 R6 = 6;
  18 R7 = 7;
  19 CHECKREG r0, 0;
  20 CHECKREG r1, 1;
  21 CHECKREG r2, 2;
  22 CHECKREG r3, 3;
  23 CHECKREG r4, 4;
  24 CHECKREG r5, 5;
  25 CHECKREG r6, 6;
  26 CHECKREG r7, 7;
  27
  28 R0 = 8;
  29 R1 = 9;
  30 R2 = 10;
  31 R3 = 11;
  32 R4 = 12;
  33 R5 = 13;
  34 R6 = 14;
  35 R7 = 15;
  36 CHECKREG r0, 8;
  37 CHECKREG r1, 9;
  38 CHECKREG r2, 10;
  39 CHECKREG r3, 11;
  40 CHECKREG r4, 12;
  41 CHECKREG r5, 13;
  42 CHECKREG r6, 14;
  43 CHECKREG r7, 15;
  44
  45 R0 = 16;
  46 R1 = 17;
  47 R2 = 18;
  48 R3 = 19;
  49 R4 = 20;
  50 R5 = 21;
  51 R6 = 22;
  52 R7 = 23;
  53 CHECKREG r0, 16;
  54 CHECKREG r1, 17;
  55 CHECKREG r2, 18;
  56 CHECKREG r3, 19;
  57 CHECKREG r4, 20;
  58 CHECKREG r5, 21;
  59 CHECKREG r6, 22;
  60 CHECKREG r7, 23;
  61
  62 R0 = 24;
  63 R1 = 25;
  64 R2 = 26;
  65 R3 = 27;
  66 R4 = 28;
  67 R5 = 29;
  68 R6 = 30;
  69 R7 = 31;
  70 CHECKREG r0, 24;
  71 CHECKREG r1, 25;
  72 CHECKREG r2, 26;
  73 CHECKREG r3, 27;
  74 CHECKREG r4, 28;
  75 CHECKREG r5, 29;
  76 CHECKREG r6, 30;
  77 CHECKREG r7, 31;
  78
  79 R0 = 32;
  80 R1 = 33;
  81 R2 = 34;
  82 R3 = 35;
  83 R4 = 36;
  84 R5 = 37;
  85 R6 = 38;
  86 R7 = 39;
  87 CHECKREG r0, 32;
  88 CHECKREG r1, 33;
  89 CHECKREG r2, 34;
  90 CHECKREG r3, 35;
  91 CHECKREG r4, 36;
  92 CHECKREG r5, 37;
  93 CHECKREG r6, 38;
  94 CHECKREG r7, 39;
  95
  96 R0 = 40;
  97 R1 = 41;
  98 R2 = 42;
  99 R3 = 43;
 100 R4 = 44;
 101 R5 = 45;
 102 R6 = 46;
 103 R7 = 47;
 104 CHECKREG r0, 40;
 105 CHECKREG r1, 41;
 106 CHECKREG r2, 42;
 107 CHECKREG r3, 43;
 108 CHECKREG r4, 44;
 109 CHECKREG r5, 45;
 110 CHECKREG r6, 46;
 111 CHECKREG r7, 47;
 112
 113 R0 = 48;
 114 R1 = 49;
 115 R2 = 50;
 116 R3 = 51;
 117 R4 = 52;
 118 R5 = 53;
 119 R6 = 54;
 120 R7 = 55;
 121 CHECKREG r0, 48;
 122 CHECKREG r1, 49;
 123 CHECKREG r2, 50;
 124 CHECKREG r3, 51;
 125 CHECKREG r4, 52;
 126 CHECKREG r5, 53;
 127 CHECKREG r6, 54;
 128 CHECKREG r7, 55;
 129
 130 R0 = 56;
 131 R1 = 57;
 132 R2 = 58;
 133 R3 = 59;
 134 R4 = 60;
 135 R5 = 61;
 136 R6 = 62;
 137 R7 = 63;
 138 CHECKREG r0, 56;
 139 CHECKREG r1, 57;
 140 CHECKREG r2, 58;
 141 CHECKREG r3, 59;
 142 CHECKREG r4, 60;
 143 CHECKREG r5, 61;
 144 CHECKREG r6, 62;
 145 CHECKREG r7, 63;
 146
 147 pass