sim/testsuite/bfin/c_dsp32mac_dr_a0.s

   1 //Original:/testcases/core/c_dsp32mac_dr_a0/c_dsp32mac_dr_a0.dsp
   2 // Spec Reference: dsp32mac dr_a0
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9
  10
  11 imm32 r0, 0xab235675;
  12 imm32 r1, 0xcaba5127;
  13 imm32 r2, 0x13a46705;
  14 imm32 r3, 0x000a0007;
  15 imm32 r4, 0x90abad09;
  16 imm32 r5, 0x10aceadb;
  17 imm32 r6, 0x000c00ad;
  18 imm32 r7, 0x1246700a;
  19
  20 A1 = A0 = 0;
  21
  22 // The result accumulated in A1 , and stored to a reg half
  23 imm32 r0, 0xb3545abd;
  24 imm32 r1, 0xabbcfec7;
  25 imm32 r2, 0xa1b45679;
  26 imm32 r3, 0x000b0007;
  27 imm32 r4, 0xefbcb569;
  28 imm32 r5, 0x12350b0b;
  29 imm32 r6, 0x000c00bd;
  30 imm32 r7, 0x678e000b;
  31 A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L );
  32 R1 = A0.w;
  33 A1 -= R2.L * R3.L, R2.L = ( A0 = R2.H * R3.L );
  34 R3 = A0.w;
  35 A1 = R4.L * R5.L, R4.L = ( A0 += R4.H * R5.H );
  36 R5 = A0.w;
  37 A1 = R6.L * R7.L, R6.L = ( A0 = R6.L * R7.H );
  38 R7 = A0.w;
  39 CHECKREG r0, 0xB354FF22;
  40 CHECKREG r1, 0xFF221DD6;
  41 CHECKREG r2, 0xA1B4FFFB;
  42 CHECKREG r3, 0xFFFAD7D8;
  43 CHECKREG r4, 0xEFBCFDAB;
  44 CHECKREG r5, 0xFDAA8BB0;
  45 CHECKREG r6, 0x000C0099;
  46 CHECKREG r7, 0x0098E7AC;
  47
  48 imm32 r0, 0xc3545abd;
  49 imm32 r1, 0xacbcfec7;
  50 imm32 r2, 0xa1c45679;
  51 imm32 r3, 0x000c0007;
  52 imm32 r4, 0xefbcc569;
  53 imm32 r5, 0x12350c0b;
  54 imm32 r6, 0x000c00cd;
  55 imm32 r7, 0x678e000c;
  56 A1 = R1.L * R0.H, R0.L = ( A0 = R1.L * R0.L );
  57 R1 = A0.w;
  58 A1 -= R2.L * R3.H, R2.L = ( A0 -= R2.H * R3.L );
  59 R3 = A0.w;
  60 A1 = R4.H * R5.H, R4.L = ( A0 += R4.H * R5.H );
  61 R5 = A0.w;
  62 A1 -= R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H );
  63 R7 = A0.w;
  64 CHECKREG r0, 0xC354FF22;
  65 CHECKREG r1, 0xFF221DD6;
  66 CHECKREG r2, 0xA1C4FF27;
  67 CHECKREG r3, 0xFF27451E;
  68 CHECKREG r4, 0xEFBCFCD7;
  69 CHECKREG r5, 0xFCD6F8F6;
  70 CHECKREG r6, 0x000CFD7D;
  71 CHECKREG r7, 0xFD7CD262;
  72
  73 imm32 r0, 0xd3545abd;
  74 imm32 r1, 0xadbcfec7;
  75 imm32 r2, 0xa1d45679;
  76 imm32 r3, 0x000d0007;
  77 imm32 r4, 0xefbcd569;
  78 imm32 r5, 0x12350d0b;
  79 imm32 r6, 0x000c00dd;
  80 imm32 r7, 0x678e000d;
  81 A1 += R1.H * R0.L, R0.L = ( A0 -= R1.L * R0.L );
  82 R1 = A0.w;
  83 A1 = R2.H * R3.H, R2.L = ( A0 -= R2.H * R3.L );
  84 R3 = A0.w;
  85 A1 -= R4.H * R5.L, R4.L = ( A0 -= R4.H * R5.H );
  86 R5 = A0.w;
  87 A1 += R6.H * R7.L, R6.L = ( A0 = R6.L * R7.H );
  88 R7 = A0.w;
  89 CHECKREG r0, 0xD354FE5B;
  90 CHECKREG r1, 0xFE5AB48C;
  91 CHECKREG r2, 0xA1D4FE60;
  92 CHECKREG r3, 0xFE5FDAF4;
  93 CHECKREG r4, 0xEFBC00B0;
  94 CHECKREG r5, 0x00B0271C;
  95 CHECKREG r6, 0x000C00B3;
  96 CHECKREG r7, 0x00B2CB2C;
  97
  98 imm32 r0, 0xe3545abd;
  99 imm32 r1, 0xaebcfec7;
 100 imm32 r2, 0xa1e45679;
 101 imm32 r3, 0x000e0007;
 102 imm32 r4, 0xefbce569;
 103 imm32 r5, 0x12350e0b;
 104 imm32 r6, 0x000c00ed;
 105 imm32 r7, 0x678e000e;
 106 A1 = R1.H * R0.H, R0.L = ( A0 = R1.L * R0.L );
 107 R1 = A0.w;
 108 A1 += R2.H * R3.H, R2.L = ( A0 += R2.H * R3.L );
 109 R3 = A0.w;
 110 A1 = R4.H * R5.H, R4.L = ( A0 = R4.H * R5.H );
 111 R5 = A0.w;
 112 A1 = R6.H * R7.H, R6.L = ( A0 -= R6.L * R7.H );
 113 R7 = A0.w;
 114 CHECKREG r0, 0xE354FF22;
 115 CHECKREG r1, 0xFF221DD6;
 116 CHECKREG r2, 0xA1E4FF1D;
 117 CHECKREG r3, 0xFF1CF84E;
 118 CHECKREG r4, 0xEFBCFDB0;
 119 CHECKREG r5, 0xFDAFB3D8;
 120 CHECKREG r6, 0x000CFCF0;
 121 CHECKREG r7, 0xFCEFF6EC;
 122
 123
 124 pass