sim/testsuite/bfin/c_dsp32mac_dr_a0_s.s

   1 //Original:/testcases/core/c_dsp32mac_dr_a0_s/c_dsp32mac_dr_a0_s.dsp
   2 // Spec Reference: dsp32mac dr a0 s (scale by 2.0 signed fraction with round)
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9
  10
  11 A1 = A0 = 0;
  12
  13 // The result accumulated in A , and stored to a reg half
  14 imm32 r0, 0x83545abd;
  15 imm32 r1, 0x98bcfec7;
  16 imm32 r2, 0xc9948679;
  17 imm32 r3, 0xd0999007;
  18 imm32 r4, 0xefb99569;
  19 imm32 r5, 0xcd35900b;
  20 imm32 r6, 0xe00c89ad;
  21 imm32 r7, 0xf78e909a;
  22 A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ) (S2RND);
  23 R1 = A0.w;
  24 A1 = R2.L * R3.H, R2.L = ( A0 = R2.H * R3.L ) (S2RND);
  25 R3 = A0.w;
  26 A1 = R4.H * R5.L, R4.L = ( A0 += R4.H * R5.H ) (S2RND);
  27 R5 = A0.w;
  28 A1 = R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ) (S2RND);
  29 R7 = A0.w;
  30 CHECKREG r0, 0x8354FE44;
  31 CHECKREG r1, 0xFF221DD6;
  32 CHECKREG r2, 0xC9945F37;
  33 CHECKREG r3, 0x2F9B8618;
  34 CHECKREG r4, 0xEFB96C22;
  35 CHECKREG r5, 0x361112B2;
  36 CHECKREG r6, 0xE00C7BBF;
  37 CHECKREG r7, 0x3DDFA49E;
  38
  39 // The result accumulated in A , and stored to a reg half (MNOP)
  40 imm32 r0, 0xc8548abd;
  41 imm32 r1, 0x7bccfec7;
  42 imm32 r2, 0xa1bc5679;
  43 imm32 r3, 0xb00bc007;
  44 imm32 r4, 0xcfbcb8c9;
  45 imm32 r5, 0x5235cb8c;
  46 imm32 r6, 0xe50ca0b8;
  47 imm32 r7, 0x675e700b;
  48 R0.L = ( A0 = R1.L * R0.L ) (S2RND);
  49 R1 = A0.w;
  50 R2.L = ( A0 += R2.L * R3.H ) (S2RND);
  51 R3 = A0.w;
  52 R4.L = ( A0 -= R4.H * R5.L ) (S2RND);
  53 R5 = A0.w;
  54 R6.L = ( A0 = R6.H * R7.H ) (S2RND);
  55 R7 = A0.w;
  56 CHECKREG r0, 0xC854023D;
  57 CHECKREG r1, 0x011EBDD6;
  58 CHECKREG r2, 0xA1BC9635;
  59 CHECKREG r3, 0xCB1A8C3C;
  60 CHECKREG r4, 0xCFBC8000;
  61 CHECKREG r5, 0xB7532E9C;
  62 CHECKREG r6, 0xE50CD478;
  63 CHECKREG r7, 0xEA3BDCD0;
  64
  65 // The result accumulated in A , and stored to a reg half (MNOP)
  66 imm32 r0, 0x7b54babd;
  67 imm32 r1, 0xbabcdec7;
  68 imm32 r2, 0xabbbe679;
  69 imm32 r3, 0x8abdb007;
  70 imm32 r4, 0x9fab7b69;
  71 imm32 r5, 0xa23a87bb;
  72 imm32 r6, 0xb00ca88b;
  73 imm32 r7, 0xc78eaab8;
  74 R0.L = ( A0 = R1.L * R0.L ) (S2RND);
  75 R1 = A0.w;
  76 R2.L = ( A0 -= R2.H * R3.L ) (S2RND);
  77 R3 = A0.w;
  78 R4.L = ( A0 = R4.H * R5.H ) (S2RND);
  79 R5 = A0.w;
  80 R6.L = ( A0 += R6.L * R7.H ) (S2RND);
  81 R7 = A0.w;
  82 CHECKREG r0, 0x7B5423F4;
  83 CHECKREG r1, 0x11FA1DD6;
  84 CHECKREG r2, 0xABBBBAA7;
  85 CHECKREG r3, 0xDD53999C;
  86 CHECKREG r4, 0x9FAB7FFF;
  87 CHECKREG r5, 0x4692C57C;
  88 CHECKREG r6, 0xB00C7FFF;
  89 CHECKREG r7, 0x6D23D9B0;
  90
  91 // The result accumulated in A , and stored to a reg half
  92 imm32 r0, 0xfa545abd;
  93 imm32 r1, 0x5ffcfec7;
  94 imm32 r2, 0xc1ef5679;
  95 imm32 r3, 0x9c0ef007;
  96 imm32 r4, 0xafccec69;
  97 imm32 r5, 0xd23c9e1b;
  98 imm32 r6, 0xc00cc0e2;
  99 imm32 r7, 0x678edc0e;
 100 A1 = R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L ) (S2RND);
 101 R3 = A0.w;
 102 A1 += R2.L * R3.H (M), R6.L = ( A0 = R2.H * R3.L ) (S2RND);
 103 R7 = A0.w;
 104 A1 += R4.H * R5.L (M), R4.L = ( A0 -= R4.H * R5.H ) (S2RND);
 105 R5 = A0.w;
 106 A1 = R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H ) (S2RND);
 107 R1 = A0.w;
 108 CHECKREG r0, 0xFA54CF65;
 109 CHECKREG r1, 0xE7B2ACD4;
 110 CHECKREG r2, 0xC1EF7FFF;
 111 CHECKREG r3, 0x6C45F786;
 112 CHECKREG r4, 0xAFCCCEDE;
 113 CHECKREG r5, 0xE76F2094;
 114 CHECKREG r6, 0xC00C0838;
 115 CHECKREG r7, 0x041C3834;
 116
 117
 118
 119 pass