sim/testsuite/bfin/c_dsp32mac_dr_a0_tu.s

   1 //Original:/testcases/core/c_dsp32mac_dr_a0_tu/c_dsp32mac_dr_a0_tu.dsp
   2 // Spec Reference: dsp32mac dr a0 tu (truncate unsigned fraction)
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9
  10
  11 A1 = A0 = 0;
  12
  13 // The result accumulated in A , and stored to a reg half
  14 imm32 r0, 0xf3545abd;
  15 imm32 r1, 0x7fbcfec7;
  16 imm32 r2, 0xc7fff679;
  17 imm32 r3, 0xd0799007;
  18 imm32 r4, 0xefb79f69;
  19 imm32 r5, 0xcd35700b;
  20 imm32 r6, 0xe00c87fd;
  21 imm32 r7, 0xf78e909f;
  22 A1 = R1.L * R0.L, R0.L = ( A0 = R1.L * R0.L ) (TFU);
  23 R1 = A0.w;
  24 A1 -= R2.L * R3.H, R2.L = ( A0 -= R2.H * R3.L ) (TFU);
  25 R3 = A0.w;
  26 A1 += R4.H * R5.L, R4.L = ( A0 -= R4.H * R5.H ) (TFU);
  27 R5 = A0.w;
  28 A1 += R6.H * R7.H, R6.L = ( A0 += R6.L * R7.H ) (TFU);
  29 R7 = A0.w;
  30 CHECKREG r0, 0xF3545A4E;
  31 CHECKREG r1, 0x5A4E0EEB;
  32 CHECKREG r2, 0xC7FF0000;
  33 CHECKREG r3, 0x00000000;
  34 CHECKREG r4, 0xEFB70000;
  35 CHECKREG r5, 0x00000000;
  36 CHECKREG r6, 0xE00C8380;
  37 CHECKREG r7, 0x83808956;
  38
  39 // The result accumulated in A , and stored to a reg half (MNOP)
  40 imm32 r0, 0xc5548abd;
  41 imm32 r1, 0x9b5cfec7;
  42 imm32 r2, 0xa9b55679;
  43 imm32 r3, 0xb09b5007;
  44 imm32 r4, 0xcfb9b5c9;
  45 imm32 r5, 0x52359b5c;
  46 imm32 r6, 0xe50c5098;
  47 imm32 r7, 0x675e7509;
  48 R0.L = ( A0 = R1.L * R0.L ) (TFU);
  49 R1 = A0.w;
  50 R2.L = ( A0 += R2.L * R3.H ) (TFU);
  51 R3 = A0.w;
  52 R4.L = ( A0 = R4.H * R5.L ) (TFU);
  53 R5 = A0.w;
  54 R6.L = ( A0 -= R6.H * R7.H ) (TFU);
  55 R7 = A0.w;
  56 CHECKREG r0, 0xC5548A13;
  57 CHECKREG r1, 0x8A135EEB;
  58 CHECKREG r2, 0xA9B5C5BA;
  59 CHECKREG r3, 0xC5BAEA2E;
  60 CHECKREG r4, 0xCFB97E0F;
  61 CHECKREG r5, 0x7E0FA97C;
  62 CHECKREG r6, 0xE50C2193;
  63 CHECKREG r7, 0x2193BB14;
  64
  65 // The result accumulated in A , and stored to a reg half (MNOP)
  66 imm32 r0, 0x4b54babd;
  67 imm32 r1, 0x12346ec7;
  68 imm32 r2, 0xa4bbe679;
  69 imm32 r3, 0x8abdb707;
  70 imm32 r4, 0x9f4b7b69;
  71 imm32 r5, 0xa234877b;
  72 imm32 r6, 0xb00c4887;
  73 imm32 r7, 0xc78ea4b8;
  74 R0.L = ( A0 -= R1.L * R0.L ) (TFU);
  75 R1 = A0.w;
  76 R2.L = ( A0 = R2.H * R3.L ) (TFU);
  77 R3 = A0.w;
  78 R4.L = ( A0 -= R4.H * R5.H ) (TFU);
  79 R5 = A0.w;
  80 R6.L = ( A0 += R6.L * R7.H ) (TFU);
  81 R7 = A0.w;
  82 CHECKREG r0, 0x4B540000;
  83 CHECKREG r1, 0x00000000;
  84 CHECKREG r2, 0xA4BB75C6;
  85 CHECKREG r3, 0x75C62E1D;
  86 CHECKREG r4, 0x9F4B10D8;
  87 CHECKREG r5, 0x10D85CE1;
  88 CHECKREG r6, 0xB00C4961;
  89 CHECKREG r7, 0x496188C3;
  90
  91 // The result accumulated in A , and stored to a reg half
  92 imm32 r0, 0x1a545abd;
  93 imm32 r1, 0x42fcfec7;
  94 imm32 r2, 0xc53f5679;
  95 imm32 r3, 0x9c64f007;
  96 imm32 r4, 0xafc7ec69;
  97 imm32 r5, 0xd23c891b;
  98 imm32 r6, 0xc00cc602;
  99 imm32 r7, 0x678edc7e;
 100 A1 -= R1.L * R0.L (M), R2.L = ( A0 += R1.L * R0.L ) (TFU);
 101 R3 = A0.w;
 102 A1 += R2.L * R3.H (M), R6.L = ( A0 -= R2.H * R3.L ) (TFU);
 103 R7 = A0.w;
 104 A1 += R4.H * R5.L (M), R4.L = ( A0 = R4.H * R5.H ) (TFU);
 105 R5 = A0.w;
 106 A1 -= R6.H * R7.H (M), R0.L = ( A0 += R6.L * R7.H ) (TFU);
 107 R1 = A0.w;
 108 CHECKREG r0, 0x1A5498EA;
 109 CHECKREG r1, 0x98EA3745;
 110 CHECKREG r2, 0xC53FA3AF;
 111 CHECKREG r3, 0xA3AF97AE;
 112 CHECKREG r4, 0xAFC7905A;
 113 CHECKREG r5, 0x905A70A4;
 114 CHECKREG r6, 0xC00C2ED1;
 115 CHECKREG r7, 0x2ED15DDC;
 116
 117
 118
 119 pass