sim/testsuite/bfin/c_dsp32mac_mix.s

   1 //Original:/testcases/core/c_dsp32mac_mix/c_dsp32mac_mix.dsp
   2 // Spec Reference: dsp32mac mix
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8 imm32 r0, 0xab235675;
   9 imm32 r1, 0xcfba5127;
  10 imm32 r2, 0x13246705;
  11 imm32 r3, 0x00060007;
  12 imm32 r4, 0x90abcd09;
  13 imm32 r5, 0x10acefdb;
  14 imm32 r6, 0x000c000d;
  15 imm32 r7, 0x1246700f;
  16
  17 A1 = A0 = 0;
  18 A0.L = R0.L;
  19 A0.H = R0.H;
  20
  21 // test the ROUNDING only on signed fraction T=1
  22 R0.H = (A1 = R4.L * R5.L), R0.L = (A0 = R4.L * R5.H) (T);
  23 R1.H = (A1 = R4.H * R5.L), R1.L = (A0 = R4.H * R5.H) (T);
  24 R2.H = (A1 = R6.L * R7.L), R2.L = (A0 = R6.H * R7.H) (T);
  25 R3.H = (A1 = R6.L * R7.H), R3.L = (A0 = R6.L * R7.L) (T);
  26 CHECKREG r0, 0x066DF95C;
  27 CHECKREG r1, 0x0E0AF17F;
  28 CHECKREG r2, 0x000B0001;
  29 CHECKREG r3, 0x0001000B;
  30
  31 // When two results are stored to a single register, they must be rounded
  32 // or truncated and stored to the 2 halves of a single destination reg dst
  33
  34 imm32 r0, 0x13545abd;
  35 imm32 r1, 0xadbcfec7;
  36 imm32 r2, 0xa1245679;
  37 imm32 r3, 0x00060007;
  38 imm32 r4, 0xefbc4569;
  39 imm32 r5, 0x1235000b;
  40 imm32 r6, 0x000c000d;
  41 imm32 r7, 0x678e000f;
  42
  43 // The result accumulated in A0 and A1, and stored to a reg half
  44 R2.H = ( A1 = R1.L * R0.H ), A0 = R1.H * R0.L;
  45 R3.H = A1 , A0 = R7.H * R6.L (T);
  46 R4.H = ( A1 = R3.L * R2.H ) (M), A0 = R3.H * R2.L;
  47 A1 = R1.L * R0.H, R5.L = ( A0 = R1.H * R0.L ) (ISS2);
  48
  49 CHECKREG r2, 0xFFD15679;
  50 CHECKREG r3, 0xFFD00007;
  51 CHECKREG r4, 0x00074569;
  52 CHECKREG r5, 0x12358000;
  53
  54 imm32 r0, 0x13545abd;
  55 imm32 r1, 0xadbcfec7;
  56 imm32 r2, 0xa1245679;
  57 imm32 r3, 0x00060007;
  58 imm32 r4, 0xefbc4569;
  59 imm32 r5, 0x1235000b;
  60 imm32 r6, 0x000c000d;
  61 imm32 r7, 0x678e000f;
  62 // The result accumulated in A0 and A1, and stored to a reg
  63 R5.H = (A1 = R1.L * R0.H), R5.L = (A0 = R1.H * R0.L) (TFU);
  64 R6.H = (A1 = R3.L * R2.H) (M), R6.L = (A0 = R3.H * R2.L) (TFU);
  65 R7.H = (A1 = R1.L * R0.H) (M), R7.L = (A0 = R1.H * R0.L) (IH);  // hi-word extraction
  66 CHECKREG r5, 0x133C3D94;
  67 CHECKREG r6, 0x00040002;
  68 CHECKREG r7, 0xFFE8E2D7;
  69
  70
  71 // The result accumulated in A0 and A1, and stored to a reg pair
  72 imm32 r0, 0x13545abd;
  73 imm32 r1, 0xadbcfec7;
  74 imm32 r2, 0xa1245679;
  75 imm32 r3, 0x00060007;
  76 imm32 r4, 0xefbc4569;
  77 imm32 r5, 0x1235000b;
  78 imm32 r6, 0x000c000d;
  79 imm32 r7, 0x678e000f;
  80
  81 R3 = ( A1 = R1.L * R0.H ), A0 = R1.H * R0.L;
  82 R5 = ( A1 = R1.L * R0.H );
  83 R7 = ( A1 += R1.L * R0.H ) (M), A0 -= R1.H * R0.L;
  84 CHECKREG r2, 0xA1245679;
  85 CHECKREG r3, 0xFFD0BC98;
  86 CHECKREG r4, 0xEFBC4569;
  87 CHECKREG r5, 0xFFD0BC98;
  88 CHECKREG r6, 0x000C000D;
  89 CHECKREG r7, 0xFFB91AE4;
  90 A1 = R1.L * R0.H, R2 = ( A0 = R1.H * R0.L );
  91 A1 = R1.L * R0.H (M), R6 = ( A0 -= R1.H * R0.L );
  92 CHECKREG r2, 0xC5AEB798;
  93 CHECKREG r3, 0xFFD0BC98;
  94 CHECKREG r4, 0xEFBC4569;
  95 CHECKREG r5, 0xFFD0BC98;
  96 CHECKREG r6, 0x00000000;
  97 CHECKREG r7, 0xFFB91AE4;
  98
  99 imm32 r0, 0x13545abd;
 100 imm32 r1, 0xadbcfec7;
 101 imm32 r2, 0xa1245679;
 102 imm32 r3, 0x00060007;
 103 imm32 r4, 0xefbc4569;
 104 imm32 r5, 0x1235000b;
 105 imm32 r6, 0x000c000d;
 106 imm32 r7, 0x678e000f;
 107 R3 = ( A1 -= R5.L * R4.H ), R2 = ( A0 -= R5.H * R4.L ) (S2RND);
 108 R3 = ( A1 -= R1.L * R0.H ) (M), R2 = ( A0 += R1.H * R0.L ) (S2RND);
 109 CHECKREG r2, 0x80000000;
 110 CHECKREG r3, 0x0002CBB0;
 111
 112
 113
 114 pass