sim/testsuite/bfin/c_dsp32shift_ahalf_lp_s.s

   1 //Original:/testcases/core/c_dsp32shift_ahalf_lp_s/c_dsp32shift_ahalf_lp_s.dsp
   2 // Spec Reference: dsp32shift ashift s
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9
  10 // Ashift : positive data, count (+)=left (half reg)
  11 // d_lo = ashft (d_lo BY d_lo)
  12 // RLx by RLx
  13 imm32 r0, 0x00000000;
  14 imm32 r1, 0x00000001;
  15 imm32 r2, 0x00000002;
  16 imm32 r3, 0x00000003;
  17 imm32 r4, 0x00000004;
  18 imm32 r5, 0x00000005;
  19 imm32 r6, 0x00000006;
  20 imm32 r7, 0x00000007;
  21 R0.L = ASHIFT R0.L BY R0.L (S);
  22 R1.L = ASHIFT R1.L BY R0.L (S);
  23 R2.L = ASHIFT R2.L BY R0.L (S);
  24 R3.L = ASHIFT R3.L BY R0.L (S);
  25 R4.L = ASHIFT R4.L BY R0.L (S);
  26 R5.L = ASHIFT R5.L BY R0.L (S);
  27 R6.L = ASHIFT R6.L BY R0.L (S);
  28 R7.L = ASHIFT R7.L BY R0.L (S);
  29 CHECKREG r0, 0x00000000;
  30 CHECKREG r1, 0x00000001;
  31 CHECKREG r2, 0x00000002;
  32 CHECKREG r3, 0x00000003;
  33 CHECKREG r4, 0x00000004;
  34 CHECKREG r5, 0x00000005;
  35 CHECKREG r6, 0x00000006;
  36 CHECKREG r7, 0x00000007;
  37
  38 imm32 r0, 0x00000001;
  39 imm32 r1, 0x00000001;
  40 imm32 r2, 0x00000002;
  41 imm32 r3, 0x00000003;
  42 imm32 r4, 0x00000004;
  43 imm32 r5, 0x00000005;
  44 imm32 r6, 0x00000006;
  45 imm32 r7, 0x00000007;
  46 R0.L = ASHIFT R0.L BY R1.L (S);
  47 //rl1 = ashift (rl1 by rl1);
  48 R2.L = ASHIFT R2.L BY R1.L (S);
  49 R3.L = ASHIFT R3.L BY R1.L (S);
  50 R4.L = ASHIFT R4.L BY R1.L (S);
  51 R5.L = ASHIFT R5.L BY R1.L (S);
  52 R6.L = ASHIFT R6.L BY R1.L (S);
  53 R7.L = ASHIFT R7.L BY R1.L (S);
  54 CHECKREG r0, 0x00000002;
  55 CHECKREG r1, 0x00000001;
  56 CHECKREG r2, 0x00000004;
  57 CHECKREG r3, 0x00000006;
  58 CHECKREG r4, 0x00000008;
  59 CHECKREG r5, 0x0000000a;
  60 CHECKREG r6, 0x0000000c;
  61 CHECKREG r7, 0x0000000e;
  62
  63
  64 imm32 r0, 0x00000001;
  65 imm32 r1, 0x00000001;
  66 imm32 r2, 0x0000000f;
  67 imm32 r3, 0x00000003;
  68 imm32 r4, 0x00000004;
  69 imm32 r5, 0x00000005;
  70 imm32 r6, 0x00000006;
  71 imm32 r7, 0x00000007;
  72 R0.L = ASHIFT R0.L BY R2.L (S);
  73 R1.L = ASHIFT R1.L BY R2.L (S);
  74 //rl2 = ashift (rl2 by rl2) s;
  75 R3.L = ASHIFT R3.L BY R2.L (S);
  76 R4.L = ASHIFT R4.L BY R2.L (S);
  77 R5.L = ASHIFT R5.L BY R2.L (S);
  78 R6.L = ASHIFT R6.L BY R2.L (S);
  79 R7.L = ASHIFT R7.L BY R2.L (S);
  80 CHECKREG r0, 0x00007fff;
  81 CHECKREG r1, 0x00007fff;
  82 CHECKREG r2, 0x0000000f;
  83 CHECKREG r3, 0x00007fff;
  84 CHECKREG r4, 0x00007fff;
  85 CHECKREG r5, 0x00007fff;
  86 CHECKREG r6, 0x00007fff;
  87 CHECKREG r7, 0x00007fff;
  88
  89 imm32 r0, 0x00000001;
  90 imm32 r1, 0x00000001;
  91 imm32 r2, 0x00000002;
  92 imm32 r3, 0x00000010;
  93 imm32 r4, 0x00000004;
  94 imm32 r5, 0x00000005;
  95 imm32 r6, 0x00000006;
  96 imm32 r7, 0x00000007;
  97 R0.L = ASHIFT R0.L BY R3.L (S);
  98 R1.L = ASHIFT R1.L BY R3.L (S);
  99 R2.L = ASHIFT R2.L BY R3.L (S);
 100 //rl3 = ashift (rl3 by rl3) s;
 101 R4.L = ASHIFT R4.L BY R3.L (S);
 102 R5.L = ASHIFT R5.L BY R3.L (S);
 103 R6.L = ASHIFT R6.L BY R3.L (S);
 104 R7.L = ASHIFT R7.L BY R3.L (S);
 105 CHECKREG r0, 0x00007fff;
 106 CHECKREG r1, 0x00007fff;
 107 CHECKREG r2, 0x00007fff;
 108 //CHECKREG r3, 0x00000010;
 109 CHECKREG r4, 0x00007fff;
 110 CHECKREG r5, 0x00007fff;
 111 CHECKREG r6, 0x00007fff;
 112 CHECKREG r7, 0x00007fff;
 113
 114 // d_lo = ashft (d_hi BY d_lo)
 115 // RHx by RLx
 116 imm32 r0, 0x00000000;
 117 imm32 r1, 0x00010000;
 118 imm32 r2, 0x00020000;
 119 imm32 r3, 0x00030000;
 120 imm32 r4, 0x00040000;
 121 imm32 r5, 0x00050000;
 122 imm32 r6, 0x00060000;
 123 imm32 r7, 0x00070000;
 124 R0.L = ASHIFT R0.H BY R0.L (S);
 125 R1.L = ASHIFT R1.H BY R0.L (S);
 126 R2.L = ASHIFT R2.H BY R0.L (S);
 127 R3.L = ASHIFT R3.H BY R0.L (S);
 128 R4.L = ASHIFT R4.H BY R0.L (S);
 129 R5.L = ASHIFT R5.H BY R0.L (S);
 130 R6.L = ASHIFT R6.H BY R0.L (S);
 131 R7.L = ASHIFT R7.H BY R0.L (S);
 132 CHECKREG r0, 0x00000000;
 133 CHECKREG r1, 0x00010001;
 134 CHECKREG r2, 0x00020002;
 135 CHECKREG r3, 0x00030003;
 136 CHECKREG r4, 0x00040004;
 137 CHECKREG r5, 0x00050005;
 138 CHECKREG r6, 0x00060006;
 139 CHECKREG r7, 0x00070007;
 140
 141 imm32 r0, 0x00010000;
 142 imm32 r1, 0x00010001;
 143 imm32 r2, 0x00020000;
 144 imm32 r3, 0x00030000;
 145 imm32 r4, 0x00040000;
 146 imm32 r5, 0x00050000;
 147 imm32 r6, 0x00060000;
 148 imm32 r7, 0x00070000;
 149 R0.L = ASHIFT R0.H BY R1.L (S);
 150 //rl1 = ashift (rh1 by rl1);
 151 R2.L = ASHIFT R2.H BY R1.L (S);
 152 R3.L = ASHIFT R3.H BY R1.L (S);
 153 R4.L = ASHIFT R4.H BY R1.L (S);
 154 R5.L = ASHIFT R5.H BY R1.L (S);
 155 R6.L = ASHIFT R6.H BY R1.L (S);
 156 R7.L = ASHIFT R7.H BY R1.L (S);
 157 CHECKREG r0, 0x00010002;
 158 CHECKREG r1, 0x00010001;
 159 CHECKREG r2, 0x00020004;
 160 CHECKREG r3, 0x00030006;
 161 CHECKREG r4, 0x00040008;
 162 CHECKREG r5, 0x0005000a;
 163 CHECKREG r6, 0x0006000c;
 164 CHECKREG r7, 0x0007000e;
 165
 166
 167 imm32 r0, 0x00010000;
 168 imm32 r1, 0x00010000;
 169 imm32 r2, 0x0002000f;
 170 imm32 r3, 0x00030000;
 171 imm32 r4, 0x00040000;
 172 imm32 r5, 0x00050000;
 173 imm32 r6, 0x00060000;
 174 imm32 r7, 0x00070000;
 175 R0.L = ASHIFT R0.H BY R2.L (S);
 176 R1.L = ASHIFT R1.H BY R2.L (S);
 177 //rl2 = ashift (rh2 by rl2);
 178 R3.L = ASHIFT R3.H BY R2.L (S);
 179 R4.L = ASHIFT R4.H BY R2.L (S);
 180 R5.L = ASHIFT R5.H BY R2.L (S);
 181 R6.L = ASHIFT R6.H BY R2.L (S);
 182 R7.L = ASHIFT R7.H BY R2.L (S);
 183 CHECKREG r0, 0x00017fff;
 184 CHECKREG r1, 0x00017fff;
 185 CHECKREG r2, 0x0002000f;
 186 CHECKREG r3, 0x00037fff;
 187 CHECKREG r4, 0x00047fff;
 188 CHECKREG r5, 0x00057fff;
 189 CHECKREG r6, 0x00067fff;
 190 CHECKREG r7, 0x00077fff;
 191
 192 imm32 r0, 0x00010001;
 193 imm32 r1, 0x00010001;
 194 imm32 r2, 0x00020002;
 195 imm32 r3, 0x00030010;
 196 imm32 r4, 0x00040004;
 197 imm32 r5, 0x00050005;
 198 imm32 r6, 0x00060006;
 199 imm32 r7, 0x00070007;
 200 R0.L = ASHIFT R0.H BY R3.L (S);
 201 R1.L = ASHIFT R1.H BY R3.L (S);
 202 R2.L = ASHIFT R2.H BY R3.L (S);
 203 //rl3 = ashift (rh3 by rl3) s;
 204 R4.L = ASHIFT R4.H BY R3.L (S);
 205 R5.L = ASHIFT R5.H BY R3.L (S);
 206 R6.L = ASHIFT R6.H BY R3.L (S);
 207 R7.L = ASHIFT R7.H BY R3.L (S);
 208 CHECKREG r0, 0x00017fff;
 209 CHECKREG r1, 0x00017fff;
 210 CHECKREG r2, 0x00027fff;
 211 CHECKREG r3, 0x00030010;
 212 CHECKREG r4, 0x00047fff;
 213 CHECKREG r5, 0x00057fff;
 214 CHECKREG r6, 0x00067fff;
 215 CHECKREG r7, 0x00077fff;
 216
 217 // d_hi = ashft (d_lo BY d_lo)
 218 // RLx by RLx
 219 imm32 r0, 0x00000000;
 220 imm32 r1, 0x00000001;
 221 imm32 r2, 0x00000002;
 222 imm32 r3, 0x00000003;
 223 imm32 r4, 0x00000004;
 224 imm32 r5, 0x00000005;
 225 imm32 r6, 0x00000006;
 226 imm32 r7, 0x00000007;
 227 R0.H = ASHIFT R0.L BY R0.L (S);
 228 R1.H = ASHIFT R1.L BY R0.L (S);
 229 R2.H = ASHIFT R2.L BY R0.L (S);
 230 R3.H = ASHIFT R3.L BY R0.L (S);
 231 R4.H = ASHIFT R4.L BY R0.L (S);
 232 R5.H = ASHIFT R5.L BY R0.L (S);
 233 R6.H = ASHIFT R6.L BY R0.L (S);
 234 R7.H = ASHIFT R7.L BY R0.L (S);
 235 CHECKREG r0, 0x00000000;
 236 CHECKREG r1, 0x00010001;
 237 CHECKREG r2, 0x00020002;
 238 CHECKREG r3, 0x00030003;
 239 CHECKREG r4, 0x00040004;
 240 CHECKREG r5, 0x00050005;
 241 CHECKREG r6, 0x00060006;
 242 CHECKREG r7, 0x00070007;
 243
 244 imm32 r0, 0x00000001;
 245 imm32 r1, 0x00000001;
 246 imm32 r2, 0x00000002;
 247 imm32 r3, 0x00000003;
 248 imm32 r4, 0x00000004;
 249 imm32 r5, 0x00000005;
 250 imm32 r6, 0x00000006;
 251 imm32 r7, 0x00000007;
 252 R0.H = ASHIFT R0.L BY R1.L (S);
 253 R1.H = ASHIFT R1.L BY R1.L (S);
 254 R2.H = ASHIFT R2.L BY R1.L (S);
 255 R3.H = ASHIFT R3.L BY R1.L (S);
 256 R4.H = ASHIFT R4.L BY R1.L (S);
 257 R5.H = ASHIFT R5.L BY R1.L (S);
 258 R6.H = ASHIFT R6.L BY R1.L (S);
 259 R7.H = ASHIFT R7.L BY R1.L (S);
 260 CHECKREG r0, 0x00020001;
 261 CHECKREG r1, 0x00020001;
 262 CHECKREG r2, 0x00040002;
 263 CHECKREG r3, 0x00060003;
 264 CHECKREG r4, 0x00080004;
 265 CHECKREG r5, 0x000a0005;
 266 CHECKREG r6, 0x000c0006;
 267 CHECKREG r7, 0x000e0007;
 268
 269
 270 imm32 r0, 0x00000001;
 271 imm32 r1, 0x00000001;
 272 imm32 r2, 0x0000000f;
 273 imm32 r3, 0x00000003;
 274 imm32 r4, 0x00000004;
 275 imm32 r5, 0x00000005;
 276 imm32 r6, 0x00000006;
 277 imm32 r7, 0x00000007;
 278 R0.H = ASHIFT R0.L BY R2.L (S);
 279 R1.H = ASHIFT R1.L BY R2.L (S);
 280 //rh2 = ashift (rl2 by rl2) s;
 281 R3.H = ASHIFT R3.L BY R2.L (S);
 282 R4.H = ASHIFT R4.L BY R2.L (S);
 283 R5.H = ASHIFT R5.L BY R2.L (S);
 284 R6.H = ASHIFT R6.L BY R2.L (S);
 285 R7.H = ASHIFT R7.L BY R2.L (S);
 286 CHECKREG r0, 0x7fff0001;
 287 CHECKREG r1, 0x7fff0001;
 288 //ECKREG(r2, 0x7fff000f);
 289 CHECKREG r3, 0x7fff0003;
 290 CHECKREG r4, 0x7fff0004;
 291 CHECKREG r5, 0x7fff0005;
 292 CHECKREG r6, 0x7fff0006;
 293 CHECKREG r7, 0x7fff0007;
 294
 295 imm32 r0, 0x00000001;
 296 imm32 r1, 0x00000001;
 297 imm32 r2, 0x00000002;
 298 imm32 r3, 0x00000010;
 299 imm32 r4, 0x00000004;
 300 imm32 r5, 0x00000005;
 301 imm32 r6, 0x00000006;
 302 imm32 r7, 0x00000007;
 303 R0.H = ASHIFT R0.L BY R3.L (S);
 304 R1.H = ASHIFT R1.L BY R3.L (S);
 305 R2.H = ASHIFT R2.L BY R3.L (S);
 306 R3.H = ASHIFT R3.L BY R3.L (S);
 307 R4.H = ASHIFT R4.L BY R3.L (S);
 308 R5.H = ASHIFT R5.L BY R3.L (S);
 309 R6.H = ASHIFT R6.L BY R3.L (S);
 310 R7.H = ASHIFT R7.L BY R3.L (S);
 311 CHECKREG r0, 0x7fff0001;
 312 CHECKREG r1, 0x7fff0001;
 313 CHECKREG r2, 0x7fff0002;
 314 CHECKREG r3, 0x7fff0010;
 315 CHECKREG r4, 0x7fff0004;
 316 CHECKREG r5, 0x7fff0005;
 317 CHECKREG r6, 0x7fff0006;
 318 CHECKREG r7, 0x7fff0007;
 319
 320 // d_lo = ashft (d_hi BY d_lo)
 321 // RHx by RLx
 322 imm32 r0, 0x00000000;
 323 imm32 r1, 0x00010000;
 324 imm32 r2, 0x00020000;
 325 imm32 r3, 0x00030000;
 326 imm32 r4, 0x00040000;
 327 imm32 r5, 0x00050000;
 328 imm32 r6, 0x00060000;
 329 imm32 r7, 0x00070000;
 330 R0.H = ASHIFT R0.H BY R0.L (S);
 331 R1.H = ASHIFT R1.H BY R0.L (S);
 332 R2.H = ASHIFT R2.H BY R0.L (S);
 333 R3.H = ASHIFT R3.H BY R0.L (S);
 334 R4.H = ASHIFT R4.H BY R0.L (S);
 335 R5.H = ASHIFT R5.H BY R0.L (S);
 336 R6.H = ASHIFT R6.H BY R0.L (S);
 337 R7.H = ASHIFT R7.H BY R0.L (S);
 338 CHECKREG r0, 0x00000000;
 339 CHECKREG r1, 0x00010000;
 340 CHECKREG r2, 0x00020000;
 341 CHECKREG r3, 0x00030000;
 342 CHECKREG r4, 0x00040000;
 343 CHECKREG r5, 0x00050000;
 344 CHECKREG r6, 0x00060000;
 345 CHECKREG r7, 0x00070000;
 346
 347 imm32 r0, 0x00010000;
 348 imm32 r1, 0x00010001;
 349 imm32 r2, 0x00020000;
 350 imm32 r3, 0x00030000;
 351 imm32 r4, 0x00040000;
 352 imm32 r5, 0x00050000;
 353 imm32 r6, 0x00060000;
 354 imm32 r7, 0x00070000;
 355 R0.H = ASHIFT R0.H BY R1.L (S);
 356 R1.H = ASHIFT R1.H BY R1.L (S);
 357 R2.H = ASHIFT R2.H BY R1.L (S);
 358 R3.H = ASHIFT R3.H BY R1.L (S);
 359 R4.H = ASHIFT R4.H BY R1.L (S);
 360 R5.H = ASHIFT R5.H BY R1.L (S);
 361 R6.H = ASHIFT R6.H BY R1.L (S);
 362 R7.H = ASHIFT R7.H BY R1.L (S);
 363 CHECKREG r0, 0x00020000;
 364 CHECKREG r1, 0x00020001;
 365 CHECKREG r2, 0x00040000;
 366 CHECKREG r3, 0x00060000;
 367 CHECKREG r4, 0x00080000;
 368 CHECKREG r5, 0x000a0000;
 369 CHECKREG r6, 0x000c0000;
 370 CHECKREG r7, 0x000e0000;
 371
 372
 373 imm32 r0, 0x00010000;
 374 imm32 r1, 0x00010000;
 375 imm32 r2, 0x0002000f;
 376 imm32 r3, 0x00030000;
 377 imm32 r4, 0x00040000;
 378 imm32 r5, 0x00050000;
 379 imm32 r6, 0x00060000;
 380 imm32 r7, 0x00070000;
 381 R0.L = ASHIFT R0.H BY R2.L (S);
 382 R1.L = ASHIFT R1.H BY R2.L (S);
 383 //rl2 = ashift (rh2 by rl2);
 384 R3.L = ASHIFT R3.H BY R2.L (S);
 385 R4.L = ASHIFT R4.H BY R2.L (S);
 386 R5.L = ASHIFT R5.H BY R2.L (S);
 387 R6.L = ASHIFT R6.H BY R2.L (S);
 388 R7.L = ASHIFT R7.H BY R2.L (S);
 389 CHECKREG r0, 0x00017fff;
 390 CHECKREG r1, 0x00017fff;
 391 //CHECKREG r2, 0x00027fff;
 392 CHECKREG r3, 0x00037fff;
 393 CHECKREG r4, 0x00047fff;
 394 CHECKREG r5, 0x00057fff;
 395 CHECKREG r6, 0x00067fff;
 396 CHECKREG r7, 0x00077fff;
 397
 398 imm32 r0, 0x00010000;
 399 imm32 r1, 0x00010000;
 400 imm32 r2, 0x00020000;
 401 imm32 r3, 0x00030010;
 402 imm32 r4, 0x00040000;
 403 imm32 r5, 0x00050000;
 404 imm32 r6, 0x00060000;
 405 imm32 r7, 0x00070000;
 406 R0.H = ASHIFT R0.H BY R3.L (S);
 407 R1.H = ASHIFT R1.H BY R3.L (S);
 408 R2.H = ASHIFT R2.H BY R3.L (S);
 409 R3.H = ASHIFT R3.H BY R3.L (S);
 410 R4.H = ASHIFT R4.H BY R3.L (S);
 411 R5.H = ASHIFT R5.H BY R3.L (S);
 412 R6.H = ASHIFT R6.H BY R3.L (S);
 413 R7.H = ASHIFT R7.H BY R3.L (S);
 414 CHECKREG r0, 0x7fff0000;
 415 CHECKREG r1, 0x7fff0000;
 416 CHECKREG r2, 0x7fff0000;
 417 CHECKREG r3, 0x7fff0010;
 418 CHECKREG r4, 0x7fff0000;
 419 CHECKREG r5, 0x7fff0000;
 420 CHECKREG r6, 0x7fff0000;
 421 CHECKREG r7, 0x7fff0000;
 422
 423 pass