sim/testsuite/bfin/c_dsp32shift_signbits_r.s

   1 //Original:/testcases/core/c_dsp32shift_signbits_r/c_dsp32shift_signbits_r.dsp
   2 // Spec Reference: dsp32shift signbits dregs
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9
  10
  11
  12 imm32 r0, 0x88880000;
  13 imm32 r1, 0x34560001;
  14 imm32 r2, 0x08000002;
  15 imm32 r3, 0x08000003;
  16 imm32 r4, 0x08000004;
  17 imm32 r5, 0x08000005;
  18 imm32 r6, 0x08000006;
  19 imm32 r7, 0x08000007;
  20 R7.L = SIGNBITS R0;
  21 R1.L = SIGNBITS R0;
  22 R2.L = SIGNBITS R0;
  23 R3.L = SIGNBITS R0;
  24 R4.L = SIGNBITS R0;
  25 R5.L = SIGNBITS R0;
  26 R6.L = SIGNBITS R0;
  27 R0.L = SIGNBITS R0;
  28 CHECKREG r0, 0x88880000;
  29 CHECKREG r1, 0x34560000;
  30 CHECKREG r2, 0x08000000;
  31 CHECKREG r3, 0x08000000;
  32 CHECKREG r4, 0x08000000;
  33 CHECKREG r5, 0x08000000;
  34 CHECKREG r6, 0x08000000;
  35 CHECKREG r7, 0x08000000;
  36
  37 imm32 r0, 0x9999001E;
  38 imm32 r1, 0x0000001E;
  39 imm32 r2, 0x0000001E;
  40 imm32 r3, 0x0000001E;
  41 imm32 r4, 0x0000001E;
  42 imm32 r5, 0x0000001E;
  43 imm32 r6, 0x0000001E;
  44 imm32 r7, 0x0000001E;
  45 R0.L = SIGNBITS R1;
  46 R7.L = SIGNBITS R1;
  47 R2.L = SIGNBITS R1;
  48 R3.L = SIGNBITS R1;
  49 R4.L = SIGNBITS R1;
  50 R5.L = SIGNBITS R1;
  51 R6.L = SIGNBITS R1;
  52 R1.L = SIGNBITS R1;
  53 CHECKREG r0, 0x9999001A;
  54 CHECKREG r1, 0x0000001A;
  55 CHECKREG r2, 0x0000001A;
  56 CHECKREG r3, 0x0000001A;
  57 CHECKREG r4, 0x0000001A;
  58 CHECKREG r5, 0x0000001A;
  59 CHECKREG r6, 0x0000001A;
  60 CHECKREG r7, 0x0000001A;
  61
  62
  63 imm32 r0, 0x0aaae001;
  64 imm32 r1, 0x0000e001;
  65 imm32 r2, 0xaaaa000f;
  66 imm32 r3, 0x0a00e003;
  67 imm32 r4, 0x00a0e004;
  68 imm32 r5, 0x00a0e005;
  69 imm32 r6, 0x0a00e006;
  70 imm32 r7, 0x0b00e007;
  71 R0.L = SIGNBITS R2;
  72 R1.L = SIGNBITS R2;
  73 R7.L = SIGNBITS R2;
  74 R3.L = SIGNBITS R2;
  75 R4.L = SIGNBITS R2;
  76 R5.L = SIGNBITS R2;
  77 R6.L = SIGNBITS R2;
  78 R2.L = SIGNBITS R2;
  79 CHECKREG r0, 0x0AAA0000;
  80 CHECKREG r1, 0x00000000;
  81 CHECKREG r2, 0xAAAA0000;
  82 CHECKREG r3, 0x0A000000;
  83 CHECKREG r4, 0x00A00000;
  84 CHECKREG r5, 0x00A00000;
  85 CHECKREG r6, 0x0A000000;
  86 CHECKREG r7, 0x0B000000;
  87
  88 imm32 r0, 0x0b00f001;
  89 imm32 r1, 0x0a00f001;
  90 imm32 r2, 0x0b00f002;
  91 imm32 r3, 0xbbbb0010;
  92 imm32 r4, 0x0b00f004;
  93 imm32 r5, 0x0b00f005;
  94 imm32 r6, 0x0b00f006;
  95 imm32 r7, 0x00b0f007;
  96 R0.L = SIGNBITS R3;
  97 R1.L = SIGNBITS R3;
  98 R2.L = SIGNBITS R3;
  99 R7.L = SIGNBITS R3;
 100 R4.L = SIGNBITS R3;
 101 R5.L = SIGNBITS R3;
 102 R6.L = SIGNBITS R3;
 103 R3.L = SIGNBITS R3;
 104 CHECKREG r0, 0x0B000000;
 105 CHECKREG r1, 0x0A000000;
 106 CHECKREG r2, 0x0B000000;
 107 CHECKREG r3, 0xBBBB0000;
 108 CHECKREG r4, 0x0B000000;
 109 CHECKREG r5, 0x0B000000;
 110 CHECKREG r6, 0x0B000000;
 111 CHECKREG r7, 0x00B00000;
 112
 113 imm32 r0, 0x00000000;
 114 imm32 r1, 0x00010000;
 115 imm32 r2, 0x00020000;
 116 imm32 r3, 0x00030000;
 117 imm32 r4, 0xcccc0000;
 118 imm32 r5, 0x00050000;
 119 imm32 r6, 0x00060000;
 120 imm32 r7, 0x00070000;
 121 R0.L = SIGNBITS R4;
 122 R1.L = SIGNBITS R4;
 123 R2.L = SIGNBITS R4;
 124 R3.L = SIGNBITS R4;
 125 R7.L = SIGNBITS R4;
 126 R5.L = SIGNBITS R4;
 127 R6.L = SIGNBITS R4;
 128 R4.L = SIGNBITS R4;
 129 CHECKREG r0, 0x00000001;
 130 CHECKREG r1, 0x00010001;
 131 CHECKREG r2, 0x00020001;
 132 CHECKREG r3, 0x00030001;
 133 CHECKREG r4, 0xCCCC0001;
 134 CHECKREG r5, 0x00050001;
 135 CHECKREG r6, 0x00060001;
 136 CHECKREG r7, 0x00070001;
 137
 138 imm32 r0, 0xa0010000;
 139 imm32 r1, 0x00010001;
 140 imm32 r2, 0xa0020000;
 141 imm32 r3, 0xa0030000;
 142 imm32 r4, 0xa0040000;
 143 imm32 r5, 0xdddd0000;
 144 imm32 r6, 0xa0060000;
 145 imm32 r7, 0xa0070000;
 146 R0.L = SIGNBITS R5;
 147 R1.L = SIGNBITS R5;
 148 R2.L = SIGNBITS R5;
 149 R3.L = SIGNBITS R5;
 150 R4.L = SIGNBITS R5;
 151 R7.L = SIGNBITS R5;
 152 R6.L = SIGNBITS R5;
 153 R5.L = SIGNBITS R5;
 154 CHECKREG r0, 0xA0010001;
 155 CHECKREG r1, 0x00010001;
 156 CHECKREG r2, 0xA0020001;
 157 CHECKREG r3, 0xA0030001;
 158 CHECKREG r4, 0xA0040001;
 159 CHECKREG r5, 0xDDDD0001;
 160 CHECKREG r6, 0xA0060001;
 161 CHECKREG r7, 0xA0070001;
 162
 163
 164 imm32 r0, 0xb0010000;
 165 imm32 r1, 0xb0010000;
 166 imm32 r2, 0xb002000f;
 167 imm32 r3, 0xb0030000;
 168 imm32 r4, 0xb0040000;
 169 imm32 r5, 0xb0050000;
 170 imm32 r6, 0xeeee0000;
 171 imm32 r7, 0xb0070000;
 172 R0.L = SIGNBITS R6;
 173 R1.L = SIGNBITS R6;
 174 R2.L = SIGNBITS R6;
 175 R3.L = SIGNBITS R6;
 176 R4.L = SIGNBITS R6;
 177 R5.L = SIGNBITS R6;
 178 R7.L = SIGNBITS R6;
 179 R6.L = SIGNBITS R6;
 180 CHECKREG r0, 0xB0010002;
 181 CHECKREG r1, 0xB0010002;
 182 CHECKREG r2, 0xB0020002;
 183 CHECKREG r3, 0xB0030002;
 184 CHECKREG r4, 0xB0040002;
 185 CHECKREG r5, 0xB0050002;
 186 CHECKREG r6, 0xEEEE0002;
 187 CHECKREG r7, 0xB0070002;
 188
 189 imm32 r0, 0xd0010000;
 190 imm32 r1, 0xd0010000;
 191 imm32 r2, 0xd0020000;
 192 imm32 r3, 0xd0030010;
 193 imm32 r4, 0xd0040000;
 194 imm32 r5, 0xd0050000;
 195 imm32 r6, 0xd0060000;
 196 imm32 r7, 0xffff0000;
 197 R0.L = SIGNBITS R7;
 198 R1.L = SIGNBITS R7;
 199 R2.L = SIGNBITS R7;
 200 R3.L = SIGNBITS R7;
 201 R4.L = SIGNBITS R7;
 202 R5.L = SIGNBITS R7;
 203 R6.L = SIGNBITS R7;
 204 R7.L = SIGNBITS R7;
 205
 206 CHECKREG r0, 0xD001000F;
 207 CHECKREG r1, 0xD001000F;
 208 CHECKREG r2, 0xD002000F;
 209 CHECKREG r3, 0xD003000F;
 210 CHECKREG r4, 0xD004000F;
 211 CHECKREG r5, 0xD005000F;
 212 CHECKREG r6, 0xD006000F;
 213 CHECKREG r7, 0xFFFF000F;
 214 pass