sim/testsuite/bfin/c_dsp32shiftim_lhalf_lp.s

   1 //Original:/testcases/core/c_dsp32shiftim_lhalf_lp/c_dsp32shiftim_lhalf_lp.dsp
   2 // Spec Reference: dspshiftimm dreg_lo(hi) = lshift (dreg_lo(hi) by imm5)
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9
  10 // lshift : positive data, count (+)=left (half reg)
  11 // d_lo = lshift (d_lo BY imm5)
  12 // RLx by imm5
  13 imm32 r0, 0x00100a00;
  14 imm32 r1, 0x00100a01;
  15 imm32 r2, 0x00100a02;
  16 imm32 r3, 0x00100a03;
  17 imm32 r4, 0x00100a04;
  18 imm32 r5, 0x00100a05;
  19 imm32 r6, 0x00100a06;
  20 imm32 r7, 0x00100a07;
  21 R7.L = R0.L << 0;
  22 R0.L = R1.L << 1;
  23 R1.L = R2.L << 2;
  24 R2.L = R3.L << 3;
  25 R3.L = R4.L << 4;
  26 R4.L = R5.L << 5;
  27 R5.L = R6.L << 6;
  28 R6.L = R7.L << 7;
  29 CHECKREG r1, 0x00102808;
  30 CHECKREG r0, 0x00101402;
  31 CHECKREG r2, 0x00105018;
  32 CHECKREG r3, 0x0010A040;
  33 CHECKREG r4, 0x001040A0;
  34 CHECKREG r5, 0x00108180;
  35 CHECKREG r6, 0x00100000;
  36 CHECKREG r7, 0x00100A00;
  37
  38 imm32 r0, 0x00200018;
  39 imm32 r1, 0x00200019;
  40 imm32 r2, 0x0020001a;
  41 imm32 r3, 0x0020001b;
  42 imm32 r4, 0x0020001c;
  43 imm32 r5, 0x0020001d;
  44 imm32 r6, 0x0020001e;
  45 imm32 r7, 0x0020001f;
  46 R2.L = R0.L << 8;
  47 R3.L = R1.L << 9;
  48 R4.L = R2.L << 10;
  49 R5.L = R3.L << 11;
  50 R6.L = R4.L << 12;
  51 R7.L = R5.L << 13;
  52 R0.L = R6.L << 14;
  53 R1.L = R7.L << 15;
  54 CHECKREG r0, 0x00200000;
  55 CHECKREG r1, 0x00200000;
  56 CHECKREG r2, 0x00201800;
  57 CHECKREG r3, 0x00203200;
  58 CHECKREG r4, 0x00200000;
  59 CHECKREG r5, 0x00200000;
  60 CHECKREG r6, 0x00200000;
  61 CHECKREG r7, 0x00200000;
  62
  63 imm32 r0, 0x05002001;
  64 imm32 r1, 0x05002001;
  65 imm32 r2, 0x0500000f;
  66 imm32 r3, 0x05002003;
  67 imm32 r4, 0x05002004;
  68 imm32 r5, 0x05002005;
  69 imm32 r6, 0x05002006;
  70 imm32 r7, 0x05002007;
  71 R3.L = R0.L << 0;
  72 R4.L = R1.L << 1;
  73 R5.L = R2.L << 2;
  74 R6.L = R3.L << 3;
  75 R7.L = R4.L << 4;
  76 R0.L = R5.L << 5;
  77 R1.L = R6.L << 6;
  78 R2.L = R7.L << 7;
  79 CHECKREG r0, 0x05000780;
  80 CHECKREG r1, 0x05000200;
  81 CHECKREG r2, 0x05001000;
  82 CHECKREG r3, 0x05002001;
  83 CHECKREG r4, 0x05004002;
  84 CHECKREG r5, 0x0500003C;
  85 CHECKREG r6, 0x05000008;
  86 CHECKREG r7, 0x05000020;
  87
  88 imm32 r0, 0x03000031;
  89 imm32 r1, 0x03000031;
  90 imm32 r2, 0x03000032;
  91 imm32 r3, 0x03000030;
  92 imm32 r4, 0x03000034;
  93 imm32 r5, 0x03000035;
  94 imm32 r6, 0x03000036;
  95 imm32 r7, 0x03000037;
  96 R4.L = R0.L << 8;
  97 R5.L = R1.L << 9;
  98 R6.L = R2.L << 10;
  99 R7.L = R3.L << 11;
 100 R0.L = R4.L << 12;
 101 R1.L = R5.L << 13;
 102 R2.L = R6.L << 14;
 103 R3.L = R7.L << 15;
 104 CHECKREG r0, 0x03000000;
 105 CHECKREG r1, 0x03000000;
 106 CHECKREG r2, 0x03000000;
 107 CHECKREG r3, 0x03000000;
 108 CHECKREG r4, 0x03003100;
 109 CHECKREG r5, 0x03006200;
 110 CHECKREG r6, 0x0300C800;
 111 CHECKREG r7, 0x03008000;
 112 // RHx by RLx
 113 imm32 r0, 0x03000000;
 114 imm32 r1, 0x03000000;
 115 imm32 r2, 0x03000000;
 116 imm32 r3, 0x03000000;
 117 imm32 r4, 0x03003100;
 118 imm32 r5, 0x03006200;
 119 imm32 r6, 0x0300C800;
 120 imm32 r7, 0x03008000;
 121 R5.L = R0.H << 0;
 122 R6.L = R1.H << 1;
 123 R7.L = R2.H << 2;
 124 R0.L = R3.H << 3;
 125 R1.L = R4.H << 4;
 126 R2.L = R5.H << 5;
 127 R3.L = R6.H << 6;
 128 R4.L = R7.H << 7;
 129 CHECKREG r0, 0x03001800;
 130 CHECKREG r1, 0x03003000;
 131 CHECKREG r2, 0x03006000;
 132 CHECKREG r3, 0x0300C000;
 133 CHECKREG r4, 0x03008000;
 134 CHECKREG r5, 0x03000300;
 135 CHECKREG r6, 0x03000600;
 136 CHECKREG r7, 0x03000C00;
 137
 138 imm32 r0, 0x05018000;
 139 imm32 r1, 0x05018001;
 140 imm32 r2, 0x05028000;
 141 imm32 r3, 0x05038000;
 142 imm32 r4, 0x05048000;
 143 imm32 r5, 0x05058000;
 144 imm32 r6, 0x05068000;
 145 imm32 r7, 0x05078000;
 146 R6.L = R0.H << 8;
 147 R7.L = R1.H << 9;
 148 R0.L = R2.H << 10;
 149 R1.L = R3.H << 11;
 150 R2.L = R4.H << 12;
 151 R3.L = R5.H << 13;
 152 R4.L = R6.H << 14;
 153 R5.L = R7.H << 15;
 154 CHECKREG r0, 0x05010800;
 155 CHECKREG r1, 0x05011800;
 156 CHECKREG r2, 0x05024000;
 157 CHECKREG r3, 0x0503A000;
 158 CHECKREG r4, 0x05048000;
 159 CHECKREG r5, 0x05058000;
 160 CHECKREG r6, 0x05060100;
 161 CHECKREG r7, 0x05070200;
 162
 163
 164 imm32 r0, 0x60019000;
 165 imm32 r1, 0x60019000;
 166 imm32 r2, 0x6002900f;
 167 imm32 r3, 0x60039000;
 168 imm32 r4, 0x60049000;
 169 imm32 r5, 0x60059000;
 170 imm32 r6, 0x60069000;
 171 imm32 r7, 0x60079000;
 172 R7.L = R0.H << 0;
 173 R0.L = R1.H << 1;
 174 R1.L = R2.H << 2;
 175 R2.L = R3.H << 3;
 176 R3.L = R4.H << 4;
 177 R4.L = R5.H << 5;
 178 R5.L = R6.H << 6;
 179 R6.L = R7.H << 7;
 180 CHECKREG r0, 0x6001C002;
 181 CHECKREG r1, 0x60018008;
 182 CHECKREG r2, 0x60020018;
 183 CHECKREG r3, 0x60030040;
 184 CHECKREG r4, 0x600400A0;
 185 CHECKREG r5, 0x60050180;
 186 CHECKREG r6, 0x60060380;
 187 CHECKREG r7, 0x60076001;
 188
 189 imm32 r0, 0x70010001;
 190 imm32 r1, 0x70010001;
 191 imm32 r2, 0x70020002;
 192 imm32 r3, 0x77030010;
 193 imm32 r4, 0x70040004;
 194 imm32 r5, 0x70050005;
 195 imm32 r6, 0x70060006;
 196 imm32 r7, 0x70070007;
 197 R0.L = R0.H << 8;
 198 R1.L = R1.H << 9;
 199 R2.L = R2.H << 10;
 200 R3.L = R3.H << 11;
 201 R4.L = R4.H << 12;
 202 R5.L = R5.H << 13;
 203 R6.L = R6.H << 14;
 204 R7.L = R7.H << 15;
 205 CHECKREG r0, 0x70010100;
 206 CHECKREG r1, 0x70010200;
 207 CHECKREG r2, 0x70020800;
 208 CHECKREG r3, 0x77031800;
 209 CHECKREG r4, 0x70044000;
 210 CHECKREG r5, 0x7005A000;
 211 CHECKREG r6, 0x70068000;
 212 CHECKREG r7, 0x70078000;
 213
 214 // d_hi = lshft (d_lo BY d_lo)
 215 // RLx by RLx
 216 imm32 r0, 0xa8000000;
 217 imm32 r1, 0xa8000001;
 218 imm32 r2, 0xa8000002;
 219 imm32 r3, 0xa8000003;
 220 imm32 r4, 0xa8000004;
 221 imm32 r5, 0xa8000005;
 222 imm32 r6, 0xa8000006;
 223 imm32 r7, 0xa8000007;
 224 R0.H = R0.L << 0;
 225 R1.H = R1.L << 1;
 226 R2.H = R2.L << 2;
 227 R3.H = R3.L << 3;
 228 R4.H = R4.L << 4;
 229 R5.H = R5.L << 5;
 230 R6.H = R6.L << 6;
 231 R7.H = R7.L << 7;
 232 CHECKREG r0, 0x00000000;
 233 CHECKREG r1, 0x00020001;
 234 CHECKREG r2, 0x00080002;
 235 CHECKREG r3, 0x00180003;
 236 CHECKREG r4, 0x00400004;
 237 CHECKREG r5, 0x00A00005;
 238 CHECKREG r6, 0x01800006;
 239 CHECKREG r7, 0x03800007;
 240
 241 imm32 r0, 0xf0090001;
 242 imm32 r1, 0xf0090001;
 243 imm32 r2, 0xf0090002;
 244 imm32 r3, 0xf0090003;
 245 imm32 r4, 0xf0090004;
 246 imm32 r5, 0xf0090005;
 247 imm32 r6, 0xf0000006;
 248 imm32 r7, 0xf0000007;
 249 R1.H = R0.L << 8;
 250 R2.H = R1.L << 9;
 251 R3.H = R2.L << 10;
 252 R4.H = R3.L << 11;
 253 R5.H = R4.L << 12;
 254 R6.H = R5.L << 13;
 255 R7.H = R6.L << 14;
 256 R0.H = R7.L << 15;
 257 CHECKREG r1, 0x01000001;
 258 CHECKREG r2, 0x02000002;
 259 CHECKREG r3, 0x08000003;
 260 CHECKREG r4, 0x18000004;
 261 CHECKREG r5, 0x40000005;
 262 CHECKREG r6, 0xA0000006;
 263 CHECKREG r7, 0x80000007;
 264 CHECKREG r0, 0x80000001;
 265
 266
 267 imm32 r0, 0x07000001;
 268 imm32 r1, 0x07000001;
 269 imm32 r2, 0x0700000f;
 270 imm32 r3, 0x07000003;
 271 imm32 r4, 0x07000004;
 272 imm32 r5, 0x07000005;
 273 imm32 r6, 0x07000006;
 274 imm32 r7, 0x07000007;
 275 R3.H = R0.L << 0;
 276 R4.H = R1.L << 1;
 277 R5.H = R2.L << 2;
 278 R6.H = R3.L << 3;
 279 R7.H = R4.L << 4;
 280 R0.H = R5.L << 5;
 281 R1.H = R6.L << 6;
 282 R2.H = R7.L << 7;
 283 CHECKREG r0, 0x00A00001;
 284 CHECKREG r1, 0x01800001;
 285 CHECKREG r2, 0x0380000F;
 286 CHECKREG r3, 0x00010003;
 287 CHECKREG r4, 0x00020004;
 288 CHECKREG r5, 0x003C0005;
 289 CHECKREG r6, 0x00180006;
 290 CHECKREG r7, 0x00400007;
 291
 292 imm32 r0, 0x00000501;
 293 imm32 r1, 0x00000501;
 294 imm32 r2, 0x00000502;
 295 imm32 r3, 0x00000510;
 296 imm32 r4, 0x00000504;
 297 imm32 r5, 0x00000505;
 298 imm32 r6, 0x00000506;
 299 imm32 r7, 0x00000507;
 300 R4.H = R0.L << 8;
 301 R5.H = R1.L << 9;
 302 R6.H = R2.L << 10;
 303 R7.H = R3.L << 11;
 304 R0.H = R4.L << 12;
 305 R1.H = R5.L << 13;
 306 R2.H = R6.L << 14;
 307 R3.H = R7.L << 15;
 308 CHECKREG r0, 0x40000501;
 309 CHECKREG r1, 0xA0000501;
 310 CHECKREG r2, 0x80000502;
 311 CHECKREG r3, 0x80000510;
 312 CHECKREG r4, 0x01000504;
 313 CHECKREG r5, 0x02000505;
 314 CHECKREG r6, 0x08000506;
 315 CHECKREG r7, 0x80000507;
 316
 317 imm32 r0, 0x00a00800;
 318 imm32 r1, 0x00a10800;
 319 imm32 r2, 0x00a20800;
 320 imm32 r3, 0x00a30800;
 321 imm32 r4, 0x00a40800;
 322 imm32 r5, 0x00a50800;
 323 imm32 r6, 0x00a60800;
 324 imm32 r7, 0x00a70800;
 325 R5.H = R0.H << 0;
 326 R6.H = R1.H << 1;
 327 R7.H = R2.H << 2;
 328 R0.H = R3.H << 3;
 329 R1.H = R4.H << 4;
 330 R2.H = R5.H << 5;
 331 R3.H = R6.H << 6;
 332 R4.H = R7.H << 7;
 333 CHECKREG r0, 0x05180800;
 334 CHECKREG r1, 0x0A400800;
 335 CHECKREG r2, 0x14000800;
 336 CHECKREG r3, 0x50800800;
 337 CHECKREG r4, 0x44000800;
 338 CHECKREG r5, 0x00A00800;
 339 CHECKREG r6, 0x01420800;
 340 CHECKREG r7, 0x02880800;
 341
 342 imm32 r0, 0x0c010000;
 343 imm32 r1, 0x0c010001;
 344 imm32 r2, 0x0c020000;
 345 imm32 r3, 0x0c030000;
 346 imm32 r4, 0x0c040000;
 347 imm32 r5, 0x0c050000;
 348 imm32 r6, 0x0c060000;
 349 imm32 r7, 0x0c070000;
 350 R6.H = R0.H << 8;
 351 R7.H = R1.H << 9;
 352 R0.H = R2.H << 10;
 353 R1.H = R3.H << 11;
 354 R2.H = R4.H << 12;
 355 R3.H = R5.H << 13;
 356 R4.H = R6.H << 14;
 357 R5.H = R7.H << 15;
 358 CHECKREG r0, 0x08000000;
 359 CHECKREG r1, 0x18000001;
 360 CHECKREG r2, 0x40000000;
 361 CHECKREG r3, 0xA0000000;
 362 CHECKREG r4, 0x00000000;
 363 CHECKREG r5, 0x00000000;
 364 CHECKREG r6, 0x01000000;
 365 CHECKREG r7, 0x02000000;
 366
 367
 368 imm32 r0, 0x00b10000;
 369 imm32 r1, 0x00b10000;
 370 imm32 r2, 0x00b2000f;
 371 imm32 r3, 0x00b30000;
 372 imm32 r4, 0x00b40000;
 373 imm32 r5, 0x00b50000;
 374 imm32 r6, 0x00b60000;
 375 imm32 r7, 0x00b70000;
 376 R7.L = R0.H << 0;
 377 R0.L = R1.H << 1;
 378 R1.L = R2.H << 2;
 379 R2.L = R3.H << 3;
 380 R3.L = R4.H << 4;
 381 R4.L = R5.H << 5;
 382 R5.L = R6.H << 6;
 383 R6.L = R7.H << 7;
 384 CHECKREG r0, 0x00B10162;
 385 CHECKREG r1, 0x00B102C8;
 386 CHECKREG r2, 0x00B20598;
 387 CHECKREG r3, 0x00B30B40;
 388 CHECKREG r4, 0x00B416A0;
 389 CHECKREG r5, 0x00B52D80;
 390 CHECKREG r6, 0x00B65B80;
 391 CHECKREG r7, 0x00B700B1;
 392
 393 imm32 r0, 0x0a010700;
 394 imm32 r1, 0x0a010700;
 395 imm32 r2, 0x0a020700;
 396 imm32 r3, 0x0a030710;
 397 imm32 r4, 0x0a040700;
 398 imm32 r5, 0x0a050700;
 399 imm32 r6, 0x0a060700;
 400 imm32 r7, 0x0a070700;
 401 R0.H = R0.H << 8;
 402 R1.H = R1.H << 9;
 403 R2.H = R2.H << 10;
 404 R3.H = R3.H << 11;
 405 R4.H = R4.H << 12;
 406 R5.H = R5.H << 13;
 407 R6.H = R6.H << 14;
 408 R7.H = R7.H << 15;
 409 CHECKREG r0, 0x01000700;
 410 CHECKREG r1, 0x02000700;
 411 CHECKREG r2, 0x08000700;
 412 CHECKREG r3, 0x18000710;
 413 CHECKREG r4, 0x40000700;
 414 CHECKREG r5, 0xA0000700;
 415 CHECKREG r6, 0x80000700;
 416 CHECKREG r7, 0x80000700;
 417
 418 pass