sim/testsuite/bfin/c_dsp32shiftim_lhalf_rp.s

   1 //Original:/testcases/core/c_dsp32shiftim_lhalf_rp/c_dsp32shiftim_lhalf_rp.dsp
   2 // Spec Reference: dspshiftimm dreg_lo(hi) = lshift (dreg_lo(hi) by imm5)
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9
  10 // lshift : positive data, count (+)=left (half reg)
  11 // d_lo = lshift (d_lo BY d_lo)
  12 // RLx by RLx
  13 imm32 r0, 0x00000000;
  14 R0.L = -1;
  15 imm32 r1, 0x90000001;
  16 imm32 r2, 0x90000002;
  17 imm32 r3, 0x90000003;
  18 imm32 r4, 0x90000004;
  19 imm32 r5, 0x90000005;
  20 imm32 r6, 0x90000006;
  21 imm32 r7, 0x90000007;
  22 R0.L = R0.L << 0;
  23 R1.L = R1.L >> 1;
  24 R2.L = R2.L >> 2;
  25 R3.L = R3.L >> 3;
  26 R4.L = R4.L >> 4;
  27 R5.L = R5.L >> 5;
  28 R6.L = R6.L >> 6;
  29 R7.L = R7.L >> 7;
  30 CHECKREG r0, 0x0000FFFF;
  31 CHECKREG r1, 0x90000000;
  32 CHECKREG r2, 0x90000000;
  33 CHECKREG r3, 0x90000000;
  34 CHECKREG r4, 0x90000000;
  35 CHECKREG r5, 0x90000000;
  36 CHECKREG r6, 0x90000000;
  37 CHECKREG r7, 0x90000000;
  38
  39 imm32 r0, 0x00001001;
  40 R1.L = -1;
  41 imm32 r2, 0xa0002002;
  42 imm32 r3, 0xa0003003;
  43 imm32 r4, 0xa0004004;
  44 imm32 r5, 0xa0005005;
  45 imm32 r6, 0xa0006006;
  46 imm32 r7, 0xa0007007;
  47 R0.L = R0.L >> 1;
  48 R1.L = R1.L >> 1;
  49 R2.L = R2.L >> 1;
  50 R3.L = R3.L >> 1;
  51 R4.L = R4.L >> 1;
  52 R5.L = R5.L >> 1;
  53 R6.L = R6.L >> 1;
  54 R7.L = R7.L >> 1;
  55 CHECKREG r0, 0x00000800;
  56 CHECKREG r1, 0x90007FFF;
  57 CHECKREG r2, 0xA0001001;
  58 CHECKREG r3, 0xA0001801;
  59 CHECKREG r4, 0xA0002002;
  60 CHECKREG r5, 0xA0002802;
  61 CHECKREG r6, 0xA0003003;
  62 CHECKREG r7, 0xA0003803;
  63
  64
  65 imm32 r0, 0xb0001001;
  66 imm32 r1, 0xb0001001;
  67 R2.L = -15;
  68 imm32 r3, 0xb0003003;
  69 imm32 r4, 0xb0004004;
  70 imm32 r5, 0xb0005005;
  71 imm32 r6, 0xb0006006;
  72 imm32 r7, 0xb0007007;
  73 R0.L = R0.L >> 15;
  74 R1.L = R1.L >> 15;
  75 R2.L = LSHIFT R2.L BY R2.L;
  76 R3.L = R3.L >> 15;
  77 R4.L = R4.L >> 15;
  78 R5.L = R5.L >> 15;
  79 R6.L = R6.L >> 15;
  80 R7.L = R7.L >> 15;
  81 CHECKREG r0, 0xb0000000;
  82 CHECKREG r1, 0xb0000000;
  83 CHECKREG r2, 0xA0000001;
  84 CHECKREG r3, 0xB0000000;
  85 CHECKREG r4, 0xb0000000;
  86 CHECKREG r5, 0xb0000000;
  87 CHECKREG r6, 0xb0000000;
  88 CHECKREG r7, 0xB0000000;
  89
  90 imm32 r0, 0xc0001001;
  91 imm32 r1, 0xc0001001;
  92 imm32 r2, 0xc0002002;
  93 R3.L = -16;
  94 imm32 r4, 0xc0004004;
  95 imm32 r5, 0xc0005005;
  96 imm32 r6, 0xc0006006;
  97 imm32 r7, 0xc0007007;
  98 R0.L = R0.L >> 13;
  99 R1.L = R1.L >> 13;
 100 R2.L = R2.L >> 13;
 101 R3.L = R3.L >> 13;
 102 R4.L = R4.L >> 13;
 103 R5.L = R5.L >> 13;
 104 R6.L = R6.L >> 13;
 105 R7.L = R7.L >> 13;
 106 CHECKREG r0, 0xc0000000;
 107 CHECKREG r1, 0xc0000000;
 108 CHECKREG r2, 0xC0000001;
 109 CHECKREG r3, 0xB0000007;
 110 CHECKREG r4, 0xC0000002;
 111 CHECKREG r5, 0xC0000002;
 112 CHECKREG r6, 0xC0000003;
 113 CHECKREG r7, 0xC0000003;
 114
 115 // RHx by RLx
 116 imm32 r0, 0x0000c000;
 117 imm32 r1, 0x0001c000;
 118 imm32 r2, 0x0002c000;
 119 imm32 r3, 0x0003c000;
 120 imm32 r4, 0x0004c000;
 121 imm32 r5, 0x0005c000;
 122 imm32 r6, 0x0006c000;
 123 imm32 r7, 0x0007c000;
 124 R0.L = R0.H << 0;
 125 R1.L = R1.H << 0;
 126 R2.L = R2.H << 0;
 127 R3.L = R3.H << 0;
 128 R4.L = R4.H << 0;
 129 R5.L = R5.H << 0;
 130 R6.L = R6.H << 0;
 131 R7.L = R7.H << 0;
 132 CHECKREG r0, 0x00000000;
 133 CHECKREG r1, 0x00010001;
 134 CHECKREG r2, 0x00020002;
 135 CHECKREG r3, 0x00030003;
 136 CHECKREG r4, 0x00040004;
 137 CHECKREG r5, 0x00050005;
 138 CHECKREG r6, 0x00060006;
 139 CHECKREG r7, 0x00070007;
 140
 141 imm32 r0, 0x10010000;
 142 R1.L = -1;
 143 imm32 r2, 0x20020000;
 144 imm32 r3, 0x30030000;
 145 imm32 r4, 0x40040000;
 146 imm32 r5, 0x50050000;
 147 imm32 r6, 0x60060000;
 148 imm32 r7, 0x70070000;
 149 R0.L = R0.H >> 1;
 150 R1.L = R1.H >> 1;
 151 R2.L = R2.H >> 1;
 152 R3.L = R3.H >> 1;
 153 R4.L = R4.H >> 1;
 154 R5.L = R5.H >> 1;
 155 R6.L = R6.H >> 1;
 156 R7.L = R7.H >> 1;
 157 CHECKREG r0, 0x10010800;
 158 CHECKREG r1, 0x00010000;
 159 CHECKREG r2, 0x20021001;
 160 CHECKREG r3, 0x30031801;
 161 CHECKREG r4, 0x40042002;
 162 CHECKREG r5, 0x50052802;
 163 CHECKREG r6, 0x60063003;
 164 CHECKREG r7, 0x70073803;
 165
 166
 167 imm32 r0, 0x1001e000;
 168 imm32 r1, 0x1001e000;
 169 R2.L = -15;
 170 imm32 r3, 0x3003e000;
 171 imm32 r4, 0x4004e000;
 172 imm32 r5, 0x5005e000;
 173 imm32 r6, 0x6006e000;
 174 imm32 r7, 0x7007e000;
 175 R0.L = R0.H >> 15;
 176 R1.L = R1.H >> 15;
 177 R2.L = R2.H >> 15;
 178 R3.L = R3.H >> 15;
 179 R4.L = R4.H >> 15;
 180 R5.L = R5.H >> 15;
 181 R6.L = R6.H >> 15;
 182 R7.L = R7.H >> 15;
 183 CHECKREG r0, 0x10010000;
 184 CHECKREG r1, 0x10010000;
 185 CHECKREG r2, 0x20020000;
 186 CHECKREG r3, 0x30030000;
 187 CHECKREG r4, 0x40040000;
 188 CHECKREG r5, 0x50050000;
 189 CHECKREG r6, 0x60060000;
 190 CHECKREG r7, 0x70070000;
 191
 192 imm32 r0, 0x1001f001;
 193 imm32 r1, 0x1001f001;
 194 imm32 r2, 0x2002f002;
 195 R3.L = -16;
 196 imm32 r4, 0x4004f004;
 197 imm32 r5, 0x5005f005;
 198 imm32 r6, 0x6006f006;
 199 imm32 r7, 0x7007f007;
 200 R0.L = R0.H >> 13;
 201 R1.L = R1.H >> 13;
 202 R2.L = R2.H >> 13;
 203 R3.L = R3.H >> 13;
 204 R4.L = R4.H >> 13;
 205 R5.L = R5.H >> 13;
 206 R6.L = R6.H >> 13;
 207 R7.L = R7.H >> 13;
 208 CHECKREG r0, 0x10010000;
 209 CHECKREG r1, 0x10010000;
 210 CHECKREG r2, 0x20020001;
 211 CHECKREG r3, 0x30030001;
 212 CHECKREG r4, 0x40040002;
 213 CHECKREG r5, 0x50050002;
 214 CHECKREG r6, 0x60060003;
 215 CHECKREG r7, 0x70070003;
 216
 217 // RLx by RLx
 218 imm32 r0, 0x00001001;
 219 imm32 r1, 0x00001001;
 220 imm32 r2, 0x00001002;
 221 imm32 r3, 0x00001003;
 222 imm32 r4, 0x00001000;
 223 imm32 r5, 0x00001005;
 224 imm32 r6, 0x00001006;
 225 imm32 r7, 0x00001007;
 226 R0.H = R0.L >> 14;
 227 R1.H = R1.L >> 14;
 228 R2.H = R2.L >> 14;
 229 R3.H = R3.L >> 14;
 230 R4.H = R4.L >> 14;
 231 R5.H = R5.L >> 14;
 232 R6.H = R6.L >> 14;
 233 R7.H = R7.L >> 14;
 234 CHECKREG r0, 0x00001001;
 235 CHECKREG r1, 0x00001001;
 236 CHECKREG r2, 0x00001002;
 237 CHECKREG r3, 0x00001003;
 238 CHECKREG r4, 0x00001000;
 239 CHECKREG r5, 0x00001005;
 240 CHECKREG r6, 0x00001006;
 241 CHECKREG r7, 0x00001007;
 242
 243 imm32 r0, 0x00002001;
 244 imm32 r1, 0x00002001;
 245 imm32 r2, 0x00002002;
 246 imm32 r3, 0x00002003;
 247 imm32 r4, 0x00002004;
 248 R5.L = -1;
 249 imm32 r6, 0x00000006;
 250 imm32 r7, 0x00000007;
 251 R0.H = R0.L >> 5;
 252 R1.H = R1.L >> 5;
 253 R2.H = R2.L >> 5;
 254 R3.H = R3.L >> 5;
 255 R4.H = R4.L >> 5;
 256 R5.H = R5.L >> 5;
 257 R6.H = R6.L >> 5;
 258 R7.H = R7.L >> 5;
 259 CHECKREG r0, 0x01002001;
 260 CHECKREG r1, 0x01002001;
 261 CHECKREG r2, 0x01002002;
 262 CHECKREG r3, 0x01002003;
 263 CHECKREG r4, 0x01002004;
 264 CHECKREG r5, 0x07FFFFFF;
 265 CHECKREG r6, 0x00000006;
 266 CHECKREG r7, 0x00000007;
 267
 268
 269 imm32 r0, 0x30001001;
 270 imm32 r1, 0x30001001;
 271 imm32 r1, 0x30002002;
 272 imm32 r3, 0x30003003;
 273 imm32 r4, 0x30004004;
 274 imm32 r5, 0x30005005;
 275 R6.L = -15;
 276 imm32 r7, 0x00007007;
 277 R0.H = R0.L >> 15;
 278 R1.H = R1.L >> 15;
 279 R2.H = R2.L >> 15;
 280 R3.H = R3.L >> 15;
 281 R4.H = R4.L >> 15;
 282 R5.H = R5.L >> 15;
 283 R6.H = R6.L >> 15;
 284 R7.H = R7.L >> 15;
 285 CHECKREG r0, 0x00001001;
 286 CHECKREG r1, 0x00002002;
 287 CHECKREG r2, 0x00002002;
 288 CHECKREG r3, 0x00003003;
 289 CHECKREG r4, 0x00004004;
 290 CHECKREG r5, 0x00005005;
 291 CHECKREG r6, 0x0001FFF1;
 292 CHECKREG r7, 0x00007007;
 293
 294 imm32 r0, 0x40001001;
 295 imm32 r1, 0x40002001;
 296 imm32 r2, 0x40002002;
 297 imm32 r3, 0x40003003;
 298 imm32 r4, 0x40004004;
 299 imm32 r5, 0x40005005;
 300 imm32 r6, 0x40006006;
 301 R7.L = -16;
 302 R0.H = R0.L >> 7;
 303 R1.H = R1.L >> 7;
 304 R2.H = R2.L >> 7;
 305 R3.H = R3.L >> 7;
 306 R4.H = R4.L >> 7;
 307 R5.H = R5.L >> 7;
 308 R6.H = R6.L >> 7;
 309 R7.H = R7.L >> 7;
 310 CHECKREG r0, 0x00201001;
 311 CHECKREG r1, 0x00402001;
 312 CHECKREG r2, 0x00402002;
 313 CHECKREG r3, 0x00603003;
 314 CHECKREG r4, 0x00804004;
 315 CHECKREG r5, 0x00A05005;
 316 CHECKREG r6, 0x00C06006;
 317 CHECKREG r7, 0x01FFFFF0;
 318
 319 // RHx by RLx
 320 imm32 r0, 0x50010000;
 321 imm32 r1, 0x50010000;
 322 imm32 r2, 0x50020000;
 323 imm32 r3, 0x50030000;
 324 R4.L = -1;
 325 imm32 r5, 0x50050000;
 326 imm32 r6, 0x50060000;
 327 imm32 r7, 0x50070000;
 328 R0.H = R0.H >> 1;
 329 R1.H = R1.H >> 1;
 330 R2.H = R2.H >> 1;
 331 R3.H = R3.H >> 1;
 332 R4.H = R4.H >> 1;
 333 R5.H = R5.H >> 1;
 334 R6.H = R6.H >> 1;
 335 R7.H = R7.H >> 1;
 336 CHECKREG r0, 0x28000000;
 337 CHECKREG r1, 0x28000000;
 338 CHECKREG r2, 0x28010000;
 339 CHECKREG r3, 0x28010000;
 340 CHECKREG r4, 0x0040FFFF;
 341 CHECKREG r5, 0x28020000;
 342 CHECKREG r6, 0x28030000;
 343 CHECKREG r7, 0x28030000;
 344
 345 imm32 r0, 0x10010000;
 346 imm32 r1, 0x10010000;
 347 imm32 r2, 0x20020000;
 348 imm32 r3, 0x30030000;
 349 imm32 r4, 0x40040000;
 350 R5.L = -1;
 351 imm32 r6, 0x60060000;
 352 imm32 r7, 0x70070000;
 353 R0.H = R0.H >> 5;
 354 R1.H = R1.H >> 5;
 355 R2.H = R2.H >> 5;
 356 R3.H = R3.H >> 5;
 357 R4.H = R4.H >> 5;
 358 R5.H = R5.H >> 5;
 359 R6.H = R6.H >> 5;
 360 R7.H = R7.H >> 5;
 361 CHECKREG r0, 0x00800000;
 362 CHECKREG r1, 0x00800000;
 363 CHECKREG r2, 0x01000000;
 364 CHECKREG r3, 0x01800000;
 365 CHECKREG r4, 0x02000000;
 366 CHECKREG r5, 0x0140FFFF;
 367 CHECKREG r6, 0x03000000;
 368 CHECKREG r7, 0x03800000;
 369
 370
 371 imm32 r0, 0x10010000;
 372 imm32 r1, 0x10010000;
 373 imm32 r2, 0x20020000;
 374 imm32 r3, 0x30030000;
 375 imm32 r4, 0x40040000;
 376 imm32 r5, 0x50050000;
 377 R6.L = -15;
 378 imm32 r7, 0x70070000;
 379 R0.L = R0.H >> 6;
 380 R1.L = R1.H >> 6;
 381 R2.L = R2.H >> 6;
 382 R3.L = R3.H >> 6;
 383 R4.L = R4.H >> 6;
 384 R5.L = R5.H >> 6;
 385 R6.L = R6.H >> 6;
 386 R7.L = R7.H >> 6;
 387 CHECKREG r0, 0x10010040;
 388 CHECKREG r1, 0x10010040;
 389 CHECKREG r2, 0x20020080;
 390 CHECKREG r3, 0x300300C0;
 391 CHECKREG r4, 0x40040100;
 392 CHECKREG r5, 0x50050140;
 393 CHECKREG r6, 0x0300000C;
 394 CHECKREG r7, 0x700701C0;
 395
 396 imm32 r0, 0x10010000;
 397 imm32 r1, 0x10010000;
 398 imm32 r2, 0x20020000;
 399 imm32 r2, 0x30030000;
 400 imm32 r4, 0x40040000;
 401 imm32 r5, 0x50050000;
 402 imm32 r6, 0x60060000;
 403 R7.L = -16;
 404 R0.H = R0.H >> 15;
 405 R1.H = R1.H >> 15;
 406 R2.H = R2.H >> 15;
 407 R3.H = R3.H >> 15;
 408 R4.H = R4.H >> 15;
 409 R5.H = R5.H >> 15;
 410 R6.H = R6.H >> 15;
 411 R7.H = R7.H >> 15;
 412 CHECKREG r0, 0x00000000;
 413 CHECKREG r1, 0x00000000;
 414 CHECKREG r2, 0x00000000;
 415 CHECKREG r3, 0x000000C0;
 416 CHECKREG r4, 0x00000000;
 417 CHECKREG r5, 0x00000000;
 418 CHECKREG r6, 0x00000000;
 419 CHECKREG r7, 0x0000FFF0;
 420
 421 pass