1 //Original
:/testcases
/core
/c_dspldst_ld_dr_ippm
/c_dspldst_ld_dr_ippm.dsp
2 // Spec Reference
: c_dspldst ld_dr_i+
+m
5 .include "testutils.inc"
15 loadsym i0
, DATA_ADDR_3;
16 loadsym i1
, DATA_ADDR_4;
17 loadsym i2
, DATA_ADDR_5;
18 loadsym i3
, DATA_ADDR_6;
28 CHECKREG
r0, 0x00010203;
29 CHECKREG
r1, 0x20212223;
30 CHECKREG
r2, 0x40414243;
31 CHECKREG
r3, 0x60616263;
32 CHECKREG
r4, 0x00010203;
33 CHECKREG
r5, 0x24252627;
34 CHECKREG
r6, 0x40414243;
35 CHECKREG
r7, 0x64656667;
44 CHECKREG
r0, 0x68696A6B;
45 CHECKREG
r1, 0x04050607;
46 CHECKREG
r2, 0x24252627;
47 CHECKREG
r3, 0x44454647;
48 CHECKREG
r4, 0x64656667;
49 CHECKREG
r5, 0x04050607;
50 CHECKREG
r6, 0x28292A2B;
51 CHECKREG
r7, 0x44454647;
65 CHECKREG
r0, 0x4C4D4E4F;
66 CHECKREG
r1, 0x68696A6B;
67 CHECKREG
r2, 0x08090A0B;
68 CHECKREG
r3, 0x28292A2B;
69 CHECKREG
r4, 0x48494A4B;
70 CHECKREG
r5, 0x68696A6B;
71 CHECKREG
r6, 0x0C0D0E0F;
72 CHECKREG
r7, 0x28292A2B;
82 CHECKREG
r0, 0x2C2D2E2F;
83 CHECKREG
r1, 0x50515253;
84 CHECKREG
r2, 0x6C6D6E6F;
85 CHECKREG
r3, 0x0C0D0E0F;
86 CHECKREG
r4, 0x2C2D2E2F;
87 CHECKREG
r5, 0x4C4D4E4F;
88 CHECKREG
r6, 0x6C6D6E6F;
89 CHECKREG
r7, 0x10111213;
99 CHECKREG
r0, 0x70717273;
100 CHECKREG
r1, 0x14151617;
101 CHECKREG
r2, 0x30313233;
102 CHECKREG
r3, 0x54555657;
103 CHECKREG
r4, 0x70717273;
104 CHECKREG
r5, 0x10111213;
105 CHECKREG
r6, 0x30313233;
106 CHECKREG
r7, 0x50515253;
110 // Pre-load memory with known data
111 // More data is defined than will actually
be used