1 //Original
:/testcases
/core
/c_dspldst_ld_drlo_ipp
/c_dspldst_ld_drlo_ipp.dsp
2 // Spec Reference
: c_dspldst ld_drlo_i+
+/--
5 .include "testutils.inc"
10 loadsym i0
, DATA_ADDR_3;
11 loadsym i1
, DATA_ADDR_4;
12 loadsym i2
, DATA_ADDR_5;
13 loadsym i3
, DATA_ADDR_6;
15 // Load Lower half of Dregs
24 CHECKREG
r0, 0x00000203;
25 CHECKREG
r1, 0x00002223;
26 CHECKREG
r2, 0x00004243;
27 CHECKREG
r3, 0x00006263;
28 CHECKREG
r4, 0x00000001;
29 CHECKREG
r5, 0x00002021;
30 CHECKREG
r6, 0x00004041;
31 CHECKREG
r7, 0x00006061;
41 CHECKREG
r0, 0x00006465;
42 CHECKREG
r1, 0x00000607;
43 CHECKREG
r2, 0x00002627;
44 CHECKREG
r3, 0x00004647;
45 CHECKREG
r4, 0x00006667;
46 CHECKREG
r5, 0x00000405;
47 CHECKREG
r6, 0x00002425;
48 CHECKREG
r7, 0x00004445;
58 CHECKREG
r0, 0x00004849;
59 CHECKREG
r1, 0x00006869;
60 CHECKREG
r2, 0x00000A0B;
61 CHECKREG
r3, 0x00002A2B;
62 CHECKREG
r4, 0x00004A4B;
63 CHECKREG
r5, 0x00006A6B;
64 CHECKREG
r6, 0x00000809;
65 CHECKREG
r7, 0x00002829;
75 CHECKREG
r0, 0x00002C2D;
76 CHECKREG
r1, 0x00004C4D;
77 CHECKREG
r2, 0x00006C6D;
78 CHECKREG
r3, 0x00000E0F;
79 CHECKREG
r4, 0x00002E2F;
80 CHECKREG
r5, 0x00004E4F;
81 CHECKREG
r6, 0x00006E6F;
82 CHECKREG
r7, 0x00000C0D;
84 // reverse to minus mninus i-
-
86 // Load Lower half of Dregs
95 CHECKREG
r0, 0x00001213;
96 CHECKREG
r1, 0x00003233;
97 CHECKREG
r2, 0x00005253;
98 CHECKREG
r3, 0x00007273;
99 CHECKREG
r4, 0x00000C0D;
100 CHECKREG
r5, 0x00002C2D;
101 CHECKREG
r6, 0x00004C4D;
102 CHECKREG
r7, 0x00006C6D;
112 CHECKREG
r0, 0x00006869;
113 CHECKREG
r1, 0x00000E0F;
114 CHECKREG
r2, 0x00002E2F;
115 CHECKREG
r3, 0x00004E4F;
116 CHECKREG
r4, 0x00006E6F;
117 CHECKREG
r5, 0x00000809;
118 CHECKREG
r6, 0x00002829;
119 CHECKREG
r7, 0x00004849;
129 CHECKREG
r0, 0x00004445;
130 CHECKREG
r1, 0x00006465;
131 CHECKREG
r2, 0x00000A0B;
132 CHECKREG
r3, 0x00002A2B;
133 CHECKREG
r4, 0x00004A4B;
134 CHECKREG
r5, 0x00006A6B;
135 CHECKREG
r6, 0x00000405;
136 CHECKREG
r7, 0x00002425;
146 CHECKREG
r0, 0x00002021;
147 CHECKREG
r1, 0x00004041;
148 CHECKREG
r2, 0x00006061;
149 CHECKREG
r3, 0x00000607;
150 CHECKREG
r4, 0x00002627;
151 CHECKREG
r5, 0x00004647;
152 CHECKREG
r6, 0x00006667;
153 CHECKREG
r7, 0x00000001;
157 // Pre-load memory with known data
158 // More data is defined than will actually
be used