sim/testsuite/bfin/c_ldimmhalf_dreg.s

   1 //Original:/testcases/core/c_ldimmhalf_dreg/c_ldimmhalf_dreg.dsp
   2 // Spec Reference: ldimmhalf dreg imm16
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9
  10 INIT_R_REGS -1;
  11
  12 // test Dreg
  13 R0 = 0x0123 (X);
  14 R1 = 0x1234 (X);
  15 R2 = 0x2345 (X);
  16 R3 = 0x3456 (X);
  17 R4 = 0x4567 (X);
  18 R5 = 0x5678 (X);
  19 R6 = 0x6789 (X);
  20 R7 = 0x789a (X);
  21 CHECKREG r0, 0x00000123;
  22 CHECKREG r1, 0x00001234;
  23 CHECKREG r2, 0x00002345;
  24 CHECKREG r3, 0x00003456;
  25 CHECKREG r4, 0x00004567;
  26 CHECKREG r5, 0x00005678;
  27 CHECKREG r6, 0x00006789;
  28 CHECKREG r7, 0x0000789A;
  29
  30 R0 = -32768 (X);
  31 R1 = -1111 (X);
  32 R2 = -2222 (X);
  33 R3 = -3333 (X);
  34 R4 = -4444 (X);
  35 R5 = -5555 (X);
  36 R6 = -6666 (X);
  37 R7 = -7777 (X);
  38 CHECKREG r0, 0xFFFF8000;
  39 CHECKREG r1, 0xFFFFFBA9;
  40 CHECKREG r2, 0xFFFFF752;
  41 CHECKREG r3, 0xFFFFF2FB;
  42 CHECKREG r4, 0xFFFFEEA4;
  43 CHECKREG r5, 0xFFFFEA4D;
  44 CHECKREG r6, 0xFFFFE5F6;
  45 CHECKREG r7, 0xFFFFE19F;
  46
  47 R0 = 0x7fff (X);
  48 R1 = 0x7ffe (X);
  49 R2 = 32767 (X);
  50 R3 = 32766 (X);
  51 R4 = -32768 (X);
  52 R5 = -32767 (X);
  53 CHECKREG r0, 0x00007fff;
  54 CHECKREG r1, 0x00007ffe;
  55 CHECKREG r2, 0x00007fff;
  56 CHECKREG r3, 0x00007ffe;
  57 CHECKREG r4, 0xFFFF8000;
  58 CHECKREG r5, 0xFFFF8001;
  59
  60 pass