sim/testsuite/bfin/c_ldimmhalf_h_ibml.s

   1 //Original:/proj/frio/dv/testcases/core/c_ldimmhalf_h_ibml/c_ldimmhalf_h_ibml.dsp
   2 // Spec Reference: ldimmhalf h ibml
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8         INIT_I_REGS -1;
   9         INIT_L_REGS -1;
  10         INIT_B_REGS -1;
  11         INIT_M_REGS -1;
  12
  13         I0.H = 0x2000;
  14         I1.H = 0x2002;
  15         I2.H = 0x2004;
  16         I3.H = 0x2006;
  17         L0.H = 0x2008;
  18         L1.H = 0x200a;
  19         L2.H = 0x200c;
  20         L3.H = 0x200e;
  21
  22         R0 = I0;
  23         R1 = I1;
  24         R2 = I2;
  25         R3 = I3;
  26         R4 = L0;
  27         R5 = L1;
  28         R6 = L2;
  29         R7 = L3;
  30         CHECKREG r0, 0x2000ffff;
  31         CHECKREG r1, 0x2002ffff;
  32         CHECKREG r2, 0x2004ffff;
  33         CHECKREG r3, 0x2006ffff;
  34         CHECKREG r4, 0x2008ffff;
  35         CHECKREG r5, 0x200affff;
  36         CHECKREG r6, 0x200cffff;
  37         CHECKREG r7, 0x200effff;
  38
  39         I0.H = 0x0111;
  40         I1.H = 0x1111;
  41         I2.H = 0x2222;
  42         I3.H = 0x3333;
  43         L0.H = 0x4444;
  44         L1.H = 0x5555;
  45         L2.H = 0x6666;
  46         L3.H = 0x7777;
  47         R0 = I0;
  48         R1 = I1;
  49         R2 = I2;
  50         R3 = I3;
  51         R4 = L0;
  52         R5 = L1;
  53         R6 = L2;
  54         R7 = L3;
  55         CHECKREG r0, 0x0111ffff;
  56         CHECKREG r1, 0x1111ffff;
  57         CHECKREG r2, 0x2222ffff;
  58         CHECKREG r3, 0x3333ffff;
  59         CHECKREG r4, 0x4444ffff;
  60         CHECKREG r5, 0x5555ffff;
  61         CHECKREG r6, 0x6666ffff;
  62         CHECKREG r7, 0x7777ffff;
  63
  64         I0.H = 0x8888;
  65         I1.H = 0x9aaa;
  66         I2.H = 0xabbb;
  67         I3.H = 0xbccc;
  68         L0.H = 0xcddd;
  69         L1.H = 0xdeee;
  70         L2.H = 0xefff;
  71         L3.H = 0xf111;
  72         R0 = I0;
  73         R1 = I1;
  74         R2 = I2;
  75         R3 = I3;
  76         R4 = L0;
  77         R5 = L1;
  78         R6 = L2;
  79         R7 = L3;
  80         CHECKREG r0, 0x8888ffff;
  81         CHECKREG r1, 0x9aaaffff;
  82         CHECKREG r2, 0xabbbffff;
  83         CHECKREG r3, 0xbcccffff;
  84         CHECKREG r4, 0xcdddffff;
  85         CHECKREG r5, 0xdeeeffff;
  86         CHECKREG r6, 0xefffffff;
  87         CHECKREG r7, 0xf111ffff;
  88
  89         B0.H = 0x3000;
  90         B1.H = 0x3002;
  91         B2.H = 0x3004;
  92         B3.H = 0x3006;
  93         M0.H = 0x3008;
  94         M1.H = 0x300a;
  95         M2.H = 0x300c;
  96         M3.H = 0x300e;
  97
  98         R0 = B0;
  99         R1 = B1;
 100         R2 = B2;
 101         R3 = B3;
 102         R4 = M0;
 103         R5 = M1;
 104         R6 = M2;
 105         R7 = M3;
 106         CHECKREG r0, 0x3000ffff;
 107         CHECKREG r1, 0x3002ffff;
 108         CHECKREG r2, 0x3004ffff;
 109         CHECKREG r3, 0x3006ffff;
 110         CHECKREG r4, 0x3008ffff;
 111         CHECKREG r5, 0x300Affff;
 112         CHECKREG r6, 0x300cffff;
 113         CHECKREG r7, 0x300effff;
 114
 115         B0.H = 0x0110;
 116         B1.H = 0x1110;
 117         B2.H = 0x2220;
 118         B3.H = 0x3330;
 119         M0.H = 0x4440;
 120         M1.H = 0x5550;
 121         M2.H = 0x6660;
 122         M3.H = 0x7770;
 123         R0 = B0;
 124         R1 = B1;
 125         R2 = B2;
 126         R3 = B3;
 127         R4 = M0;
 128         R5 = M1;
 129         R6 = M2;
 130         R7 = M3;
 131         CHECKREG r0, 0x0110FFFF;
 132         CHECKREG r1, 0x1110FFFF;
 133         CHECKREG r2, 0x2220FFFF;
 134         CHECKREG r3, 0x3330FFFF;
 135         CHECKREG r4, 0x4440FFFF;
 136         CHECKREG r5, 0x5550FFFF;
 137         CHECKREG r6, 0x6660FFFF;
 138         CHECKREG r7, 0x7770FFFF;
 139
 140         B0.H = 0xf880;
 141         B1.H = 0xfaa0;
 142         B2.H = 0xfbb0;
 143         B3.H = 0xfcc0;
 144         M0.H = 0xfdd0;
 145         M1.H = 0xfee0;
 146         M2.H = 0xfff0;
 147         M3.H = 0xf110;
 148         R0 = B0;
 149         R1 = B1;
 150         R2 = B2;
 151         R3 = B3;
 152         R4 = M0;
 153         R5 = M1;
 154         R6 = M2;
 155         R7 = M3;
 156         CHECKREG r0, 0xf880ffff;
 157         CHECKREG r1, 0xfaa0ffff;
 158         CHECKREG r2, 0xfbb0ffff;
 159         CHECKREG r3, 0xfcc0ffff;
 160         CHECKREG r4, 0xfdd0ffff;
 161         CHECKREG r5, 0xfee0ffff;
 162         CHECKREG r6, 0xfff0ffff;
 163         CHECKREG r7, 0xf110ffff;
 164
 165         pass