sim/testsuite/bfin/c_ldimmhalf_l_dr.s

   1 //Original:/testcases/core/c_ldimmhalf_l_dr/c_ldimmhalf_l_dr.dsp
   2 // Spec Reference: ldimmhalf l dreg
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9
  10 INIT_R_REGS -1;
  11
  12
  13 // test Dreg
  14 R0.L = 0x0001;
  15 R1.L = 0x0003;
  16 R2.L = 0x0005;
  17 R3.L = 0x0007;
  18 R4.L = 0x0009;
  19 R5.L = 0x000b;
  20 R6.L = 0x000d;
  21 R7.L = 0x000f;
  22 CHECKREG r0, 0xffff0001;
  23 CHECKREG r1, 0xffff0003;
  24 CHECKREG r2, 0xffff0005;
  25 CHECKREG r3, 0xffff0007;
  26 CHECKREG r4, 0xffff0009;
  27 CHECKREG r5, 0xffff000b;
  28 CHECKREG r6, 0xffff000d;
  29 CHECKREG r7, 0xffff000f;
  30
  31 R0.L = 0x0010;
  32 R1.L = 0x0030;
  33 R2.L = 0x0050;
  34 R3.L = 0x0070;
  35 R4.L = 0x0090;
  36 R5.L = 0x00b0;
  37 R6.L = 0x00d0;
  38 R7.L = 0x00f0;
  39 CHECKREG r0, 0xffff0010;
  40 CHECKREG r1, 0xffff0030;
  41 CHECKREG r2, 0xffff0050;
  42 CHECKREG r3, 0xffff0070;
  43 CHECKREG r4, 0xffff0090;
  44 CHECKREG r5, 0xffff00b0;
  45 CHECKREG r6, 0xffff00d0;
  46 CHECKREG r7, 0xffff00f0;
  47
  48 R0.L = 0x0100;
  49 R1.L = 0x0300;
  50 R2.L = 0x0500;
  51 R3.L = 0x0700;
  52 R4.L = 0x0900;
  53 R5.L = 0x0b00;
  54 R6.L = 0x0d00;
  55 R7.L = 0x0f00;
  56 CHECKREG r0, 0xffff0100;
  57 CHECKREG r1, 0xffff0300;
  58 CHECKREG r2, 0xffff0500;
  59 CHECKREG r3, 0xffff0700;
  60 CHECKREG r4, 0xffff0900;
  61 CHECKREG r5, 0xffff0b00;
  62 CHECKREG r6, 0xffff0d00;
  63 CHECKREG r7, 0xffff0f00;
  64
  65 R0.L = 0x1000;
  66 R1.L = 0x3000;
  67 R2.L = 0x5000;
  68 R3.L = 0x7000;
  69 R4.L = 0x9000;
  70 R5.L = 0xb000;
  71 R6.L = 0xd000;
  72 R7.L = 0xf000;
  73 CHECKREG r0, 0xffff1000;
  74 CHECKREG r1, 0xffff3000;
  75 CHECKREG r2, 0xffff5000;
  76 CHECKREG r3, 0xffff7000;
  77 CHECKREG r4, 0xffff9000;
  78 CHECKREG r5, 0xffffb000;
  79 CHECKREG r6, 0xffffd000;
  80 CHECKREG r7, 0xfffff000;
  81
  82 pass