sim/testsuite/bfin/c_ldimmhalf_lz_dr.s

   1 //Original:/testcases/core/c_ldimmhalf_lz_dr/c_ldimmhalf_lz_dr.dsp
   2 // Spec Reference: ldimmhalf lz dreg
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9 INIT_R_REGS -1;
  10
  11
  12 // test Dreg
  13 R0 = 0x0001 (Z);
  14 R1 = 0x0003 (Z);
  15 R2 = 0x0005 (Z);
  16 R3 = 0x0007 (Z);
  17 R4 = 0x0009 (Z);
  18 R5 = 0x000b (Z);
  19 R6 = 0x000d (Z);
  20 R7 = 0x000f (Z);
  21 CHECKREG r0, 0x00000001;
  22 CHECKREG r1, 0x00000003;
  23 CHECKREG r2, 0x00000005;
  24 CHECKREG r3, 0x00000007;
  25 CHECKREG r4, 0x00000009;
  26 CHECKREG r5, 0x0000000b;
  27 CHECKREG r6, 0x0000000d;
  28 CHECKREG r7, 0x0000000f;
  29
  30 R0 = 0x0010 (Z);
  31 R1 = 0x0030 (Z);
  32 R2 = 0x0050 (Z);
  33 R3 = 0x0070 (Z);
  34 R4 = 0x0090 (Z);
  35 R5 = 0x00b0 (Z);
  36 R6 = 0x00d0 (Z);
  37 R7 = 0x00f0 (Z);
  38 CHECKREG r0, 0x00000010;
  39 CHECKREG r1, 0x00000030;
  40 CHECKREG r2, 0x00000050;
  41 CHECKREG r3, 0x00000070;
  42 CHECKREG r4, 0x00000090;
  43 CHECKREG r5, 0x000000b0;
  44 CHECKREG r6, 0x000000d0;
  45 CHECKREG r7, 0x000000f0;
  46
  47 R0 = 0x0100 (Z);
  48 R1 = 0x0300 (Z);
  49 R2 = 0x0500 (Z);
  50 R3 = 0x0700 (Z);
  51 R4 = 0x0900 (Z);
  52 R5 = 0x0b00 (Z);
  53 R6 = 0x0d00 (Z);
  54 R7 = 0x0f00 (Z);
  55 CHECKREG r0, 0x00000100;
  56 CHECKREG r1, 0x00000300;
  57 CHECKREG r2, 0x00000500;
  58 CHECKREG r3, 0x00000700;
  59 CHECKREG r4, 0x00000900;
  60 CHECKREG r5, 0x00000b00;
  61 CHECKREG r6, 0x00000d00;
  62 CHECKREG r7, 0x00000f00;
  63
  64 R0 = 0x1000 (Z);
  65 R1 = 0x3000 (Z);
  66 R2 = 0x5000 (Z);
  67 R3 = 0x7000 (Z);
  68 R4 = 0x9000 (Z);
  69 R5 = 0xb000 (Z);
  70 R6 = 0xd000 (Z);
  71 R7 = 0xf000 (Z);
  72 CHECKREG r0, 0x00001000;
  73 CHECKREG r1, 0x00003000;
  74 CHECKREG r2, 0x00005000;
  75 CHECKREG r3, 0x00007000;
  76 CHECKREG r4, 0x00009000;
  77 CHECKREG r5, 0x0000b000;
  78 CHECKREG r6, 0x0000d000;
  79 CHECKREG r7, 0x0000f000;
  80
  81 pass