sim/testsuite/bfin/c_ldimmhalf_lzhi_ibml.s

   1 //Original:/testcases/core/c_ldimmhalf_lzhi_ibml/c_ldimmhalf_lzhi_ibml.dsp
   2 # mach: bfin
   3
   4 .include "testutils.inc"
   5         start
   6
   7
   8 // Spec Reference: ldimmhalf lzhi ibml
   9
  10
  11
  12
  13 I0 = 0x2001 (Z);
  14 I0.H = 0x2000;
  15 I1 = 0x2003 (Z);
  16 I1.H = 0x2002;
  17 I2 = 0x2005 (Z);
  18 I2.H = 0x2004;
  19 I3 = 0x2007 (Z);
  20 I3.H = 0x2006;
  21 L0 = 0x2009 (Z);
  22 L0.H = 0x2008;
  23 L1 = 0x200b (Z);
  24 L1.H = 0x200a;
  25 L2 = 0x200d (Z);
  26 L2.H = 0x200c;
  27 L3 = 0x200f (Z);
  28 L3.H = 0x200e;
  29
  30
  31 R0 = I0;
  32 R1 = I1;
  33 R2 = I2;
  34 R3 = I3;
  35 R4 = L0;
  36 R5 = L1;
  37 R6 = L2;
  38 R7 = L3;
  39 CHECKREG r0, 0x20002001;
  40 CHECKREG r1, 0x20022003;
  41 CHECKREG r2, 0x20042005;
  42 CHECKREG r3, 0x20062007;
  43 CHECKREG r4, 0x20082009;
  44 CHECKREG r5, 0x200a200b;
  45 CHECKREG r6, 0x200c200d;
  46 CHECKREG r7, 0x200e200f;
  47
  48 I0 = 0x0111 (Z);
  49 I0.H = 0x1000;
  50 I1 = 0x1111 (Z);
  51 I1.H = 0x1000;
  52 I2 = 0x2222 (Z);
  53 I2.H = 0x2000;
  54 I3 = 0x3333 (Z);
  55 I3.H = 0x3000;
  56 L0 = 0x4444 (Z);
  57 L0.H = 0x4000;
  58 L1 = 0x5555 (Z);
  59 L1.H = 0x5000;
  60 L2 = 0x6666 (Z);
  61 L2.H = 0x6000;
  62 L3 = 0x7777 (Z);
  63 L3.H = 0x7000;
  64 R0 = I0;
  65 R1 = I1;
  66 R2 = I2;
  67 R3 = I3;
  68 R4 = L0;
  69 R5 = L1;
  70 R6 = L2;
  71 R7 = L3;
  72 CHECKREG r0, 0x10000111;
  73 CHECKREG r1, 0x10001111;
  74 CHECKREG r2, 0x20002222;
  75 CHECKREG r3, 0x30003333;
  76 CHECKREG r4, 0x40004444;
  77 CHECKREG r5, 0x50005555;
  78 CHECKREG r6, 0x60006666;
  79 CHECKREG r7, 0x70007777;
  80
  81 I0 = 0x8888 (Z);
  82 I0.H = 0x8000;
  83 I1 = 0x9aaa (Z);
  84 I1.H = 0x9000;
  85 I2 = 0xabbb (Z);
  86 I2.H = 0xa000;
  87 I3 = 0xbccc (Z);
  88 I3.H = 0xb000;
  89 L0 = 0xcddd (Z);
  90 L0.H = 0xc000;
  91 L1 = 0xdeee (Z);
  92 L1.H = 0xd000;
  93 L2 = 0xefff (Z);
  94 L2.H = 0xe000;
  95 L3 = 0xf111 (Z);
  96 L3.H = 0xf000;
  97 R0 = I0;
  98 R1 = I1;
  99 R2 = I2;
 100 R3 = I3;
 101 R4 = L0;
 102 R5 = L1;
 103 R6 = L2;
 104 R7 = L3;
 105 CHECKREG r0, 0x80008888;
 106 CHECKREG r1, 0x90009aaa;
 107 CHECKREG r2, 0xa000abbb;
 108 CHECKREG r3, 0xb000bccc;
 109 CHECKREG r4, 0xc000cddd;
 110 CHECKREG r5, 0xd000deee;
 111 CHECKREG r6, 0xe000efff;
 112 CHECKREG r7, 0xf000f111;
 113
 114 B0 = 0x3001 (Z);
 115 B0.H = 0x3000;
 116 B1 = 0x3003 (Z);
 117 B1.H = 0x3002;
 118 B2 = 0x3005 (Z);
 119 B2.H = 0x3004;
 120 B3 = 0x3007 (Z);
 121 B3.H = 0x3006;
 122 M0 = 0x3009 (Z);
 123 M0.H = 0x3008;
 124 M1 = 0x300b (Z);
 125 M1.H = 0x300a;
 126 M2 = 0x300d (Z);
 127 M2.H = 0x300c;
 128 M3 = 0x300f (Z);
 129 M3.H = 0x300e;
 130
 131 R0 = B0;
 132 R1 = B1;
 133 R2 = B2;
 134 R3 = B3;
 135 R4 = M0;
 136 R5 = M1;
 137 R6 = M2;
 138 R7 = M3;
 139 CHECKREG r0, 0x30003001;
 140 CHECKREG r1, 0x30023003;
 141 CHECKREG r2, 0x30043005;
 142 CHECKREG r3, 0x30063007;
 143 CHECKREG r4, 0x30083009;
 144 CHECKREG r5, 0x300A300B;
 145 CHECKREG r6, 0x300c300d;
 146 CHECKREG r7, 0x300e300f;
 147
 148
 149 B0 = 0x0110 (Z);
 150 B0.H = 0x1000;
 151 B1 = 0x1110 (Z);
 152 B1.H = 0x1000;
 153 B2 = 0x2220 (Z);
 154 B2.H = 0x2000;
 155 B3 = 0x3330 (Z);
 156 B3.H = 0x3000;
 157 M0 = 0x4440 (Z);
 158 M0.H = 0x4000;
 159 M1 = 0x5550 (Z);
 160 M1.H = 0x5000;
 161 M2 = 0x6660 (Z);
 162 M2.H = 0x6000;
 163 M3 = 0x7770 (Z);
 164 M3.H = 0x7000;
 165 R0 = B0;
 166 R1 = B1;
 167 R2 = B2;
 168 R3 = B3;
 169 R4 = M0;
 170 R5 = M1;
 171 R6 = M2;
 172 R7 = M3;
 173 CHECKREG r0, 0x10000110;
 174 CHECKREG r1, 0x10001110;
 175 CHECKREG r2, 0x20002220;
 176 CHECKREG r3, 0x30003330;
 177 CHECKREG r4, 0x40004440;
 178 CHECKREG r5, 0x50005550;
 179 CHECKREG r6, 0x60006660;
 180 CHECKREG r7, 0x70007770;
 181
 182 B0 = 0xf880 (Z);
 183 B0.H = 0x8000;
 184 B1 = 0xfaa0 (Z);
 185 B1.H = 0xa000;
 186 B2 = 0xfbb0 (Z);
 187 B2.H = 0xb000;
 188 B3 = 0xfcc0 (Z);
 189 B3.H = 0xc000;
 190 M0 = 0xfdd0 (Z);
 191 M0.H = 0xd000;
 192 M1 = 0xfee0 (Z);
 193 M1.H = 0xe000;
 194 M2 = 0xfff0 (Z);
 195 M2.H = 0xf000;
 196 M3 = 0xf110 (Z);
 197 M3.H = 0x1000;
 198 R0 = B0;
 199 R1 = B1;
 200 R2 = B2;
 201 R3 = B3;
 202 R4 = M0;
 203 R5 = M1;
 204 R6 = M2;
 205 R7 = M3;
 206 CHECKREG r0, 0x8000f880;
 207 CHECKREG r1, 0xa000faa0;
 208 CHECKREG r2, 0xb000fbb0;
 209 CHECKREG r3, 0xc000fcc0;
 210 CHECKREG r4, 0xd000fdd0;
 211 CHECKREG r5, 0xe000fee0;
 212 CHECKREG r6, 0xf000fff0;
 213 CHECKREG r7, 0x1000f110;
 214
 215
 216 pass