1 //Original
:/testcases
/core
/c_ldst_st_p_d_pp_b
/c_ldst_st_p_d_pp_b.dsp
2 // Spec Reference
: c_ldst st_p+
+ b byte
5 .include "testutils.inc"
17 loadsym p5
, DATA_ADDR_1;
18 loadsym p1
, DATA_ADDR_2;
19 loadsym p2
, DATA_ADDR_3;
20 loadsym p4
, DATA_ADDR_5;
21 loadsym fp
, DATA_ADDR_6;
23 // store incremented by
1 loc
72 // Read back
and check
73 loadsym p5
, DATA_ADDR_1;
74 loadsym p1
, DATA_ADDR_2;
75 loadsym p2
, DATA_ADDR_3;
76 loadsym p4
, DATA_ADDR_5;
77 loadsym fp
, DATA_ADDR_6;
83 CHECKREG
r0, 0x4B3A2918;
84 CHECKREG
r1, 0x5C4B3A29;
85 CHECKREG
r3, 0x7E6D5C4B;
86 CHECKREG
r4, 0x3A291807;
87 CHECKREG
r5, 0x077E6D5C;
88 CHECKREG
r7, 0x719A8C7E;
94 CHECKREG
r0, 0x4B3A2918;
95 CHECKREG
r1, 0x077E6D5C;
96 CHECKREG
r2, 0x18077E6D;
97 CHECKREG
r4, 0x3A291807;
98 CHECKREG
r5, 0x7E6D5C4B;
99 CHECKREG
r6, 0x4B3A2918;
105 CHECKREG
r1, 0x077E6D5C;
106 CHECKREG
r2, 0x28292A2B;
107 CHECKREG
r3, 0x48494A4B;
108 CHECKREG
r5, 0x88898A8B;
109 CHECKREG
r6, 0x08090A0B;
110 CHECKREG
r7, 0xA8A9AAAB;
114 // Pre-load memory with known data
115 // More data is defined than will actually
be used