1 //Original
:testcases
/core
/c_ldstidxl_ld_dr_xb
/c_ldstidxl_ld_dr_xb.dsp
2 // Spec Reference
: c_ldstidxl load dreg XB
(ld with indexed addressing
)
5 .include "testutils.inc"
18 I1
= P3; P3
= I0; I3
= SP; SP
= I2;
19 loadsym p1
, DATA_ADDR_1
, 0x00;
20 loadsym p2
, DATA_ADDR_2
, 0xA0;
21 loadsym i1
, DATA_ADDR_1
, 0x70;
22 loadsym p4
, DATA_ADDR_2
, 0x70;
23 loadsym p5
, DATA_ADDR_1
, 0x70;
24 loadsym fp
, DATA_ADDR_2
, 0x70;
25 loadsym i3
, DATA_ADDR_1
, 0x70;
28 R0 = B [ P1
+ 151 ] (X
);
29 R1 = B [ P1
+ 83 ] (X
);
30 R2 = B [ P1
+ 45 ] (X
);
31 R3 = B [ P1
+ 17 ] (X
);
32 R4 = B [ P1
+ 39 ] (X
);
33 R5 = B [ P1
+ 21 ] (X
);
34 R6 = B [ P1
+ 123 ] (X
);
35 R7 = B [ P1
+ 155 ] (X
);
36 CHECKREG
r0, 0x00000000;
37 CHECKREG
r1, 0x00000018;
38 CHECKREG
r2, 0x00000076;
39 CHECKREG
r3, 0x00000012;
40 CHECKREG
r4, 0x00000055;
41 CHECKREG
r5, 0x00000016;
42 CHECKREG
r6, 0x00000058;
43 CHECKREG
r7, 0x00000004;
45 R0 = B [ P2
+ -121 ] (X
);
46 R1 = B [ P2
+ -113 ] (X
);
47 R2 = B [ P2
+ -35 ] (X
);
48 R3 = B [ P2
+ -27 ] (X
);
49 R4 = B [ P2
+ -49 ] (X
);
50 R5 = B [ P2
+ -5 ] (X
);
51 R6 = B [ P2
+ -51 ] (X
);
52 R7 = B [ P2
+ -147 ] (X
);
53 CHECKREG
r0, 0xFFFFFFCF;
54 CHECKREG
r1, 0xFFFFFFD7;
55 CHECKREG
r2, 0x00000056;
56 CHECKREG
r3, 0x00000064;
57 CHECKREG
r4, 0xFFFFFF94;
58 CHECKREG
r5, 0x0000004C;
59 CHECKREG
r6, 0xFFFFFF99;
60 CHECKREG
r7, 0x0000004E;
62 R0 = B [ P3
+ 56 ] (X
);
63 R1 = B [ P3
+ 62 ] (X
);
64 R2 = B [ P3
+ -63 ] (X
);
65 R3 = B [ P3
+ 61 ] (X
);
66 R4 = B [ P3
+ -59 ] (X
);
67 R5 = B [ P3
+ 11 ] (X
);
68 R6 = B [ P3
+ -23 ] (X
);
69 R7 = B [ P3
+ -111 ] (X
);
70 CHECKREG
r0, 0x00000017;
71 CHECKREG
r1, 0x00000019;
72 CHECKREG
r2, 0xFFFFFF84;
73 CHECKREG
r3, 0x0000001A;
74 CHECKREG
r4, 0xFFFFFF88;
75 CHECKREG
r5, 0x00000058;
76 CHECKREG
r6, 0x00000028;
77 CHECKREG
r7, 0x00000002;
79 R0 = B [ P4
+ 47 ] (X
);
80 R1 = B [ P4
+ -41 ] (X
);
81 R2 = B [ P4
+ 38 ] (X
);
82 R3 = B [ P4
+ -31 ] (X
);
83 R4 = B [ P4
+ 28 ] (X
);
84 R5 = B [ P4
+ 26 ] (X
);
85 R6 = B [ P4
+ -22 ] (X
);
86 R7 = B [ P4
+ 105 ] (X
);
87 CHECKREG
r0, 0x00000050;
88 CHECKREG
r1, 0xFFFFFF93;
89 CHECKREG
r2, 0x00000049;
90 CHECKREG
r3, 0xFFFFFF99;
91 CHECKREG
r4, 0x00000043;
92 CHECKREG
r5, 0x00000067;
93 CHECKREG
r6, 0xFFFFFFE8;
94 CHECKREG
r7, 0xFFFFFF99;
96 R0 = B [ P5
+ -14 ] (X
);
97 R1 = B [ P5
+ 12 ] (X
);
98 R2 = B [ P5
+ -6 ] (X
);
99 R3 = B [ P5
+ 4 ] (X
);
100 R4 = B [ P5
+ 0 ] (X
);
101 R5 = B [ P5
+ -2 ] (X
);
102 R6 = B [ P5
+ 8 ] (X
);
103 R7 = B [ P5
+ -107 ] (X
);
104 CHECKREG
r0, 0x00000035;
105 CHECKREG
r1, 0x00000065;
106 CHECKREG
r2, 0x00000043;
107 CHECKREG
r3, 0x00000057;
108 CHECKREG
r4, 0x00000053;
109 CHECKREG
r5, 0x00000047;
110 CHECKREG
r6, 0x00000061;
111 CHECKREG
r7, 0x00000006;
113 R0 = B [ FP
+ 99 ] (X
);
114 R1 = B [ FP
+ -15 ] (X
);
115 R2 = B [ FP
+ 41 ] (X
);
116 R3 = B [ FP
+ -65 ] (X
);
117 R4 = B [ FP
+ 25 ] (X
);
118 R5 = B [ FP
+ -34 ] (X
);
119 R6 = B [ FP
+ 37 ] (X
);
120 R7 = B [ FP
+ -97 ] (X
);
121 CHECKREG
r0, 0xFFFFFF93;
122 CHECKREG
r1, 0xFFFFFF99;
123 CHECKREG
r2, 0x0000004E;
124 CHECKREG
r3, 0xFFFFFFD7;
125 CHECKREG
r4, 0x00000068;
126 CHECKREG
r5, 0xFFFFFFE8;
127 CHECKREG
r6, 0x0000004A;
128 CHECKREG
r7, 0x0000004C;
130 R0 = B [ SP
+ 46 ] (X
);
131 R1 = B [ SP
+ -41 ] (X
);
132 R2 = B [ SP
+ 48 ] (X
);
133 R3 = B [ SP
+ 51 ] (X
);
134 R4 = B [ SP
+ -102 ] (X
);
135 R5 = B [ SP
+ 89 ] (X
);
136 R6 = B [ SP
+ 62 ] (X
);
137 R7 = B [ SP
+ 43 ] (X
);
138 CHECKREG
r0, 0x00000009;
139 CHECKREG
r1, 0x00000005;
140 CHECKREG
r2, 0x0000000F;
141 CHECKREG
r3, 0x0000000C;
142 CHECKREG
r4, 0x00000009;
143 CHECKREG
r5, 0xFFFFFF88;
144 CHECKREG
r6, 0x00000019;
145 CHECKREG
r7, 0x00000004;
150 // Pre-load memory with known data
151 // More data is defined than will actually
be used