1 //Original
:testcases
/core
/c_ldstidxl_ld_preg
/c_ldstidxl_ld_preg.dsp
2 // Spec Reference
: c_ldstidxl load dreg
5 .include "testutils.inc"
18 I1
= P3; P3
= I0; I3
= SP; SP
= I2;
19 loadsym p1
, DATA_ADDR_1
, 0x00;
20 loadsym p2
, DATA_ADDR_2
, 0xA0;
21 loadsym i1
, DATA_ADDR_1
, 0x70;
22 loadsym p4
, DATA_ADDR_2
, 0x70;
23 loadsym p5
, DATA_ADDR_1
, 0x70;
24 loadsym fp
, DATA_ADDR_2
, 0x70;
25 loadsym i3
, DATA_ADDR_1
, 0x70;
35 CHECKREG p1
, 0x18191A1B;
36 CHECKREG p2
, 0x0C0D0E0F;
37 CHECKREG p3
, 0x74757677;
38 CHECKREG p4
, 0x08090A0B;
39 CHECKREG p5
, 0x08090A0B;
40 CHECKREG sp
, 0x10111213;
41 CHECKREG fp
, 0x58596061;
43 I1
= P3; P3
= I0; I3
= SP; SP
= I2;
44 loadsym p2
, DATA_ADDR_2
, 0xA0;
54 CHECKREG p1
, 0xEBECEDEE;
55 CHECKREG p2
, 0x7C7D7E7F;
56 CHECKREG p3
, 0xA60CAD7E;
57 CHECKREG p4
, 0xA50CAD6E;
58 CHECKREG p5
, 0x70717273;
59 CHECKREG sp
, 0xA30CAD4E;
60 CHECKREG fp
, 0x64656667;
62 I1
= P3; P3
= I0; I3
= SP; SP
= I2;
63 loadsym i1
, DATA_ADDR_1
, 0x70;
72 CHECKREG p1
, 0x14151617;
73 CHECKREG p2
, 0x08090A0B;
74 CHECKREG p3
, 0x82838485;
75 CHECKREG p4
, 0x74757677;
76 CHECKREG p5
, 0x80818283;
77 CHECKREG sp
, 0x10111213;
78 CHECKREG fp
, 0x01020304;
80 I1
= P3; P3
= I0; I3
= SP; SP
= I2;
81 loadsym p4
, DATA_ADDR_2
, 0x70;
90 CHECKREG p1
, 0x6C6D6E6F;
91 CHECKREG p2
, 0xAB0CAD03;
92 CHECKREG p3
, 0x70717273;
93 CHECKREG p4
, 0xAB0CAD05;
94 CHECKREG p5
, 0xFBFCFDFE;
95 CHECKREG sp
, 0x03040506;
96 CHECKREG fp
, 0x6C6D6E6F;
98 I1
= P3; P3
= I0; I3
= SP; SP
= I2;
99 loadsym p5
, DATA_ADDR_1
, 0x70;
109 CHECKREG p1
, 0x66676869;
110 CHECKREG p2
, 0x62636465;
111 CHECKREG p3
, 0x84858687;
112 CHECKREG p4
, 0x50515253;
113 CHECKREG p5
, 0x1C1D1E1F;
114 CHECKREG sp
, 0x05060708;
115 CHECKREG fp
, 0x72636467;
117 I1
= P3; P3
= I0; I3
= SP; SP
= I2;
118 loadsym i3
, DATA_ADDR_2
, 0x70;
128 CHECKREG p1
, 0xF7F8F9FA;
129 CHECKREG p2
, 0xB455565B;
130 CHECKREG p3
, 0xEBECEDEE;
131 CHECKREG p4
, 0x0B0CAD0E;
132 CHECKREG p5
, 0xAB0CAD06;
133 CHECKREG sp
, 0xAB0CAD04;
134 CHECKREG fp
, 0x60616263;
136 I1
= P3; P3
= I0; I3
= SP; SP
= I2;
137 loadsym fp
, DATA_ADDR_2
, 0x70;
147 CHECKREG p1
, 0x68696A6B;
148 CHECKREG p2
, 0x6C6D6E6F;
149 CHECKREG p3
, 0x60616263;
150 CHECKREG p4
, 0x74757677;
151 CHECKREG p5
, 0x68696A6B;
152 CHECKREG sp
, 0x7C7D7E7F;
153 CHECKREG fp
, 0xEBECEDEE;
158 // Pre-load memory with known data
159 // More data is defined than will actually
be used