1 //Original
:testcases
/core
/c_ldstidxl_st_dr_h
/c_ldstidxl_st_dr_h.dsp
2 // Spec Reference
: c_ldstidxl store dreg
5 .include "testutils.inc"
25 I1
= P3; P3
= I0; I3
= SP; SP
= I2;
26 loadsym p1
, DATA_ADDR_1
, 0x00;
27 loadsym p2
, DATA_ADDR_2
, 0xc8;
28 loadsym i1
, DATA_ADDR_1
, 0x10;
29 loadsym p4
, DATA_ADDR_2
, 0xc8;
30 loadsym p5
, DATA_ADDR_1
, 0x00;
31 loadsym fp
, DATA_ADDR_2
, 0xc8;
32 loadsym i3
, DATA_ADDR_1
, 0x00;
35 W
[ P1
+ 0x1002 ] = R0;
36 W
[ P1
+ 0x1004 ] = R1;
37 W
[ P1
+ 0x1006 ] = R2;
38 W
[ P1
+ 0x1008 ] = R3;
39 W
[ P2
+ -0x1010 ] = R4;
40 W
[ P2
+ -0x1022 ] = R5;
41 W
[ P2
+ -0x1034 ] = R6;
42 W
[ P2
+ -0x1046 ] = R7;
43 R6 = W
[ P1
+ 0x1002 ] (Z
);
44 R5 = W
[ P1
+ 0x1004 ] (Z
);
45 R4 = W
[ P1
+ 0x1006 ] (Z
);
46 R3 = W
[ P1
+ 0x1008 ] (Z
);
47 R2 = W
[ P2
+ -0x1010 ] (Z
);
48 R7 = W
[ P2
+ -0x1022 ] (Z
);
49 R0 = W
[ P2
+ -0x1034 ] (Z
);
50 R1 = W
[ P2
+ -0x1046 ] (Z
);
51 CHECKREG
r0, 0x0000B0A6;
52 CHECKREG
r1, 0x0000C0A7;
53 CHECKREG
r2, 0x000090A4;
54 CHECKREG
r3, 0x000080A3;
55 CHECKREG
r4, 0x000070A2;
56 CHECKREG
r5, 0x000060A1;
57 CHECKREG
r6, 0x000050A0;
58 CHECKREG
r7, 0x0000A0A5;
68 W
[ P3
+ 0x1018 ] = R0;
69 W
[ P3
+ 0x1020 ] = R1;
70 W
[ P3
+ 0x1022 ] = R2;
71 W
[ P3
+ 0x1024 ] = R3;
72 W
[ P4
+ -0x1026 ] = R4;
73 W
[ P4
+ -0x1028 ] = R5;
74 W
[ P4
+ -0x1030 ] = R6;
75 W
[ P4
+ -0x1052 ] = R7;
76 R3 = W
[ P3
+ 0x1018 ] (Z
);
77 R4 = W
[ P3
+ 0x1020 ] (Z
);
78 R0 = W
[ P3
+ 0x1022 ] (Z
);
79 R1 = W
[ P3
+ 0x1024 ] (Z
);
80 R2 = W
[ P4
+ -0x1026 ] (Z
);
81 R5 = W
[ P4
+ -0x1028 ] (Z
);
82 R6 = W
[ P4
+ -0x1030 ] (Z
);
83 R7 = W
[ P4
+ -0x1052 ] (Z
);
84 CHECKREG
r0, 0x000070B2;
85 CHECKREG
r1, 0x000080B3;
86 CHECKREG
r2, 0x000090B4;
87 CHECKREG
r3, 0x000050B0;
88 CHECKREG
r4, 0x000060B1;
89 CHECKREG
r5, 0x0000A0B5;
90 CHECKREG
r6, 0x0000B0B6;
91 CHECKREG
r7, 0x0000C0B7;
100 imm32
r6, 0x70c9b0c6;
101 imm32
r7, 0xd0c8c0c7;
102 W
[ P5
+ 0x1034 ] = R0;
103 W
[ P5
+ 0x1036 ] = R1;
104 W
[ P5
+ 0x1038 ] = R2;
105 W
[ P5
+ 0x1040 ] = R3;
106 W
[ SP
+ -0x1042 ] = R4;
107 W
[ SP
+ -0x1054 ] = R5;
108 W
[ SP
+ -0x1066 ] = R6;
109 W
[ SP
+ -0x1078 ] = R7;
110 R6 = W
[ P5
+ 0x1034 ] (Z
);
111 R5 = W
[ P5
+ 0x1036 ] (Z
);
112 R4 = W
[ P5
+ 0x1038 ] (Z
);
113 R3 = W
[ P5
+ 0x1040 ] (Z
);
114 R2 = W
[ SP
+ -0x1042 ] (Z
);
115 R0 = W
[ SP
+ -0x1054 ] (Z
);
116 R7 = W
[ SP
+ -0x1066 ] (Z
);
117 R1 = W
[ SP
+ -0x1078 ] (Z
);
118 CHECKREG
r0, 0x0000A0C5;
119 CHECKREG
r1, 0x0000C0C7;
120 CHECKREG
r2, 0x000090C4;
121 CHECKREG
r3, 0x000080C3;
122 CHECKREG
r4, 0x000070C2;
123 CHECKREG
r5, 0x000060C1;
124 CHECKREG
r6, 0x000050C0;
127 imm32
r0, 0x60df50d0;
128 imm32
r1, 0x70de60d1;
129 imm32
r2, 0x80dd70d2;
130 imm32
r3, 0x90dc80d3;
131 imm32
r4, 0xa0db90d4;
132 imm32
r5, 0xb0daa0d5;
133 imm32
r6, 0xc0d9b0d6;
134 imm32
r7, 0xd0d8c0d7;
135 W
[ FP
+ 0x1050 ] = R0;
136 W
[ FP
+ 0x1052 ] = R1;
137 W
[ FP
+ 0x1054 ] = R2;
138 W
[ FP
+ 0x1056 ] = R3;
139 W
[ FP
+ 0x1058 ] = R4;
140 W
[ FP
+ 0x1060 ] = R5;
141 W
[ FP
+ 0x1062 ] = R6;
142 W
[ FP
+ 0x1064 ] = R7;
143 R3 = W
[ FP
+ 0x1050 ] (Z
);
144 R4 = W
[ FP
+ 0x1052 ] (Z
);
145 R0 = W
[ FP
+ 0x1054 ] (Z
);
146 R1 = W
[ FP
+ 0x1056 ] (Z
);
147 R2 = W
[ FP
+ 0x1058 ] (Z
);
148 R5 = W
[ FP
+ 0x1060 ] (Z
);
149 R6 = W
[ FP
+ 0x1062 ] (Z
);
150 R7 = W
[ FP
+ 0x1064 ] (Z
);
151 CHECKREG
r0, 0x000070D2;
152 CHECKREG
r1, 0x000080D3;
153 CHECKREG
r2, 0x000090D4;
154 CHECKREG
r3, 0x000050D0;
155 CHECKREG
r4, 0x000060D1;
156 CHECKREG
r5, 0x0000A0D5;
157 CHECKREG
r6, 0x0000B0D6;
158 CHECKREG
r7, 0x0000C0D7;
163 // Pre-load memory with known data
164 // More data is defined than will actually
be used
608 // Make sure there is space for us to scribble