1 //Original
:testcases
/core
/c_ldstidxl_st_dreg
/c_ldstidxl_st_dreg.dsp
2 // Spec Reference
: c_ldstidxl store dreg
5 .include "testutils.inc"
26 I1
= P3; P3
= I0; I3
= SP; SP
= I2;
27 loadsym p1
, DATA_ADDR_1
, 0x00;
28 loadsym p2
, DATA_ADDR_2
, 0xc8;
29 loadsym i1
, DATA_ADDR_1
, 0x10;
30 loadsym p4
, DATA_ADDR_2
, 0xc8;
31 loadsym p5
, DATA_ADDR_1
, 0x00;
32 loadsym fp
, DATA_ADDR_2
, 0xc8;
33 loadsym i3
, DATA_ADDR_1
, 0x00;
40 [ P2
+ -0x1020 ] = R4;
41 [ P2
+ -0x1024 ] = R5;
42 [ P2
+ -0x1028 ] = R6;
43 [ P2
+ -0x1030 ] = R7;
48 R2 = [ P2
+ -0x1020 ];
49 R7 = [ P2
+ -0x1024 ];
50 R0 = [ P2
+ -0x1028 ];
51 R1 = [ P2
+ -0x1030 ];
52 CHECKREG
r0, 0x7019B0A6;
53 CHECKREG
r1, 0xD028C0A7;
54 CHECKREG
r2, 0x501B90A4;
55 CHECKREG
r3, 0x402C80A3;
56 CHECKREG
r4, 0x300370A2;
57 CHECKREG
r5, 0x204E60A1;
58 CHECKREG
r6, 0x105F50A0;
59 CHECKREG
r7, 0x600AA0A5;
73 [ P4
+ -0x1050 ] = R4;
74 [ P4
+ -0x1054 ] = R5;
75 [ P4
+ -0x1060 ] = R6;
76 [ P4
+ -0x1064 ] = R7;
81 R2 = [ P4
+ -0x1050 ];
82 R5 = [ P4
+ -0x1054 ];
83 R6 = [ P4
+ -0x1060 ];
84 R7 = [ P4
+ -0x1064 ];
85 CHECKREG
r0, 0x30BD70B2;
86 CHECKREG
r1, 0x40BC80B3;
87 CHECKREG
r2, 0x55BB90B4;
88 CHECKREG
r3, 0x10BF50B0;
89 CHECKREG
r4, 0x20BE60B1;
90 CHECKREG
r5, 0x60BAA0B5;
91 CHECKREG
r6, 0x70B9B0B6;
92 CHECKREG
r7, 0x80B8C0B7;
100 imm32
r5, 0x60caa0c5;
101 imm32
r6, 0x70c9b0c6;
102 imm32
r7, 0xd0c8c0c7;
107 [ SP
+ -0x1020 ] = R4;
108 [ SP
+ -0x1024 ] = R5;
109 [ SP
+ -0x1028 ] = R6;
110 [ SP
+ -0x1030 ] = R7;
115 R2 = [ SP
+ -0x1020 ];
116 R0 = [ SP
+ -0x1024 ];
117 R7 = [ SP
+ -0x1028 ];
118 R1 = [ SP
+ -0x1030 ];
119 CHECKREG
r0, 0x60CAA0C5;
120 CHECKREG
r1, 0xD0C8C0C7;
121 CHECKREG
r2, 0x50CB90C4;
122 CHECKREG
r3, 0x40CC80C3;
123 CHECKREG
r4, 0x20CE60C1;
124 CHECKREG
r5, 0x30C370C2;
125 CHECKREG
r6, 0x10CF50C0;
128 imm32
r0, 0x60df50d0;
129 imm32
r1, 0x70de60d1;
130 imm32
r2, 0x80dd70d2;
131 imm32
r3, 0x90dc80d3;
132 imm32
r4, 0xa0db90d4;
133 imm32
r5, 0xb0daa0d5;
134 imm32
r6, 0xc0d9b0d6;
135 imm32
r7, 0xd0d8c0d7;
136 [ FP
+ 0x1034 ] = R0;
137 [ FP
+ 0x1040 ] = R1;
138 [ FP
+ 0x1044 ] = R2;
139 [ FP
+ 0x1048 ] = R3;
140 [ FP
+ 0x1050 ] = R4;
141 [ FP
+ 0x1054 ] = R5;
142 [ FP
+ 0x1060 ] = R6;
143 [ FP
+ 0x1064 ] = R7;
145 R3 = [ FP
+ 0x1034 ];
146 R4 = [ FP
+ 0x1040 ];
147 R0 = [ FP
+ 0x1044 ];
148 R1 = [ FP
+ 0x1048 ];
149 R2 = [ FP
+ 0x1050 ];
150 R5 = [ FP
+ 0x1054 ];
151 R6 = [ FP
+ 0x1060 ];
152 R7 = [ FP
+ 0x1064 ];
153 CHECKREG
r0, 0x80DD70D2;
154 CHECKREG
r1, 0x90DC80D3;
155 CHECKREG
r2, 0xA0DB90D4;
156 CHECKREG
r3, 0x60DF50D0;
157 CHECKREG
r4, 0x70DE60D1;
158 CHECKREG
r5, 0xB0DAA0D5;
159 CHECKREG
r6, 0xC0D9B0D6;
160 CHECKREG
r7, 0xD0D8C0D7;
166 // Pre-load memory with known data
167 // More data is defined than will actually
be used
170 // Make sure there is space between the text section
, and the data section
779 // Make sure there is space for us to scribble