1 //Original
:testcases
/core
/c_ldstpmod_st_dreg
/c_ldstpmod_st_dreg.dsp
2 // Spec Reference
: c_ldstpmod store dreg
5 .include "testutils.inc"
31 I1
= P3; P3
= I0; I3
= SP; SP
= I2;
32 loadsym p5
, DATA_ADDR_5
, 0x00;
47 I1
= P3; P3
= I0; I3
= SP; SP
= I2;
48 loadsym p5
, DATA_ADDR_5
, 0x00;
57 CHECKREG
r0, 0xB00AA005;
58 CHECKREG
r1, 0xC009B006;
59 CHECKREG
r2, 0xA00B9004;
60 CHECKREG
r3, 0x900C8003;
61 CHECKREG
r4, 0x800D7002;
62 CHECKREG
r5, 0x700E6001;
63 CHECKREG
r6, 0x600F5000;
80 I1
= P3; P3
= I0; I3
= SP; SP
= I2;
81 loadsym p1
, DATA_ADDR_1
, 0x00;
96 I1
= P3; P3
= I0; I3
= SP; SP
= I2;
97 loadsym p1
, DATA_ADDR_1
, 0x00;
106 CHECKREG
r0, 0x600AA0A5;
107 CHECKREG
r1, 0x7019B0A6;
108 CHECKREG
r2, 0x501B90A4;
109 CHECKREG
r3, 0x402C80A3;
110 CHECKREG
r4, 0x300370A2;
111 CHECKREG
r5, 0x204E60A1;
112 CHECKREG
r6, 0x105F50A0;
115 imm32
r0, 0x10bf50b0;
116 imm32
r1, 0x20be60b1;
117 imm32
r2, 0x30bd70b2;
118 imm32
r3, 0x40bc80b3;
119 imm32
r4, 0x55bb90b4;
120 imm32
r5, 0x60baa0b5;
121 imm32
r6, 0x70b9b0b6;
122 imm32
r7, 0x80b8c0b7;
129 I1
= P3; P3
= I0; I3
= SP; SP
= I2;
130 loadsym p2
, DATA_ADDR_2
, 0x00;
145 I1
= P3; P3
= I0; I3
= SP; SP
= I2;
146 loadsym p2
, DATA_ADDR_2
, 0x00;
155 CHECKREG
r0, 0x30BD70B2;
156 CHECKREG
r1, 0x40BC80B3;
157 CHECKREG
r2, 0x55BB90B4;
158 CHECKREG
r3, 0x10BF50B0;
159 CHECKREG
r4, 0x20BE60B1;
160 CHECKREG
r5, 0x60BAA0B5;
161 CHECKREG
r6, 0x70B9B0B6;
164 imm32
r0, 0x10cf50c0;
165 imm32
r1, 0x20ce60c1;
166 imm32
r2, 0x30c370c2;
167 imm32
r3, 0x40cc80c3;
168 imm32
r4, 0x50cb90c4;
169 imm32
r5, 0x60caa0c5;
170 imm32
r6, 0x70c9b0c6;
171 imm32
r7, 0xd0c8c0c7;
178 I1
= P3; P3
= I0; I3
= SP; SP
= I2;
179 loadsym i1
, DATA_ADDR_3
, 0x00;
194 I1
= P3; P3
= I0; I3
= SP; SP
= I2;
195 loadsym i1
, DATA_ADDR_3
, 0x00;
204 CHECKREG
r0, 0x60CAA0C5;
205 CHECKREG
r1, 0x70C9B0C6;
206 CHECKREG
r2, 0x50CB90C4;
207 CHECKREG
r3, 0x40CC80C3;
208 CHECKREG
r4, 0x30C370C2;
209 CHECKREG
r5, 0x20CE60C1;
210 CHECKREG
r6, 0x10CF50C0;
213 imm32
r0, 0x60df50d0;
214 imm32
r1, 0x70de60d1;
215 imm32
r2, 0x80dd70d2;
216 imm32
r3, 0x90dc80d3;
217 imm32
r4, 0xa0db90d4;
218 imm32
r5, 0xb0daa0d5;
219 imm32
r6, 0xc0d9b0d6;
220 imm32
r7, 0xd0d8c0d7;
227 I1
= P3; P3
= I0; I3
= SP; SP
= I2;
228 loadsym p4
, DATA_ADDR_4
, 0x00;
243 I1
= P3; P3
= I0; I3
= SP; SP
= I2;
244 loadsym p4
, DATA_ADDR_4
, 0x00;
253 CHECKREG
r0, 0x80DD70D2;
254 CHECKREG
r1, 0x90DC80D3;
255 CHECKREG
r2, 0xA0DB90D4;
256 CHECKREG
r3, 0xB0DAA0D5;
257 CHECKREG
r4, 0xC0D9B0D6;
258 CHECKREG
r5, 0x60DF50D0;
259 CHECKREG
r6, 0x70DE60D1;
262 imm32
r0, 0x1e5f50e0;
263 imm32
r1, 0x2e4e60e1;
264 imm32
r2, 0x3e0370e2;
265 imm32
r3, 0x4e2c80e3;
266 imm32
r4, 0x5e1b90e4;
267 imm32
r5, 0x6e0aa0e5;
268 imm32
r6, 0x7e19b0e6;
269 imm32
r7, 0xde28c0e7;
276 I1
= P3; P3
= I0; I3
= SP; SP
= I2;
277 loadsym i3
, DATA_ADDR_6
, 0x00;
292 I1
= P3; P3
= I0; I3
= SP; SP
= I2;
293 loadsym i3
, DATA_ADDR_6
, 0x00;
302 CHECKREG
r0, 0x6E0AA0E5;
303 CHECKREG
r1, 0x7E19B0E6;
304 CHECKREG
r2, 0x5E1B90E4;
305 CHECKREG
r3, 0x4E2C80E3;
306 CHECKREG
r4, 0x3E0370E2;
307 CHECKREG
r5, 0x2E4E60E1;
308 CHECKREG
r6, 0x1E5F50E0;
311 imm32
r0, 0x10ff50f0;
312 imm32
r1, 0x20fe60f1;
313 imm32
r2, 0x30fd70f2;
314 imm32
r3, 0x40fc80f3;
315 imm32
r4, 0x55fb90f4;
316 imm32
r5, 0x60faa0f5;
317 imm32
r6, 0x70f9b0f6;
318 imm32
r7, 0x80f8c0f7;
326 I1
= P3; P3
= I0; I3
= SP; SP
= I2;
327 loadsym fp
, DATA_ADDR_7
, 0x00;
342 I1
= P3; P3
= I0; I3
= SP; SP
= I2;
343 loadsym fp
, DATA_ADDR_7
, 0x00;
352 CHECKREG
r0, 0x30FD70F2;
353 CHECKREG
r1, 0x40FC80F3;
354 CHECKREG
r2, 0x55FB90F4;
355 CHECKREG
r3, 0x10FF50F0;
356 CHECKREG
r4, 0x20FE60F1;
357 CHECKREG
r5, 0x60FAA0F5;
358 CHECKREG
r6, 0x70F9B0F6;
363 // Pre-load memory with known data
364 // More data is defined than will actually
be used