sim/testsuite/bfin/c_loopsetup_prelc.s

   1 //Original:/testcases/core/c_loopsetup_prelc/c_loopsetup_prelc.dsp
   2 // Spec Reference: loopsetup preload lc0 lc1
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9 INIT_R_REGS 0;
  10
  11 ASTAT = r0;
  12
  13 //p0 = 2;
  14 P1 = 3;
  15 P2 = 4;
  16 P3 = 5;
  17 P4 = 6;
  18 P5 = 7;
  19 SP = 8;
  20 FP = 9;
  21
  22 R0 = 0x05;
  23 R1 = 0x10;
  24 R2 = 0x20;
  25 R3 = 0x30;
  26 R4 = 0x40 (X);
  27 R5 = 0x50 (X);
  28 R6 = 0x60 (X);
  29 R7 = 0x70 (X);
  30
  31 LC0 = R0;
  32 LC1 = R1;
  33
  34 LSETUP ( start1 , end1 ) LC0;
  35 start1: R0 += 1;
  36  R1 += -2;
  37 end1: R2 += 3;
  38  R3 += 4;
  39 LSETUP ( start2 , end2 ) LC1;
  40 start2: R4 += 4;
  41 end2: R5 += -5;
  42  R3 += 1;
  43 LSETUP ( start3 , end3 ) LC0 = P3;
  44 start3: R6 += 6;
  45 end3: R7 += -7;
  46  R3 += 1;
  47 CHECKREG r0, 0x0000000a;
  48 CHECKREG r1, 0x00000006;
  49 CHECKREG r2, 0x0000002f;
  50 CHECKREG r3, 0x00000036;
  51 CHECKREG r4, 0x00000080;
  52 CHECKREG r5, 0x00000000;
  53 CHECKREG r6, 0x0000007E;
  54 CHECKREG r7, 0x0000004D;
  55
  56 R0 = 0x05;
  57 R1 = 0x10;
  58 R2 = 0x20;
  59 R3 = 0x30;
  60 R4 = 0x40 (X);
  61 R5 = 0x50 (X);
  62 R6 = 0x60 (X);
  63 R7 = 0x70 (X);
  64
  65 LC0 = R2;
  66 LC1 = R3;
  67
  68 LSETUP ( start4 , end4 ) LC0;
  69 start4: R0 += 1;
  70  R1 += -2;
  71 end4: R2 += 3;
  72  R3 += 4;
  73 LSETUP ( start5 , end5 ) LC1;
  74 start5: R4 += 1;
  75 end5: R5 += -2;
  76  R3 += 3;
  77
  78 LSETUP ( start6 , end6 ) LC0 = P2;
  79 start6: R6 += 4;
  80 end6: R7 += -5;
  81  R3 += 6;
  82 CHECKREG r0, 0x00000025;
  83 CHECKREG r1, 0xFFFFFFD0;
  84 CHECKREG r2, 0x00000080;
  85 CHECKREG r3, 0x0000003D;
  86 CHECKREG r4, 0x00000070;
  87 CHECKREG r5, 0xFFFFFFF0;
  88 CHECKREG r6, 0x00000070;
  89 CHECKREG r7, 0x0000005C;
  90 LSETUP ( start7 , end7 ) LC1;
  91 start7: R4 += 4;
  92 end7: R5 += -5;
  93  R3 += 6;
  94 CHECKREG r0, 0x00000025;
  95 CHECKREG r1, 0xFFFFFFD0;
  96 CHECKREG r2, 0x00000080;
  97 CHECKREG r3, 0x00000043;
  98 CHECKREG r4, 0x00000074;
  99 CHECKREG r5, 0xFFFFFFEB;
 100 CHECKREG r6, 0x00000070;
 101 CHECKREG r7, 0x0000005C;
 102
 103 P1 = 12;
 104 P2 = 14;
 105 P3 = 16;
 106 P4 = 18;
 107 P5 = 20;
 108 SP = 22;
 109 FP = 24;
 110
 111 R0 = 0x05;
 112 R1 = 0x10;
 113 R2 = 0x20;
 114 R3 = 0x30;
 115 R4 = 0x40 (X);
 116 R5 = 0x50 (X);
 117 R6 = 0x25;
 118 R7 = 0x32;
 119
 120 LC0 = R6;
 121 LC1 = R7;
 122 LSETUP ( start11 , end11 ) LC0;
 123 start11: R0 += 1;
 124  R1 += -1;
 125 end11: R2 += 1;
 126  R3 += 1;
 127 LSETUP ( start12 , end12 ) LC1;
 128 start12: R4 += 1;
 129 end12: R5 += -1;
 130  R3 += 1;
 131 LSETUP ( start13 , end13 ) LC1 = P4;
 132 start13: R6 += 1;
 133 end13: R7 += -1;
 134  R3 += 1;
 135 CHECKREG r0, 0x0000002A;
 136 CHECKREG r1, 0xFFFFFFEB;
 137 CHECKREG r2, 0x00000045;
 138 CHECKREG r3, 0x00000033;
 139 CHECKREG r4, 0x00000072;
 140 CHECKREG r5, 0x0000001E;
 141 CHECKREG r6, 0x00000037;
 142 CHECKREG r7, 0x00000020;
 143
 144
 145 pass