1 //Original
:/testcases
/core
/c_multi_issue_dsp_ldst_1
/c_multi_issue_dsp_ldst_1.dsp
2 // Spec Reference
: dsp32mac
and 2 load
/store
5 .include "testutils.inc"
22 // test the default
(signed fraction
: left
)
31 A1
= R0.
L * R1.
L, A0
= R0.
L * R1.
L ||
R0 = [ I0
++ ] ||
R1 = [ I1
++ ];
32 A1
+= R2.
L * R3.
L, A0
+= R2.
L * R3.H ||
R2 = [ I0
++ ] ||
R3 = [ I1
++ ];
33 A1
+= R6.H
* R7.H
, A0
+= R6.H
* R7.
L ||
R4 = [ P1
++ ] ||
[ I1
++ ] = R5;
36 CHECKREG
r0, 0x000A0000;
37 CHECKREG
r1, 0x00F00100;
38 CHECKREG
r2, 0x000B0001;
39 CHECKREG
r3, 0x00E00101;
40 CHECKREG
r4, 0x000A0000;
41 CHECKREG
r5, 0xA7891234;
42 CHECKREG
r6, 0x92793486;
43 CHECKREG
r7, 0xDD2F9BAA;
53 A1
= R0.
L * R1.
L, A0
= R0.
L * R1.
L ||
R4 = [ P1
++ ] ||
[ I0
++ ] = R6;
54 A1
-= R2.
L * R3.
L, A0
+= R2.
L * R3.H ||
R2 = [ P2
++ ] ||
[ I1
++ ] = R3;
55 A1
+= R4.H
* R6.H
, A0
-= R4.H
* R6.
L ||
[ P2
++ ] = R5 ||
R7 = [ I1
++ ];
58 CHECKREG
r0, 0x12245618;
59 CHECKREG
r1, 0x23256719;
60 CHECKREG
r2, 0x00F00100;
61 CHECKREG
r3, 0x45278912;
62 CHECKREG
r4, 0x000B0001;
63 CHECKREG
r5, 0x67291214;
64 CHECKREG
r6, 0x8634CCA2;
65 CHECKREG
r7, 0xB4E7420A;
75 A1
+= R0.H
* R1.H
, A0
+= R0.
L * R1.
L ||
R2 = [ P1
++ ] ||
[ I1
-- ] = R3;
76 A1
+= R2.H
* R3.H
, A0
+= R2.
L * R3.H ||
NOP ||
[ I0
++ ] = R2;
77 A1
= R4.H
* R5.
L, A0
+= R4.H
* R5.
L ||
R3 = [ P2
-- ] ||
R6 = [ I0
-- ];
80 CHECKREG
r0, 0x15245648;
81 CHECKREG
r1, 0x25256749;
82 CHECKREG
r2, 0xA1234517;
83 CHECKREG
r3, 0xA7891234;
84 CHECKREG
r4, 0x55389143;
85 CHECKREG
r5, 0x65391244;
86 CHECKREG
r6, 0xFD508A74;
87 CHECKREG
r7, 0x0C2925C0;
96 R2 = R0 +|
+ R7, R4 = R0 -|
- R7 (ASR
) ||
R0 = [ I1
++ ] ||
[ I0
-- ] = R2;
97 R1 = R6 +|
+ R3, R5 = R6 -|
- R3 ||
R6 = [ P1
] ||
[ I0
-- ] = R3;
98 R5 = R4 +|
+ R2, R0 = R4 -|
- R2 (CO
) ||
NOP ||
[ I0
++ ] = R5;
99 CHECKREG
r0, 0xFA99FFDD;
100 CHECKREG
r1, 0x0B8A0E79;
101 CHECKREG
r2, 0x0AA32DD7;
102 CHECKREG
r3, 0x04670912;
103 CHECKREG
r4, 0x0A802870;
104 CHECKREG
r5, 0x15235647;
105 CHECKREG
r6, 0x0356089A;
106 CHECKREG
r7, 0x00230567;