sim/testsuite/bfin/c_progctrl_clisti_interr.S

   1 //Original:/proj/frio/dv/testcases/core/c_progctrl_clisti_interr/c_progctrl_clisti_interr.dsp
   2 // Spec Reference: CLI STI interrupt on HW TIMER
   3 # mach: bfin
   4 # sim: --environment operating
   5
   6 #include "test.h"
   7 .include "testutils.inc"
   8 start
   9
  10 //
  11 // Include Files
  12 //
  13
  14 include(std.inc)
  15 include(selfcheck.inc)
  16
  17 // Defines
  18
  19 #ifndef TCNTL
  20 #define TCNTL            0xFFE03000
  21 #endif
  22 #ifndef TPERIOD
  23 #define TPERIOD          0xFFE03004
  24 #endif
  25 #ifndef TSCALE
  26 #define TSCALE           0xFFE03008
  27 #endif
  28 #ifndef TCOUNT
  29 #define TCOUNT           0xFFE0300c
  30 #endif
  31 #ifndef EVT
  32 #define EVT              0xFFE02000
  33 #endif
  34 #ifndef EVT15
  35 #define EVT15            0xFFE0203c
  36 #endif
  37 #ifndef EVT_OVERRIDE
  38 #define EVT_OVERRIDE     0xFFE02100
  39 #endif
  40 #ifndef ITABLE
  41 #define ITABLE           0x000FF000
  42 #endif
  43 #ifndef PROGRAM_STACK
  44 #define PROGRAM_STACK    0x000FF100
  45 #endif
  46 #ifndef STACKSIZE
  47 #define STACKSIZE        0x00000300
  48 #endif
  49
  50 // Boot code
  51
  52
  53 INIT_R_REGS(0);                             // Initialize Dregs
  54 INIT_P_REGS(0);                             // Initialize Pregs
  55
  56       //CHECK_INIT(p5,   0xE0000000);
  57 include(symtable.inc)
  58 CHECK_INIT_DEF(p5);
  59  BOOT :
  60
  61 LD32(sp, 0x000FF200);
  62 LD32(p0, EVT);              // Setup Event Vectors and Handlers
  63
  64 LD32_LABEL(r0, EHANDLE);    // Emulation Handler (Int0)
  65         [ P0 ++ ] = R0;
  66
  67 LD32_LABEL(r0, RHANDLE);    // Reset Handler (Int1)
  68         [ P0 ++ ] = R0;
  69
  70 LD32_LABEL(r0, NHANDLE);    // NMI Handler (Int2)
  71         [ P0 ++ ] = R0;
  72
  73 LD32_LABEL(r0, XHANDLE);    // Exception Handler (Int3)
  74         [ P0 ++ ] = R0;
  75
  76         [ P0 ++ ] = R0;                // IVT4 not used
  77
  78 LD32_LABEL(r0, HWHANDLE);   // HW Error Handler (Int5)
  79         [ P0 ++ ] = R0;
  80
  81 LD32_LABEL(r0, THANDLE);    // Timer Handler (Int6)
  82         [ P0 ++ ] = R0;
  83
  84 LD32_LABEL(r0, I7HANDLE);   // IVG7 Handler
  85         [ P0 ++ ] = R0;
  86
  87 LD32_LABEL(r0, I8HANDLE);   // IVG8 Handler
  88         [ P0 ++ ] = R0;
  89
  90 LD32_LABEL(r0, I9HANDLE);   // IVG9 Handler
  91         [ P0 ++ ] = R0;
  92
  93 LD32_LABEL(r0, I10HANDLE);  // IVG10 Handler
  94         [ P0 ++ ] = R0;
  95
  96 LD32_LABEL(r0, I11HANDLE);  // IVG11 Handler
  97         [ P0 ++ ] = R0;
  98
  99 LD32_LABEL(r0, I12HANDLE);  // IVG12 Handler
 100         [ P0 ++ ] = R0;
 101
 102 LD32_LABEL(r0, I13HANDLE);  // IVG13 Handler
 103         [ P0 ++ ] = R0;
 104
 105 LD32_LABEL(r0, I14HANDLE);  // IVG14 Handler
 106         [ P0 ++ ] = R0;
 107
 108 LD32_LABEL(r0, I15HANDLE);  // IVG15 Handler
 109         [ P0 ++ ] = R0;
 110
 111 LD32(p0, EVT_OVERRIDE);
 112         R0 = 0;
 113         [ P0 ++ ] = R0;
 114         R0 = -1;     // Change this to mask interrupts (*)
 115         [ P0 ] = R0;   // IMASK
 116
 117 LD32_LABEL(p1, START);
 118
 119 LD32(p0, EVT15);
 120         [ P0 ] = P1;   // IVG15 (General) handler (Int 15) load with start
 121
 122 RAISE 15;    // after we RTI, INT 15 should be taken
 123
 124 LD32_LABEL(r7, START);
 125 RETI = r7;
 126 NOP;        // Workaround for Bug 217
 127 RTI;
 128 NOP;
 129 NOP;
 130 NOP;
 131 NOP;
 132 NOP;
 133 NOP;
 134 NOP;
 135 NOP;
 136 DUMMY:
 137           NOP;
 138 NOP;
 139 NOP;
 140 NOP;
 141 NOP;
 142 NOP;
 143 NOP;
 144 NOP;
 145 NOP;
 146 NOP;
 147
 148  START :
 149         R7 = 0x0;
 150         R6 = 0x1;
 151         [ -- SP ] = RETI;        // Enable Nested Interrupts
 152
 153 CLI R1;                                           // stop interrupt
 154 WR_MMR(TCNTL,   0x00000001, p0, r0);        // Turn ON TMPWR (active state)
 155 WR_MMR(TPERIOD, 0x00000050, p0, r0);
 156 WR_MMR(TCOUNT,  0x00000013, p0, r0);
 157 WR_MMR(TSCALE,  0x00000000, p0, r0);
 158 CSYNC;
 159         // Read the contents of the Timer
 160
 161 RD_MMR(TPERIOD, p0, r2);
 162 CHECKREG(r2,    0x00000050);
 163
 164 //      RD_MMR(TCOUNT, p0, r3);
 165 //      CHECKREG(r3, 0x00000013);// fsim -ro useChecker=regtrace -seed 8b8db910
 166
 167
 168 WR_MMR(TCNTL,   0x00000003, p0, r0);        // enable Timer (TMPWR, TMREN)
 169 CSYNC;
 170
 171 NOP; NOP; NOP;
 172 NOP; NOP; NOP;
 173 NOP; NOP; NOP;
 174 NOP; NOP; NOP;
 175 NOP; NOP; NOP;
 176 NOP; NOP; NOP;
 177 NOP; NOP; NOP;
 178 NOP; NOP; NOP;
 179 RD_MMR(TPERIOD, p0, r4);
 180 CHECKREG(r4,    0x00000050);
 181
 182 //      RD_MMR(TCNTL, p0, r5);
 183 //      CHECKREG(r5,    0x0000000B);                // INTERRUPT did happen
 184
 185 WR_MMR(TCNTL,   0x00000000, p0, r0);        // Turn OFF Timer
 186 CSYNC;
 187 NOP;
 188 WR_MMR(TCNTL,   0x00000001, p0, r0);        // Turn ON Timer Power
 189 WR_MMR(TPERIOD, 0x00000015, p0, r0);
 190 WR_MMR(TCOUNT,  0x00000013, p0, r0);
 191 WR_MMR(TSCALE,  0x00000002, p0, r0);
 192 WR_MMR(TCNTL,   0x00000007, p0, r0);        // Turn ON Timer (TAUTORLD=1)
 193 CSYNC;
 194 NOP;
 195 NOP;
 196 NOP;
 197 NOP;
 198 NOP;
 199 NOP;
 200 NOP;
 201 NOP;
 202 NOP;
 203 NOP;
 204 NOP;
 205 NOP;
 206 NOP;
 207 NOP;
 208 NOP;
 209 JUMP.S label4;
 210         R4.L = 0x1111;                             // Will be killed
 211         R4.H = 0x1111;                             // Will be killed
 212 NOP;
 213 NOP;
 214 NOP;
 215 label5: R5.H = 0x7777;
 216         R5.L = 0x7888;
 217 JUMP.S label6;
 218         R5.L = 0x1111;                             // Will be killed
 219         R5.H = 0x1111;                             // Will be killed
 220 NOP;
 221 NOP;
 222 NOP;
 223 NOP;
 224 NOP;
 225 NOP;
 226 label4: R4.H = 0x5555;
 227         R4.L = 0x6666;
 228 NOP;
 229 JUMP.S label5;
 230         R5.L = 0x2222;     // Will be killed
 231         R5.H = 0x2222;     // Will be killed
 232 NOP;
 233 NOP;
 234 NOP;
 235 NOP;
 236 label6: R3.H = 0x7999;
 237         R3.L = 0x7aaa;
 238 NOP;
 239 NOP;
 240 NOP;
 241 NOP;
 242 NOP;
 243 NOP;
 244 NOP;
 245                                                     // With auto reload
 246         // Read the contents of the Timer
 247
 248 RD_MMR(TPERIOD, p0, r2);
 249 CHECKREG(r2,    0x00000015);
 250
 251 //      RD_MMR(TCNTL , p0, r3);
 252 //      CHECKREG(r3,    0x0000000F);
 253 NOP;
 254 CHECKREG(r7,    0x00000000);    // no interrupt being serviced
 255 NOP;
 256 STI R1;
 257
 258 NOP; NOP; NOP;
 259 NOP; NOP; NOP;
 260 WR_MMR(TCNTL,   0x00000000, p0, r0);        // Turn OFF Timer
 261 CSYNC;
 262 NOP; NOP; NOP;
 263
 264
 265
 266
 267
 268 dbg_pass;        // Call Endtest Macro
 269
 270
 271
 272 //*********************************************************************
 273 //
 274 // Handlers for Events
 275 //
 276
 277 EHANDLE:            // Emulation Handler 0
 278 RTE;
 279
 280 RHANDLE:            // Reset Handler 1
 281 RTI;
 282
 283 NHANDLE:            // NMI Handler 2
 284 RTN;
 285
 286 XHANDLE:            // Exception Handler 3
 287 RTX;
 288
 289 HWHANDLE:           // HW Error Handler 5
 290 RTI;
 291
 292 THANDLE:            // Timer Handler 6
 293         R7 = R7 + R6;
 294 RTI;
 295
 296 I7HANDLE:           // IVG 7 Handler
 297 RTI;
 298
 299 I8HANDLE:           // IVG 8 Handler
 300 RTI;
 301
 302 I9HANDLE:           // IVG 9 Handler
 303 RTI;
 304
 305 I10HANDLE:          // IVG 10 Handler
 306 RTI;
 307
 308 I11HANDLE:          // IVG 11 Handler
 309 RTI;
 310
 311 I12HANDLE:          // IVG 12 Handler
 312 RTI;
 313
 314 I13HANDLE:          // IVG 13 Handler
 315 RTI;
 316
 317 I14HANDLE:          // IVG 14 Handler
 318 RTI;
 319
 320 I15HANDLE:          // IVG 15 Handler
 321         R5 = RETI;
 322         P0 = R5;
 323 JUMP ( P0 );
 324 RTI;
 325
 326 .section MEM_PROGRAM_STACK,"aw"
 327
 328 .space (STACKSIZE);
 329 STACK:
 330 NOP;NOP;NOP;NOP;NOP;NOP;NOP; // needed for icache bug