sim/testsuite/bfin/c_ptr2op_pr_shadd_1_2.s

   1 //Original:/proj/frio/dv/testcases/core/c_ptr2op_pr_shadd_1_2/c_ptr2op_pr_shadd_1_2.dsp
   2 // Spec Reference:  ptr2op shadd  preg, pregs, 1 (2)
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8         R0 = 0;
   9         ASTAT = R0;
  10
  11 // check p-reg to p-reg move
  12
  13         imm32 p1, 0xf0921203;
  14         imm32 p2, 0xbe041305;
  15         imm32 p3, 0xd0d61407;
  16         imm32 p4, 0xa00a1089;
  17         imm32 p5, 0x400a300b;
  18         imm32 sp, 0xe07c180d;
  19         imm32 fp, 0x206e109f;
  20         P1 = ( P1 + P1 ) << 2;
  21         P2 = ( P2 + P1 ) << 2;
  22         P3 = ( P3 + P1 ) << 2;
  23         P4 = ( P4 + P1 ) << 1;
  24         P5 = ( P5 + P1 ) << 2;
  25         SP = ( SP + P1 ) << 2;
  26         FP = ( FP + P1 ) << 1;
  27         CHECKREG p1, 0x84909018;
  28         CHECKREG p2, 0x0A528C74;
  29         CHECKREG p3, 0x559A907C;
  30         CHECKREG p4, 0x49354142;
  31         CHECKREG p5, 0x126B008C;
  32         CHECKREG sp, 0x9432A094;
  33         CHECKREG fp, 0x49FD416E;
  34
  35         imm32 p1, 0x50021003;
  36         imm32 p2, 0x26041005;
  37         imm32 p3, 0x60761007;
  38         imm32 p4, 0x20081009;
  39         imm32 p5, 0xf00a900b;
  40         imm32 sp, 0xb00c1a0d;
  41         imm32 fp, 0x200e10bf;
  42         P1 = ( P1 + P2 ) << 1;
  43         P2 = ( P2 + P2 ) << 2;
  44         P3 = ( P3 + P2 ) << 1;
  45         P4 = ( P4 + P2 ) << 2;
  46         P5 = ( P5 + P2 ) << 2;
  47         SP = ( SP + P2 ) << 1;
  48         FP = ( FP + P2 ) << 2;
  49         CHECKREG p1, 0xEC0C4010;
  50         CHECKREG p2, 0x30208028;
  51         CHECKREG p3, 0x212D205E;
  52         CHECKREG p4, 0x40A240C4;
  53         CHECKREG p5, 0x80AC40CC;
  54         CHECKREG sp, 0xC059346A;
  55         CHECKREG fp, 0x40BA439C;
  56
  57         imm32 p1, 0x30026003;
  58         imm32 p2, 0x40051005;
  59         imm32 p3, 0x20e65057;
  60         imm32 p4, 0x2d081089;
  61         imm32 p5, 0xf00ab07b;
  62         imm32 sp, 0x200c1b0d;
  63         imm32 fp, 0x200e100f;
  64         P1 = ( P1 + P3 ) << 2;
  65         P2 = ( P2 + P3 ) << 1;
  66         P3 = ( P3 + P3 ) << 2;
  67         P4 = ( P4 + P3 ) << 2;
  68         P5 = ( P5 + P3 ) << 2;
  69         SP = ( SP + P3 ) << 1;
  70         FP = ( FP + P3 ) << 2;
  71         CHECKREG p1, 0x43A2C168;
  72         CHECKREG p2, 0xC1D6C0B8;
  73         CHECKREG p3, 0x073282B8;
  74         CHECKREG p4, 0xD0EA4D04;
  75         CHECKREG p5, 0xDCF4CCCC;
  76         CHECKREG sp, 0x4E7D3B8A;
  77         CHECKREG fp, 0x9D024B1C;
  78
  79         imm32 p1, 0xa0021003;
  80         imm32 p2, 0x2c041005;
  81         imm32 p3, 0x40b61007;
  82         imm32 p4, 0x250d1009;
  83         imm32 p5, 0x260ae00b;
  84         imm32 sp, 0x700c110d;
  85         imm32 fp, 0x900e104f;
  86         P1 = ( P1 + P4 ) << 1;
  87         P2 = ( P2 + P4 ) << 2;
  88         P3 = ( P3 + P4 ) << 2;
  89         P4 = ( P4 + P4 ) << 2;
  90         P5 = ( P5 + P4 ) << 1;
  91         SP = ( SP + P4 ) << 2;
  92         FP = ( FP + P4 ) << 2;
  93         CHECKREG p1, 0x8A1E4018;
  94         CHECKREG p2, 0x44448038;
  95         CHECKREG p3, 0x970C8040;
  96         CHECKREG p4, 0x28688048;
  97         CHECKREG p5, 0x9CE6C0A6;
  98         CHECKREG sp, 0x61D24554;
  99         CHECKREG fp, 0xE1DA425C;
 100
 101         imm32 p1, 0xae021003;
 102         imm32 p2, 0x22041705;
 103         imm32 p3, 0x20361487;
 104         imm32 p4, 0x90743009;
 105         imm32 p5, 0xa60aa00b;
 106         imm32 sp, 0xb00c1b0d;
 107         imm32 fp, 0x200e10cf;
 108         P1 = ( P1 + P5 ) << 2;
 109         P2 = ( P2 + P5 ) << 2;
 110         P3 = ( P3 + P5 ) << 2;
 111         P4 = ( P4 + P5 ) << 2;
 112         P5 = ( P5 + P5 ) << 1;
 113         SP = ( SP + P5 ) << 2;
 114         FP = ( FP + P5 ) << 2;
 115         CHECKREG p1, 0x5032C038;
 116         CHECKREG p2, 0x203ADC40;
 117         CHECKREG p3, 0x1902D248;
 118         CHECKREG p4, 0xD9FB4050;
 119         CHECKREG p5, 0x982A802C;
 120         CHECKREG sp, 0x20DA6CE4;
 121         CHECKREG fp, 0xE0E243EC;
 122
 123         imm32 p1, 0x50021003;
 124         imm32 p2, 0x62041005;
 125         imm32 p3, 0x70e61007;
 126         imm32 p4, 0x290f1009;
 127         imm32 p5, 0x700ab00b;
 128         imm32 sp, 0x2a0c1d0d;
 129         imm32 fp, 0xb00e1e0f;
 130         P1 = ( P1 + SP ) << 2;
 131         P2 = ( P2 + SP ) << 1;
 132         P3 = ( P3 + SP ) << 2;
 133         P4 = ( P4 + SP ) << 2;
 134         P5 = ( P5 + SP ) << 2;
 135         SP = ( SP + SP ) << 1;
 136         FP = ( FP + SP ) << 2;
 137         CHECKREG p1, 0xE838B440;
 138         CHECKREG p2, 0x18205A24;
 139         CHECKREG p3, 0x6BC8B450;
 140         CHECKREG p4, 0x4C6CB458;
 141         CHECKREG p5, 0x685B3460;
 142         CHECKREG sp, 0xA8307434;
 143         CHECKREG fp, 0x60FA490C;
 144
 145         imm32 p1, 0x32002003;
 146         imm32 p2, 0x24004005;
 147         imm32 p3, 0xe0506007;
 148         imm32 p4, 0xd0068009;
 149         imm32 p5, 0x230ae00b;
 150         imm32 sp, 0x205c1f0d;
 151         imm32 fp, 0x200e10bf;
 152         P1 = ( P1 + FP ) << 2;
 153         P2 = ( P2 + FP ) << 1;
 154         P3 = ( P3 + FP ) << 2;
 155         P4 = ( P4 + FP ) << 2;
 156         P5 = ( P5 + FP ) << 2;
 157         SP = ( SP + FP ) << 2;
 158         FP = ( FP + FP ) << 2;
 159         CHECKREG p1, 0x4838C308;
 160         CHECKREG p2, 0x881CA188;
 161         CHECKREG p3, 0x0179C318;
 162         CHECKREG p4, 0xC0524320;
 163         CHECKREG p5, 0x0C63C328;
 164         CHECKREG sp, 0x01A8BF30;
 165         CHECKREG fp, 0x007085F8;
 166
 167         pass