sim/testsuite/bfin/c_regmv_imlb_dr.s

   1 //Original:/testcases/core/c_regmv_imlb_dr/c_regmv_imlb_dr.dsp
   2 // Spec Reference: regmv imlb to dr
   3 # mach: bfin
   4
   5 .include "testutils.inc"
   6         start
   7
   8
   9
  10
  11
  12
  13 // initialize source regs
  14 imm32 i0, 0x11111111;
  15 imm32 i1, 0x22222222;
  16 imm32 i2, 0x33333333;
  17 imm32 i3, 0x44444444;
  18
  19
  20 // i to dreg
  21 R0 = I0;
  22 R1 = I0;
  23 R2 = I0;
  24 R3 = I0;
  25 R4 = I1;
  26 R5 = I1;
  27 R6 = I1;
  28 R7 = I1;
  29 CHECKREG r0, 0x11111111;
  30 CHECKREG r1, 0x11111111;
  31 CHECKREG r2, 0x11111111;
  32 CHECKREG r3, 0x11111111;
  33 CHECKREG r4, 0x22222222;
  34 CHECKREG r5, 0x22222222;
  35 CHECKREG r6, 0x22222222;
  36 CHECKREG r7, 0x22222222;
  37
  38 R0 = I1;
  39 R1 = I1;
  40 R2 = I1;
  41 R3 = I1;
  42 R4 = I0;
  43 R5 = I0;
  44 R6 = I0;
  45 R7 = I0;
  46 CHECKREG r0, 0x22222222;
  47 CHECKREG r1, 0x22222222;
  48 CHECKREG r2, 0x22222222;
  49 CHECKREG r3, 0x22222222;
  50 CHECKREG r4, 0x11111111;
  51 CHECKREG r5, 0x11111111;
  52 CHECKREG r6, 0x11111111;
  53 CHECKREG r7, 0x11111111;
  54
  55
  56 // i to dreg
  57 R0 = I2;
  58 R1 = I2;
  59 R2 = I2;
  60 R3 = I2;
  61 R4 = I3;
  62 R5 = I3;
  63 R6 = I3;
  64 R7 = I3;
  65 CHECKREG r0, 0x33333333;
  66 CHECKREG r1, 0x33333333;
  67 CHECKREG r2, 0x33333333;
  68 CHECKREG r3, 0x33333333;
  69 CHECKREG r4, 0x44444444;
  70 CHECKREG r5, 0x44444444;
  71 CHECKREG r6, 0x44444444;
  72 CHECKREG r7, 0x44444444;
  73
  74 R0 = I3;
  75 R1 = I3;
  76 R2 = I3;
  77 R3 = I3;
  78 R4 = I2;
  79 R5 = I2;
  80 R6 = I2;
  81 R7 = I2;
  82 CHECKREG r0, 0x44444444;
  83 CHECKREG r1, 0x44444444;
  84 CHECKREG r2, 0x44444444;
  85 CHECKREG r3, 0x44444444;
  86 CHECKREG r4, 0x33333333;
  87 CHECKREG r5, 0x33333333;
  88 CHECKREG r6, 0x33333333;
  89 CHECKREG r7, 0x33333333;
  90
  91
  92 imm32 m0, 0x55555555;
  93 imm32 m1, 0x66666666;
  94 imm32 m2, 0x77777777;
  95 imm32 m3, 0x88888888;
  96 // m to dreg
  97 R0 = M0;
  98 R1 = M0;
  99 R2 = M0;
 100 R3 = M0;
 101 R4 = M1;
 102 R5 = M1;
 103 R6 = M1;
 104 R7 = M1;
 105 CHECKREG r0, 0x55555555;
 106 CHECKREG r1, 0x55555555;
 107 CHECKREG r2, 0x55555555;
 108 CHECKREG r3, 0x55555555;
 109 CHECKREG r4, 0x66666666;
 110 CHECKREG r5, 0x66666666;
 111 CHECKREG r6, 0x66666666;
 112 CHECKREG r7, 0x66666666;
 113
 114 R0 = M1;
 115 R1 = M1;
 116 R2 = M1;
 117 R3 = M1;
 118 R4 = M0;
 119 R5 = M0;
 120 R6 = M0;
 121 R7 = M0;
 122 CHECKREG r0, 0x66666666;
 123 CHECKREG r1, 0x66666666;
 124 CHECKREG r2, 0x66666666;
 125 CHECKREG r3, 0x66666666;
 126 CHECKREG r4, 0x55555555;
 127 CHECKREG r5, 0x55555555;
 128 CHECKREG r6, 0x55555555;
 129 CHECKREG r7, 0x55555555;
 130
 131 R0 = M2;
 132 R1 = M2;
 133 R2 = M2;
 134 R3 = M2;
 135 R4 = M3;
 136 R5 = M3;
 137 R6 = M3;
 138 R7 = M3;
 139 CHECKREG r0, 0x77777777;
 140 CHECKREG r1, 0x77777777;
 141 CHECKREG r2, 0x77777777;
 142 CHECKREG r3, 0x77777777;
 143 CHECKREG r4, 0x88888888;
 144 CHECKREG r5, 0x88888888;
 145 CHECKREG r6, 0x88888888;
 146 CHECKREG r7, 0x88888888;
 147
 148 R0 = M3;
 149 R1 = M3;
 150 R2 = M3;
 151 R3 = M3;
 152 R4 = M2;
 153 R5 = M2;
 154 R6 = M2;
 155 R7 = M2;
 156 CHECKREG r0, 0x88888888;
 157 CHECKREG r1, 0x88888888;
 158 CHECKREG r2, 0x88888888;
 159 CHECKREG r3, 0x88888888;
 160 CHECKREG r4, 0x77777777;
 161 CHECKREG r5, 0x77777777;
 162 CHECKREG r6, 0x77777777;
 163 CHECKREG r7, 0x77777777;
 164
 165 imm32 l0, 0x99999999;
 166 imm32 l1, 0xaaaaaaaa;
 167 imm32 l2, 0xbbbbbbbb;
 168 imm32 l3, 0xcccccccc;
 169 // l to dreg
 170 R0 = L0;
 171 R1 = L0;
 172 R2 = L0;
 173 R3 = L0;
 174 R4 = L1;
 175 R5 = L1;
 176 R6 = L1;
 177 R7 = L1;
 178 CHECKREG r0, 0x99999999;
 179 CHECKREG r1, 0x99999999;
 180 CHECKREG r2, 0x99999999;
 181 CHECKREG r3, 0x99999999;
 182 CHECKREG r4, 0xaaaaaaaa;
 183 CHECKREG r5, 0xaaaaaaaa;
 184 CHECKREG r6, 0xaaaaaaaa;
 185 CHECKREG r7, 0xaaaaaaaa;
 186
 187 R0 = L1;
 188 R1 = L1;
 189 R2 = L1;
 190 R3 = L1;
 191 R4 = L0;
 192 R5 = L0;
 193 R6 = L0;
 194 R7 = L0;
 195 CHECKREG r0, 0xaaaaaaaa;
 196 CHECKREG r1, 0xaaaaaaaa;
 197 CHECKREG r2, 0xaaaaaaaa;
 198 CHECKREG r3, 0xaaaaaaaa;
 199 CHECKREG r4, 0x99999999;
 200 CHECKREG r5, 0x99999999;
 201 CHECKREG r6, 0x99999999;
 202 CHECKREG r7, 0x99999999;
 203
 204
 205 R0 = L2;
 206 R1 = L2;
 207 R2 = L2;
 208 R3 = L2;
 209 R4 = L3;
 210 R5 = L3;
 211 R6 = L3;
 212 R7 = L3;
 213 CHECKREG r0, 0xbbbbbbbb;
 214 CHECKREG r1, 0xbbbbbbbb;
 215 CHECKREG r2, 0xbbbbbbbb;
 216 CHECKREG r3, 0xbbbbbbbb;
 217 CHECKREG r4, 0xcccccccc;
 218 CHECKREG r5, 0xcccccccc;
 219 CHECKREG r6, 0xcccccccc;
 220 CHECKREG r7, 0xcccccccc;
 221
 222 R0 = L3;
 223 R1 = L3;
 224 R2 = L3;
 225 R3 = L3;
 226 R4 = L2;
 227 R5 = L2;
 228 R6 = L2;
 229 R7 = L2;
 230 CHECKREG r0, 0xcccccccc;
 231 CHECKREG r1, 0xcccccccc;
 232 CHECKREG r2, 0xcccccccc;
 233 CHECKREG r3, 0xcccccccc;
 234 CHECKREG r4, 0xbbbbbbbb;
 235 CHECKREG r5, 0xbbbbbbbb;
 236 CHECKREG r6, 0xbbbbbbbb;
 237 CHECKREG r7, 0xbbbbbbbb;
 238
 239
 240 imm32 b0, 0xdddddddd;
 241 imm32 b1, 0xeeeeeeee;
 242 imm32 b2, 0xffffffff;
 243 imm32 b3, 0x12345678;
 244 // b to dreg
 245 R0 = B0;
 246 R1 = B0;
 247 R2 = B0;
 248 R3 = B0;
 249 R4 = B1;
 250 R5 = B1;
 251 R6 = B1;
 252 R7 = B1;
 253 CHECKREG r0, 0xdddddddd;
 254 CHECKREG r1, 0xdddddddd;
 255 CHECKREG r2, 0xdddddddd;
 256 CHECKREG r3, 0xdddddddd;
 257 CHECKREG r4, 0xeeeeeeee;
 258 CHECKREG r5, 0xeeeeeeee;
 259 CHECKREG r6, 0xeeeeeeee;
 260 CHECKREG r7, 0xeeeeeeee;
 261
 262 R0 = B1;
 263 R1 = B1;
 264 R2 = B1;
 265 R3 = B1;
 266 R4 = B0;
 267 R5 = B0;
 268 R6 = B0;
 269 R7 = B0;
 270 CHECKREG r0, 0xeeeeeeee;
 271 CHECKREG r1, 0xeeeeeeee;
 272 CHECKREG r2, 0xeeeeeeee;
 273 CHECKREG r3, 0xeeeeeeee;
 274 CHECKREG r4, 0xdddddddd;
 275 CHECKREG r5, 0xdddddddd;
 276 CHECKREG r6, 0xdddddddd;
 277 CHECKREG r7, 0xdddddddd;
 278
 279 R0 = B2;
 280 R1 = B2;
 281 R2 = B2;
 282 R3 = B2;
 283 R4 = B3;
 284 R5 = B3;
 285 R6 = B3;
 286 R7 = B3;
 287 CHECKREG r0, 0xffffffff;
 288 CHECKREG r1, 0xffffffff;
 289 CHECKREG r2, 0xffffffff;
 290 CHECKREG r3, 0xffffffff;
 291 CHECKREG r4, 0x12345678;
 292 CHECKREG r5, 0x12345678;
 293 CHECKREG r6, 0x12345678;
 294 CHECKREG r7, 0x12345678;
 295
 296 R0 = B3;
 297 R1 = B3;
 298 R2 = B3;
 299 R3 = B3;
 300 R4 = B2;
 301 R5 = B2;
 302 R6 = B2;
 303 R7 = B2;
 304 CHECKREG r0, 0x12345678;
 305 CHECKREG r1, 0x12345678;
 306 CHECKREG r2, 0x12345678;
 307 CHECKREG r3, 0x12345678;
 308 CHECKREG r4, 0xffffffff;
 309 CHECKREG r5, 0xffffffff;
 310 CHECKREG r6, 0xffffffff;
 311 CHECKREG r7, 0xffffffff;
 312
 313 pass