sim/testsuite/bfin/s7.s

   1 //  Test  r4 = VMAX/VMAX (r5,r1)  A0>>2;
   2 # mach: bfin
   3
   4 .include "testutils.inc"
   5         start
   6
   7
   8 // Both max values are in high half, hence both bits
   9 // into A0 are 1
  10         A0 = 0;
  11         R1.L = 0x2;     // max in r1 is 3
  12         R1.H = 0x3;
  13
  14         R0.L = 0x6;     // max in r0 is 7
  15         R0.H = 0x7;
  16
  17         R6 = VIT_MAX( R1 , R0 ) (ASR);
  18
  19         DBGA ( R6.L , 0x0007 );
  20         DBGA ( R6.H , 0x0003 );
  21         R7 = A0.w;
  22         DBGA ( R7.L , 0x0000 );
  23         DBGA ( R7.H , 0xc000 );
  24         R7.L = A0.x;
  25         DBGA ( R7.L , 0x0000 );
  26
  27 // max value in r1 is in low, so second bit into A0 is zero
  28         A0 = 0;
  29         R1.L = 0x3;     // max in r1 is 3
  30         R1.H = 0x2;
  31
  32         R0.L = 0x6;     // max in r0 is 7
  33         R0.H = 0x7;
  34
  35         R6 = VIT_MAX( R1 , R0 ) (ASR);
  36
  37         DBGA ( R6.L , 0x0007 );
  38         DBGA ( R6.H , 0x0003 );
  39         R7 = A0.w;
  40         DBGA ( R7.L , 0x0000 );
  41         DBGA ( R7.H , 0x4000 );
  42         R7.L = A0.x;
  43         DBGA ( R7.L , 0x0000 );
  44
  45 // both max values in low, so both bits into A0 are zero
  46         R0.L = 0x8000;
  47         R0.H = 0x0;
  48         A0.w = R0;
  49         R1.L = 0x3;     // max in r1 is 3
  50         R1.H = 0x2;
  51
  52         R0.L = 0x7;     // max in r0 is 7
  53         R0.H = 0x6;
  54
  55         R6 = VIT_MAX( R1 , R0 ) (ASR);
  56
  57         DBGA ( R6.L , 0x0007 );
  58         DBGA ( R6.H , 0x0003 );
  59         R7 = A0.w;
  60         DBGA ( R7.L , 0x2000 );
  61         DBGA ( R7.H , 0x0000 );
  62         R7.L = A0.x;
  63         DBGA ( R7.L , 0x0000 );
  64
  65 // Test for correct max when one value overflows
  66         A0 = 0;
  67         R1.L = 0x7fff;  // max in r1 is 0x8001 (overflowed)
  68         R1.H = 0x8001;
  69
  70         R0.L = 0x6;     // max in r0 is 7
  71         R0.H = 0x7;
  72
  73         R6 = VIT_MAX( R1 , R0 ) (ASR);
  74
  75         DBGA ( R6.L , 0x0007 );
  76         DBGA ( R6.H , 0x8001 );
  77         R7 = A0.w;
  78         DBGA ( R7.L , 0x0000 );
  79         DBGA ( R7.H , 0xc000 );
  80         R7.L = A0.x;
  81         DBGA ( R7.L , 0x0000 );
  82
  83         pass