sim/m32r/cpux.c

   1 /* Misc. support for CPU family m32rxf.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright 1996-2018 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU simulators.
   8
   9    This file is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    It is distributed in the hope that it will be useful, but WITHOUT
  15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  17    License for more details.
  18
  19    You should have received a copy of the GNU General Public License along
  20    with this program; if not, see <http://www.gnu.org/licenses/>.
  21
  22 */
  23
  24 #define WANT_CPU m32rxf
  25 #define WANT_CPU_M32RXF
  26
  27 #include "sim-main.h"
  28 #include "cgen-ops.h"
  29
  30 /* Get the value of h-pc.  */
  31
  32 USI
  33 m32rxf_h_pc_get (SIM_CPU *current_cpu)
  34 {
  35   return CPU (h_pc);
  36 }
  37
  38 /* Set a value for h-pc.  */
  39
  40 void
  41 m32rxf_h_pc_set (SIM_CPU *current_cpu, USI newval)
  42 {
  43   CPU (h_pc) = newval;
  44 }
  45
  46 /* Get the value of h-gr.  */
  47
  48 SI
  49 m32rxf_h_gr_get (SIM_CPU *current_cpu, UINT regno)
  50 {
  51   return CPU (h_gr[regno]);
  52 }
  53
  54 /* Set a value for h-gr.  */
  55
  56 void
  57 m32rxf_h_gr_set (SIM_CPU *current_cpu, UINT regno, SI newval)
  58 {
  59   CPU (h_gr[regno]) = newval;
  60 }
  61
  62 /* Get the value of h-cr.  */
  63
  64 USI
  65 m32rxf_h_cr_get (SIM_CPU *current_cpu, UINT regno)
  66 {
  67   return GET_H_CR (regno);
  68 }
  69
  70 /* Set a value for h-cr.  */
  71
  72 void
  73 m32rxf_h_cr_set (SIM_CPU *current_cpu, UINT regno, USI newval)
  74 {
  75   SET_H_CR (regno, newval);
  76 }
  77
  78 /* Get the value of h-accum.  */
  79
  80 DI
  81 m32rxf_h_accum_get (SIM_CPU *current_cpu)
  82 {
  83   return GET_H_ACCUM ();
  84 }
  85
  86 /* Set a value for h-accum.  */
  87
  88 void
  89 m32rxf_h_accum_set (SIM_CPU *current_cpu, DI newval)
  90 {
  91   SET_H_ACCUM (newval);
  92 }
  93
  94 /* Get the value of h-accums.  */
  95
  96 DI
  97 m32rxf_h_accums_get (SIM_CPU *current_cpu, UINT regno)
  98 {
  99   return GET_H_ACCUMS (regno);
 100 }
 101
 102 /* Set a value for h-accums.  */
 103
 104 void
 105 m32rxf_h_accums_set (SIM_CPU *current_cpu, UINT regno, DI newval)
 106 {
 107   SET_H_ACCUMS (regno, newval);
 108 }
 109
 110 /* Get the value of h-cond.  */
 111
 112 BI
 113 m32rxf_h_cond_get (SIM_CPU *current_cpu)
 114 {
 115   return CPU (h_cond);
 116 }
 117
 118 /* Set a value for h-cond.  */
 119
 120 void
 121 m32rxf_h_cond_set (SIM_CPU *current_cpu, BI newval)
 122 {
 123   CPU (h_cond) = newval;
 124 }
 125
 126 /* Get the value of h-psw.  */
 127
 128 UQI
 129 m32rxf_h_psw_get (SIM_CPU *current_cpu)
 130 {
 131   return GET_H_PSW ();
 132 }
 133
 134 /* Set a value for h-psw.  */
 135
 136 void
 137 m32rxf_h_psw_set (SIM_CPU *current_cpu, UQI newval)
 138 {
 139   SET_H_PSW (newval);
 140 }
 141
 142 /* Get the value of h-bpsw.  */
 143
 144 UQI
 145 m32rxf_h_bpsw_get (SIM_CPU *current_cpu)
 146 {
 147   return CPU (h_bpsw);
 148 }
 149
 150 /* Set a value for h-bpsw.  */
 151
 152 void
 153 m32rxf_h_bpsw_set (SIM_CPU *current_cpu, UQI newval)
 154 {
 155   CPU (h_bpsw) = newval;
 156 }
 157
 158 /* Get the value of h-bbpsw.  */
 159
 160 UQI
 161 m32rxf_h_bbpsw_get (SIM_CPU *current_cpu)
 162 {
 163   return CPU (h_bbpsw);
 164 }
 165
 166 /* Set a value for h-bbpsw.  */
 167
 168 void
 169 m32rxf_h_bbpsw_set (SIM_CPU *current_cpu, UQI newval)
 170 {
 171   CPU (h_bbpsw) = newval;
 172 }
 173
 174 /* Get the value of h-lock.  */
 175
 176 BI
 177 m32rxf_h_lock_get (SIM_CPU *current_cpu)
 178 {
 179   return CPU (h_lock);
 180 }
 181
 182 /* Set a value for h-lock.  */
 183
 184 void
 185 m32rxf_h_lock_set (SIM_CPU *current_cpu, BI newval)
 186 {
 187   CPU (h_lock) = newval;
 188 }
 189
 190 /* Record trace results for INSN.  */
 191
 192 void
 193 m32rxf_record_trace_results (SIM_CPU *current_cpu, CGEN_INSN *insn,
 194                             int *indices, TRACE_RECORD *tr)
 195 {
 196 }