sim/m32r/m32r-sim.h

   1 /* collection of junk waiting time to sort out
   2    Copyright (C) 1996-2018 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5    This file is part of GDB, the GNU debugger.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #ifndef M32R_SIM_H
  21 #define M32R_SIM_H
  22
  23 /* GDB register numbers.  */
  24 #define PSW_REGNUM      16
  25 #define CBR_REGNUM      17
  26 #define SPI_REGNUM      18
  27 #define SPU_REGNUM      19
  28 #define BPC_REGNUM      20
  29 #define PC_REGNUM       21
  30 #define ACCL_REGNUM     22
  31 #define ACCH_REGNUM     23
  32 #define ACC1L_REGNUM    24
  33 #define ACC1H_REGNUM    25
  34 #define BBPSW_REGNUM    26
  35 #define BBPC_REGNUM     27
  36 #define EVB_REGNUM      28
  37
  38 extern int m32r_decode_gdb_ctrl_regnum (int);
  39
  40 /* Cover macros for hardware accesses.
  41    FIXME: Eventually move to cgen.  */
  42 #define GET_H_SM() ((CPU (h_psw) & 0x80) != 0)
  43
  44 #ifndef GET_H_CR
  45 extern USI  m32rbf_h_cr_get_handler (SIM_CPU *, UINT);
  46 extern void m32rbf_h_cr_set_handler (SIM_CPU *, UINT, USI);
  47
  48 #define GET_H_CR(regno) \
  49   XCONCAT2 (WANT_CPU,_h_cr_get_handler) (current_cpu, (regno))
  50 #define SET_H_CR(regno, val) \
  51   XCONCAT2 (WANT_CPU,_h_cr_set_handler) (current_cpu, (regno), (val))
  52 #endif
  53
  54 #ifndef  GET_H_PSW
  55 extern UQI  m32rbf_h_psw_get_handler (SIM_CPU *);
  56 extern void m32rbf_h_psw_set_handler (SIM_CPU *, UQI);
  57
  58 #define GET_H_PSW() \
  59   XCONCAT2 (WANT_CPU,_h_psw_get_handler) (current_cpu)
  60 #define SET_H_PSW(val) \
  61   XCONCAT2 (WANT_CPU,_h_psw_set_handler) (current_cpu, (val))
  62 #endif
  63
  64 #ifndef  GET_H_ACCUM
  65 extern DI   m32rbf_h_accum_get_handler (SIM_CPU *);
  66 extern void m32rbf_h_accum_set_handler (SIM_CPU *, DI);
  67
  68 #define GET_H_ACCUM() \
  69   XCONCAT2 (WANT_CPU,_h_accum_get_handler) (current_cpu)
  70 #define SET_H_ACCUM(val) \
  71   XCONCAT2 (WANT_CPU,_h_accum_set_handler) (current_cpu, (val))
  72 #endif
  73 \f
  74 /* Misc. profile data.  */
  75
  76 typedef struct {
  77   /* nop insn slot filler count */
  78   unsigned int fillnop_count;
  79   /* number of parallel insns */
  80   unsigned int parallel_count;
  81
  82   /* FIXME: generalize this to handle all insn lengths, move to common.  */
  83   /* number of short insns, not including parallel ones */
  84   unsigned int short_count;
  85   /* number of long insns */
  86   unsigned int long_count;
  87
  88   /* Working area for computing cycle counts.  */
  89   unsigned long insn_cycles; /* FIXME: delete */
  90   unsigned long cti_stall;
  91   unsigned long load_stall;
  92   unsigned long biggest_cycles;
  93
  94   /* Bitmask of registers loaded by previous insn.  */
  95   unsigned int load_regs;
  96   /* Bitmask of registers loaded by current insn.  */
  97   unsigned int load_regs_pending;
  98 } M32R_MISC_PROFILE;
  99
 100 /* Initialize the working area.  */
 101 void m32r_init_insn_cycles (SIM_CPU *, int);
 102 /* Update the totals for the insn.  */
 103 void m32r_record_insn_cycles (SIM_CPU *, int);
 104
 105 /* This is invoked by the nop pattern in the .cpu file.  */
 106 #define PROFILE_COUNT_FILLNOPS(cpu, addr) \
 107 do { \
 108   if (PROFILE_INSN_P (cpu) \
 109       && (addr & 3) != 0) \
 110     ++ CPU_M32R_MISC_PROFILE (cpu)->fillnop_count; \
 111 } while (0)
 112
 113 /* This is invoked by the execute section of mloop{,x}.in.  */
 114 #define PROFILE_COUNT_PARINSNS(cpu) \
 115 do { \
 116   if (PROFILE_INSN_P (cpu)) \
 117     ++ CPU_M32R_MISC_PROFILE (cpu)->parallel_count; \
 118 } while (0)
 119
 120 /* This is invoked by the execute section of mloop{,x}.in.  */
 121 #define PROFILE_COUNT_SHORTINSNS(cpu) \
 122 do { \
 123   if (PROFILE_INSN_P (cpu)) \
 124     ++ CPU_M32R_MISC_PROFILE (cpu)->short_count; \
 125 } while (0)
 126
 127 /* This is invoked by the execute section of mloop{,x}.in.  */
 128 #define PROFILE_COUNT_LONGINSNS(cpu) \
 129 do { \
 130   if (PROFILE_INSN_P (cpu)) \
 131     ++ CPU_M32R_MISC_PROFILE (cpu)->long_count; \
 132 } while (0)
 133 \f
 134 #define GETTWI GETTSI
 135 #define SETTWI SETTSI
 136 \f
 137 /* Additional execution support.  */
 138
 139 \f
 140 /* Hardware/device support.
 141    ??? Will eventually want to move device stuff to config files.  */
 142
 143 /* Exception, Interrupt, and Trap addresses */
 144 #define EIT_SYSBREAK_ADDR       0x10
 145 #define EIT_RSVD_INSN_ADDR      0x20
 146 #define EIT_ADDR_EXCP_ADDR      0x30
 147 #define EIT_TRAP_BASE_ADDR      0x40
 148 #define EIT_EXTERN_ADDR         0x80
 149 #define EIT_RESET_ADDR          0x7ffffff0
 150 #define EIT_WAKEUP_ADDR         0x7ffffff0
 151
 152 /* Special purpose traps.  */
 153 #define TRAP_SYSCALL    0
 154 #define TRAP_BREAKPOINT 1
 155
 156 /* Handle the trap insn.  */
 157 USI m32r_trap (SIM_CPU *, PCADDR, int);
 158
 159 #endif /* M32R_SIM_H */