sim/m32r/decode.c

   1 /* Simulator instruction decoder for m32rbf.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996-2024 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU simulators.
   8
   9    This file is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    It is distributed in the hope that it will be useful, but WITHOUT
  15    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  16    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  17    License for more details.
  18
  19    You should have received a copy of the GNU General Public License along
  20    with this program; if not, write to the Free Software Foundation, Inc.,
  21    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  22
  23 */
  24
  25 #define WANT_CPU m32rbf
  26 #define WANT_CPU_M32RBF
  27
  28 #include "sim-main.h"
  29 #include "sim-assert.h"
  30 #include "cgen-mem.h"
  31 #include "cgen-ops.h"
  32
  33 /* The instruction descriptor array.
  34    This is computed at runtime.  Space for it is not malloc'd to save a
  35    teensy bit of cpu in the decoder.  Moving it to malloc space is trivial
  36    but won't be done until necessary (we don't currently support the runtime
  37    addition of instructions nor an SMP machine with different cpus).  */
  38 static IDESC m32rbf_insn_data[M32RBF_INSN__MAX];
  39
  40 /* Commas between elements are contained in the macros.
  41    Some of these are conditionally compiled out.  */
  42
  43 static const struct insn_sem m32rbf_insn_sem[] =
  44 {
  45   { VIRTUAL_INSN_X_INVALID, M32RBF_INSN_X_INVALID, M32RBF_SFMT_EMPTY },
  46   { VIRTUAL_INSN_X_AFTER, M32RBF_INSN_X_AFTER, M32RBF_SFMT_EMPTY },
  47   { VIRTUAL_INSN_X_BEFORE, M32RBF_INSN_X_BEFORE, M32RBF_SFMT_EMPTY },
  48   { VIRTUAL_INSN_X_CTI_CHAIN, M32RBF_INSN_X_CTI_CHAIN, M32RBF_SFMT_EMPTY },
  49   { VIRTUAL_INSN_X_CHAIN, M32RBF_INSN_X_CHAIN, M32RBF_SFMT_EMPTY },
  50   { VIRTUAL_INSN_X_BEGIN, M32RBF_INSN_X_BEGIN, M32RBF_SFMT_EMPTY },
  51   { M32R_INSN_ADD, M32RBF_INSN_ADD, M32RBF_SFMT_ADD },
  52   { M32R_INSN_ADD3, M32RBF_INSN_ADD3, M32RBF_SFMT_ADD3 },
  53   { M32R_INSN_AND, M32RBF_INSN_AND, M32RBF_SFMT_ADD },
  54   { M32R_INSN_AND3, M32RBF_INSN_AND3, M32RBF_SFMT_AND3 },
  55   { M32R_INSN_OR, M32RBF_INSN_OR, M32RBF_SFMT_ADD },
  56   { M32R_INSN_OR3, M32RBF_INSN_OR3, M32RBF_SFMT_OR3 },
  57   { M32R_INSN_XOR, M32RBF_INSN_XOR, M32RBF_SFMT_ADD },
  58   { M32R_INSN_XOR3, M32RBF_INSN_XOR3, M32RBF_SFMT_AND3 },
  59   { M32R_INSN_ADDI, M32RBF_INSN_ADDI, M32RBF_SFMT_ADDI },
  60   { M32R_INSN_ADDV, M32RBF_INSN_ADDV, M32RBF_SFMT_ADDV },
  61   { M32R_INSN_ADDV3, M32RBF_INSN_ADDV3, M32RBF_SFMT_ADDV3 },
  62   { M32R_INSN_ADDX, M32RBF_INSN_ADDX, M32RBF_SFMT_ADDX },
  63   { M32R_INSN_BC8, M32RBF_INSN_BC8, M32RBF_SFMT_BC8 },
  64   { M32R_INSN_BC24, M32RBF_INSN_BC24, M32RBF_SFMT_BC24 },
  65   { M32R_INSN_BEQ, M32RBF_INSN_BEQ, M32RBF_SFMT_BEQ },
  66   { M32R_INSN_BEQZ, M32RBF_INSN_BEQZ, M32RBF_SFMT_BEQZ },
  67   { M32R_INSN_BGEZ, M32RBF_INSN_BGEZ, M32RBF_SFMT_BEQZ },
  68   { M32R_INSN_BGTZ, M32RBF_INSN_BGTZ, M32RBF_SFMT_BEQZ },
  69   { M32R_INSN_BLEZ, M32RBF_INSN_BLEZ, M32RBF_SFMT_BEQZ },
  70   { M32R_INSN_BLTZ, M32RBF_INSN_BLTZ, M32RBF_SFMT_BEQZ },
  71   { M32R_INSN_BNEZ, M32RBF_INSN_BNEZ, M32RBF_SFMT_BEQZ },
  72   { M32R_INSN_BL8, M32RBF_INSN_BL8, M32RBF_SFMT_BL8 },
  73   { M32R_INSN_BL24, M32RBF_INSN_BL24, M32RBF_SFMT_BL24 },
  74   { M32R_INSN_BNC8, M32RBF_INSN_BNC8, M32RBF_SFMT_BC8 },
  75   { M32R_INSN_BNC24, M32RBF_INSN_BNC24, M32RBF_SFMT_BC24 },
  76   { M32R_INSN_BNE, M32RBF_INSN_BNE, M32RBF_SFMT_BEQ },
  77   { M32R_INSN_BRA8, M32RBF_INSN_BRA8, M32RBF_SFMT_BRA8 },
  78   { M32R_INSN_BRA24, M32RBF_INSN_BRA24, M32RBF_SFMT_BRA24 },
  79   { M32R_INSN_CMP, M32RBF_INSN_CMP, M32RBF_SFMT_CMP },
  80   { M32R_INSN_CMPI, M32RBF_INSN_CMPI, M32RBF_SFMT_CMPI },
  81   { M32R_INSN_CMPU, M32RBF_INSN_CMPU, M32RBF_SFMT_CMP },
  82   { M32R_INSN_CMPUI, M32RBF_INSN_CMPUI, M32RBF_SFMT_CMPI },
  83   { M32R_INSN_DIV, M32RBF_INSN_DIV, M32RBF_SFMT_DIV },
  84   { M32R_INSN_DIVU, M32RBF_INSN_DIVU, M32RBF_SFMT_DIV },
  85   { M32R_INSN_REM, M32RBF_INSN_REM, M32RBF_SFMT_DIV },
  86   { M32R_INSN_REMU, M32RBF_INSN_REMU, M32RBF_SFMT_DIV },
  87   { M32R_INSN_JL, M32RBF_INSN_JL, M32RBF_SFMT_JL },
  88   { M32R_INSN_JMP, M32RBF_INSN_JMP, M32RBF_SFMT_JMP },
  89   { M32R_INSN_LD, M32RBF_INSN_LD, M32RBF_SFMT_LD },
  90   { M32R_INSN_LD_D, M32RBF_INSN_LD_D, M32RBF_SFMT_LD_D },
  91   { M32R_INSN_LDB, M32RBF_INSN_LDB, M32RBF_SFMT_LDB },
  92   { M32R_INSN_LDB_D, M32RBF_INSN_LDB_D, M32RBF_SFMT_LDB_D },
  93   { M32R_INSN_LDH, M32RBF_INSN_LDH, M32RBF_SFMT_LDH },
  94   { M32R_INSN_LDH_D, M32RBF_INSN_LDH_D, M32RBF_SFMT_LDH_D },
  95   { M32R_INSN_LDUB, M32RBF_INSN_LDUB, M32RBF_SFMT_LDB },
  96   { M32R_INSN_LDUB_D, M32RBF_INSN_LDUB_D, M32RBF_SFMT_LDB_D },
  97   { M32R_INSN_LDUH, M32RBF_INSN_LDUH, M32RBF_SFMT_LDH },
  98   { M32R_INSN_LDUH_D, M32RBF_INSN_LDUH_D, M32RBF_SFMT_LDH_D },
  99   { M32R_INSN_LD_PLUS, M32RBF_INSN_LD_PLUS, M32RBF_SFMT_LD_PLUS },
 100   { M32R_INSN_LD24, M32RBF_INSN_LD24, M32RBF_SFMT_LD24 },
 101   { M32R_INSN_LDI8, M32RBF_INSN_LDI8, M32RBF_SFMT_LDI8 },
 102   { M32R_INSN_LDI16, M32RBF_INSN_LDI16, M32RBF_SFMT_LDI16 },
 103   { M32R_INSN_LOCK, M32RBF_INSN_LOCK, M32RBF_SFMT_LOCK },
 104   { M32R_INSN_MACHI, M32RBF_INSN_MACHI, M32RBF_SFMT_MACHI },
 105   { M32R_INSN_MACLO, M32RBF_INSN_MACLO, M32RBF_SFMT_MACHI },
 106   { M32R_INSN_MACWHI, M32RBF_INSN_MACWHI, M32RBF_SFMT_MACHI },
 107   { M32R_INSN_MACWLO, M32RBF_INSN_MACWLO, M32RBF_SFMT_MACHI },
 108   { M32R_INSN_MUL, M32RBF_INSN_MUL, M32RBF_SFMT_ADD },
 109   { M32R_INSN_MULHI, M32RBF_INSN_MULHI, M32RBF_SFMT_MULHI },
 110   { M32R_INSN_MULLO, M32RBF_INSN_MULLO, M32RBF_SFMT_MULHI },
 111   { M32R_INSN_MULWHI, M32RBF_INSN_MULWHI, M32RBF_SFMT_MULHI },
 112   { M32R_INSN_MULWLO, M32RBF_INSN_MULWLO, M32RBF_SFMT_MULHI },
 113   { M32R_INSN_MV, M32RBF_INSN_MV, M32RBF_SFMT_MV },
 114   { M32R_INSN_MVFACHI, M32RBF_INSN_MVFACHI, M32RBF_SFMT_MVFACHI },
 115   { M32R_INSN_MVFACLO, M32RBF_INSN_MVFACLO, M32RBF_SFMT_MVFACHI },
 116   { M32R_INSN_MVFACMI, M32RBF_INSN_MVFACMI, M32RBF_SFMT_MVFACHI },
 117   { M32R_INSN_MVFC, M32RBF_INSN_MVFC, M32RBF_SFMT_MVFC },
 118   { M32R_INSN_MVTACHI, M32RBF_INSN_MVTACHI, M32RBF_SFMT_MVTACHI },
 119   { M32R_INSN_MVTACLO, M32RBF_INSN_MVTACLO, M32RBF_SFMT_MVTACHI },
 120   { M32R_INSN_MVTC, M32RBF_INSN_MVTC, M32RBF_SFMT_MVTC },
 121   { M32R_INSN_NEG, M32RBF_INSN_NEG, M32RBF_SFMT_MV },
 122   { M32R_INSN_NOP, M32RBF_INSN_NOP, M32RBF_SFMT_NOP },
 123   { M32R_INSN_NOT, M32RBF_INSN_NOT, M32RBF_SFMT_MV },
 124   { M32R_INSN_RAC, M32RBF_INSN_RAC, M32RBF_SFMT_RAC },
 125   { M32R_INSN_RACH, M32RBF_INSN_RACH, M32RBF_SFMT_RAC },
 126   { M32R_INSN_RTE, M32RBF_INSN_RTE, M32RBF_SFMT_RTE },
 127   { M32R_INSN_SETH, M32RBF_INSN_SETH, M32RBF_SFMT_SETH },
 128   { M32R_INSN_SLL, M32RBF_INSN_SLL, M32RBF_SFMT_ADD },
 129   { M32R_INSN_SLL3, M32RBF_INSN_SLL3, M32RBF_SFMT_SLL3 },
 130   { M32R_INSN_SLLI, M32RBF_INSN_SLLI, M32RBF_SFMT_SLLI },
 131   { M32R_INSN_SRA, M32RBF_INSN_SRA, M32RBF_SFMT_ADD },
 132   { M32R_INSN_SRA3, M32RBF_INSN_SRA3, M32RBF_SFMT_SLL3 },
 133   { M32R_INSN_SRAI, M32RBF_INSN_SRAI, M32RBF_SFMT_SLLI },
 134   { M32R_INSN_SRL, M32RBF_INSN_SRL, M32RBF_SFMT_ADD },
 135   { M32R_INSN_SRL3, M32RBF_INSN_SRL3, M32RBF_SFMT_SLL3 },
 136   { M32R_INSN_SRLI, M32RBF_INSN_SRLI, M32RBF_SFMT_SLLI },
 137   { M32R_INSN_ST, M32RBF_INSN_ST, M32RBF_SFMT_ST },
 138   { M32R_INSN_ST_D, M32RBF_INSN_ST_D, M32RBF_SFMT_ST_D },
 139   { M32R_INSN_STB, M32RBF_INSN_STB, M32RBF_SFMT_STB },
 140   { M32R_INSN_STB_D, M32RBF_INSN_STB_D, M32RBF_SFMT_STB_D },
 141   { M32R_INSN_STH, M32RBF_INSN_STH, M32RBF_SFMT_STH },
 142   { M32R_INSN_STH_D, M32RBF_INSN_STH_D, M32RBF_SFMT_STH_D },
 143   { M32R_INSN_ST_PLUS, M32RBF_INSN_ST_PLUS, M32RBF_SFMT_ST_PLUS },
 144   { M32R_INSN_ST_MINUS, M32RBF_INSN_ST_MINUS, M32RBF_SFMT_ST_PLUS },
 145   { M32R_INSN_SUB, M32RBF_INSN_SUB, M32RBF_SFMT_ADD },
 146   { M32R_INSN_SUBV, M32RBF_INSN_SUBV, M32RBF_SFMT_ADDV },
 147   { M32R_INSN_SUBX, M32RBF_INSN_SUBX, M32RBF_SFMT_ADDX },
 148   { M32R_INSN_TRAP, M32RBF_INSN_TRAP, M32RBF_SFMT_TRAP },
 149   { M32R_INSN_UNLOCK, M32RBF_INSN_UNLOCK, M32RBF_SFMT_UNLOCK },
 150   { M32R_INSN_CLRPSW, M32RBF_INSN_CLRPSW, M32RBF_SFMT_CLRPSW },
 151   { M32R_INSN_SETPSW, M32RBF_INSN_SETPSW, M32RBF_SFMT_SETPSW },
 152   { M32R_INSN_BSET, M32RBF_INSN_BSET, M32RBF_SFMT_BSET },
 153   { M32R_INSN_BCLR, M32RBF_INSN_BCLR, M32RBF_SFMT_BSET },
 154   { M32R_INSN_BTST, M32RBF_INSN_BTST, M32RBF_SFMT_BTST },
 155 };
 156
 157 static const struct insn_sem m32rbf_insn_sem_invalid =
 158 {
 159   VIRTUAL_INSN_X_INVALID, M32RBF_INSN_X_INVALID, M32RBF_SFMT_EMPTY
 160 };
 161
 162 /* Initialize an IDESC from the compile-time computable parts.  */
 163
 164 static INLINE void
 165 init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
 166 {
 167   const CGEN_INSN *insn_table = CGEN_CPU_INSN_TABLE (CPU_CPU_DESC (cpu))->init_entries;
 168
 169   id->num = t->index;
 170   id->sfmt = t->sfmt;
 171   if ((int) t->type <= 0)
 172     id->idata = & cgen_virtual_insn_table[- (int) t->type];
 173   else
 174     id->idata = & insn_table[t->type];
 175   id->attrs = CGEN_INSN_ATTRS (id->idata);
 176   /* Oh my god, a magic number.  */
 177   id->length = CGEN_INSN_BITSIZE (id->idata) / 8;
 178
 179 #if WITH_PROFILE_MODEL_P
 180   id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
 181   {
 182     SIM_DESC sd = CPU_STATE (cpu);
 183     SIM_ASSERT (t->index == id->timing->num);
 184   }
 185 #endif
 186
 187   /* Semantic pointers are initialized elsewhere.  */
 188 }
 189
 190 /* Initialize the instruction descriptor table.  */
 191
 192 void
 193 m32rbf_init_idesc_table (SIM_CPU *cpu)
 194 {
 195   IDESC *id,*tabend;
 196   const struct insn_sem *t,*tend;
 197   int tabsize = M32RBF_INSN__MAX;
 198   IDESC *table = m32rbf_insn_data;
 199
 200   memset (table, 0, tabsize * sizeof (IDESC));
 201
 202   /* First set all entries to the `invalid insn'.  */
 203   t = & m32rbf_insn_sem_invalid;
 204   for (id = table, tabend = table + tabsize; id < tabend; ++id)
 205     init_idesc (cpu, id, t);
 206
 207   /* Now fill in the values for the chosen cpu.  */
 208   for (t = m32rbf_insn_sem, tend = t + ARRAY_SIZE (m32rbf_insn_sem);
 209        t != tend; ++t)
 210     {
 211       init_idesc (cpu, & table[t->index], t);
 212     }
 213
 214   /* Link the IDESC table into the cpu.  */
 215   CPU_IDESC (cpu) = table;
 216 }
 217
 218 /* Given an instruction, return a pointer to its IDESC entry.  */
 219
 220 const IDESC *
 221 m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
 222               CGEN_INSN_WORD base_insn, CGEN_INSN_WORD entire_insn,
 223               ARGBUF *abuf)
 224 {
 225   /* Result of decoder.  */
 226   M32RBF_INSN_TYPE itype;
 227
 228   {
 229     CGEN_INSN_WORD insn = base_insn;
 230
 231     {
 232       unsigned int val0 = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
 233       switch (val0)
 234       {
 235       case 0: itype = M32RBF_INSN_SUBV; goto extract_sfmt_addv;
 236       case 1: itype = M32RBF_INSN_SUBX; goto extract_sfmt_addx;
 237       case 2: itype = M32RBF_INSN_SUB; goto extract_sfmt_add;
 238       case 3: itype = M32RBF_INSN_NEG; goto extract_sfmt_mv;
 239       case 4: itype = M32RBF_INSN_CMP; goto extract_sfmt_cmp;
 240       case 5: itype = M32RBF_INSN_CMPU; goto extract_sfmt_cmp;
 241       case 8: itype = M32RBF_INSN_ADDV; goto extract_sfmt_addv;
 242       case 9: itype = M32RBF_INSN_ADDX; goto extract_sfmt_addx;
 243       case 10: itype = M32RBF_INSN_ADD; goto extract_sfmt_add;
 244       case 11: itype = M32RBF_INSN_NOT; goto extract_sfmt_mv;
 245       case 12: itype = M32RBF_INSN_AND; goto extract_sfmt_add;
 246       case 13: itype = M32RBF_INSN_XOR; goto extract_sfmt_add;
 247       case 14: itype = M32RBF_INSN_OR; goto extract_sfmt_add;
 248       case 15:
 249         if ((entire_insn & 0xf8f0) == 0xf0)
 250           { itype = M32RBF_INSN_BTST; goto extract_sfmt_btst; }
 251         itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 252       case 16: itype = M32RBF_INSN_SRL; goto extract_sfmt_add;
 253       case 18: itype = M32RBF_INSN_SRA; goto extract_sfmt_add;
 254       case 20: itype = M32RBF_INSN_SLL; goto extract_sfmt_add;
 255       case 22: itype = M32RBF_INSN_MUL; goto extract_sfmt_add;
 256       case 24: itype = M32RBF_INSN_MV; goto extract_sfmt_mv;
 257       case 25: itype = M32RBF_INSN_MVFC; goto extract_sfmt_mvfc;
 258       case 26: itype = M32RBF_INSN_MVTC; goto extract_sfmt_mvtc;
 259       case 28:
 260         {
 261           unsigned int val1 = (((insn >> 8) & (1 << 0)));
 262           switch (val1)
 263           {
 264           case 0:
 265             if ((entire_insn & 0xfff0) == 0x1ec0)
 266               { itype = M32RBF_INSN_JL; goto extract_sfmt_jl; }
 267             itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 268           case 1:
 269             if ((entire_insn & 0xfff0) == 0x1fc0)
 270               { itype = M32RBF_INSN_JMP; goto extract_sfmt_jmp; }
 271             itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 272           default: itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 273           }
 274         }
 275       case 29:
 276         if ((entire_insn & 0xffff) == 0x10d6)
 277           { itype = M32RBF_INSN_RTE; goto extract_sfmt_rte; }
 278         itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 279       case 31:
 280         if ((entire_insn & 0xfff0) == 0x10f0)
 281           { itype = M32RBF_INSN_TRAP; goto extract_sfmt_trap; }
 282         itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 283       case 32: itype = M32RBF_INSN_STB; goto extract_sfmt_stb;
 284       case 34: itype = M32RBF_INSN_STH; goto extract_sfmt_sth;
 285       case 36: itype = M32RBF_INSN_ST; goto extract_sfmt_st;
 286       case 37: itype = M32RBF_INSN_UNLOCK; goto extract_sfmt_unlock;
 287       case 38: itype = M32RBF_INSN_ST_PLUS; goto extract_sfmt_st_plus;
 288       case 39: itype = M32RBF_INSN_ST_MINUS; goto extract_sfmt_st_plus;
 289       case 40: itype = M32RBF_INSN_LDB; goto extract_sfmt_ldb;
 290       case 41: itype = M32RBF_INSN_LDUB; goto extract_sfmt_ldb;
 291       case 42: itype = M32RBF_INSN_LDH; goto extract_sfmt_ldh;
 292       case 43: itype = M32RBF_INSN_LDUH; goto extract_sfmt_ldh;
 293       case 44: itype = M32RBF_INSN_LD; goto extract_sfmt_ld;
 294       case 45: itype = M32RBF_INSN_LOCK; goto extract_sfmt_lock;
 295       case 46: itype = M32RBF_INSN_LD_PLUS; goto extract_sfmt_ld_plus;
 296       case 48: itype = M32RBF_INSN_MULHI; goto extract_sfmt_mulhi;
 297       case 49: itype = M32RBF_INSN_MULLO; goto extract_sfmt_mulhi;
 298       case 50: itype = M32RBF_INSN_MULWHI; goto extract_sfmt_mulhi;
 299       case 51: itype = M32RBF_INSN_MULWLO; goto extract_sfmt_mulhi;
 300       case 52: itype = M32RBF_INSN_MACHI; goto extract_sfmt_machi;
 301       case 53: itype = M32RBF_INSN_MACLO; goto extract_sfmt_machi;
 302       case 54: itype = M32RBF_INSN_MACWHI; goto extract_sfmt_machi;
 303       case 55: itype = M32RBF_INSN_MACWLO; goto extract_sfmt_machi;
 304       case 64:
 305       case 65:
 306       case 66:
 307       case 67:
 308       case 68:
 309       case 69:
 310       case 70:
 311       case 71:
 312       case 72:
 313       case 73:
 314       case 74:
 315       case 75:
 316       case 76:
 317       case 77:
 318       case 78:
 319       case 79: itype = M32RBF_INSN_ADDI; goto extract_sfmt_addi;
 320       case 80:
 321       case 81: itype = M32RBF_INSN_SRLI; goto extract_sfmt_slli;
 322       case 82:
 323       case 83: itype = M32RBF_INSN_SRAI; goto extract_sfmt_slli;
 324       case 84:
 325       case 85: itype = M32RBF_INSN_SLLI; goto extract_sfmt_slli;
 326       case 87:
 327         {
 328           unsigned int val1 = (((insn >> 0) & (1 << 0)));
 329           switch (val1)
 330           {
 331           case 0:
 332             if ((entire_insn & 0xf0ff) == 0x5070)
 333               { itype = M32RBF_INSN_MVTACHI; goto extract_sfmt_mvtachi; }
 334             itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 335           case 1:
 336             if ((entire_insn & 0xf0ff) == 0x5071)
 337               { itype = M32RBF_INSN_MVTACLO; goto extract_sfmt_mvtachi; }
 338             itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 339           default: itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 340           }
 341         }
 342       case 88:
 343         if ((entire_insn & 0xffff) == 0x5080)
 344           { itype = M32RBF_INSN_RACH; goto extract_sfmt_rac; }
 345         itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 346       case 89:
 347         if ((entire_insn & 0xffff) == 0x5090)
 348           { itype = M32RBF_INSN_RAC; goto extract_sfmt_rac; }
 349         itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 350       case 95:
 351         {
 352           unsigned int val1 = (((insn >> 0) & (3 << 0)));
 353           switch (val1)
 354           {
 355           case 0:
 356             if ((entire_insn & 0xf0ff) == 0x50f0)
 357               { itype = M32RBF_INSN_MVFACHI; goto extract_sfmt_mvfachi; }
 358             itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 359           case 1:
 360             if ((entire_insn & 0xf0ff) == 0x50f1)
 361               { itype = M32RBF_INSN_MVFACLO; goto extract_sfmt_mvfachi; }
 362             itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 363           case 2:
 364             if ((entire_insn & 0xf0ff) == 0x50f2)
 365               { itype = M32RBF_INSN_MVFACMI; goto extract_sfmt_mvfachi; }
 366             itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 367           default: itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 368           }
 369         }
 370       case 96:
 371       case 97:
 372       case 98:
 373       case 99:
 374       case 100:
 375       case 101:
 376       case 102:
 377       case 103:
 378       case 104:
 379       case 105:
 380       case 106:
 381       case 107:
 382       case 108:
 383       case 109:
 384       case 110:
 385       case 111: itype = M32RBF_INSN_LDI8; goto extract_sfmt_ldi8;
 386       case 112:
 387         {
 388           unsigned int val1 = (((insn >> 8) & (15 << 0)));
 389           switch (val1)
 390           {
 391           case 0:
 392             if ((entire_insn & 0xffff) == 0x7000)
 393               { itype = M32RBF_INSN_NOP; goto extract_sfmt_nop; }
 394             itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 395           case 1: itype = M32RBF_INSN_SETPSW; goto extract_sfmt_setpsw;
 396           case 2: itype = M32RBF_INSN_CLRPSW; goto extract_sfmt_clrpsw;
 397           case 12: itype = M32RBF_INSN_BC8; goto extract_sfmt_bc8;
 398           case 13: itype = M32RBF_INSN_BNC8; goto extract_sfmt_bc8;
 399           case 14: itype = M32RBF_INSN_BL8; goto extract_sfmt_bl8;
 400           case 15: itype = M32RBF_INSN_BRA8; goto extract_sfmt_bra8;
 401           default: itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 402           }
 403         }
 404       case 113:
 405       case 114:
 406       case 115:
 407       case 116:
 408       case 117:
 409       case 118:
 410       case 119:
 411       case 120:
 412       case 121:
 413       case 122:
 414       case 123:
 415       case 124:
 416       case 125:
 417       case 126:
 418       case 127:
 419         {
 420           unsigned int val1 = (((insn >> 8) & (15 << 0)));
 421           switch (val1)
 422           {
 423           case 1: itype = M32RBF_INSN_SETPSW; goto extract_sfmt_setpsw;
 424           case 2: itype = M32RBF_INSN_CLRPSW; goto extract_sfmt_clrpsw;
 425           case 12: itype = M32RBF_INSN_BC8; goto extract_sfmt_bc8;
 426           case 13: itype = M32RBF_INSN_BNC8; goto extract_sfmt_bc8;
 427           case 14: itype = M32RBF_INSN_BL8; goto extract_sfmt_bl8;
 428           case 15: itype = M32RBF_INSN_BRA8; goto extract_sfmt_bra8;
 429           default: itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 430           }
 431         }
 432       case 132:
 433         if ((entire_insn & 0xfff00000) == 0x80400000)
 434           { itype = M32RBF_INSN_CMPI; goto extract_sfmt_cmpi; }
 435         itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 436       case 133:
 437         if ((entire_insn & 0xfff00000) == 0x80500000)
 438           { itype = M32RBF_INSN_CMPUI; goto extract_sfmt_cmpi; }
 439         itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 440       case 136: itype = M32RBF_INSN_ADDV3; goto extract_sfmt_addv3;
 441       case 138: itype = M32RBF_INSN_ADD3; goto extract_sfmt_add3;
 442       case 140: itype = M32RBF_INSN_AND3; goto extract_sfmt_and3;
 443       case 141: itype = M32RBF_INSN_XOR3; goto extract_sfmt_and3;
 444       case 142: itype = M32RBF_INSN_OR3; goto extract_sfmt_or3;
 445       case 144:
 446         if ((entire_insn & 0xf0f0ffff) == 0x90000000)
 447           { itype = M32RBF_INSN_DIV; goto extract_sfmt_div; }
 448         itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 449       case 145:
 450         if ((entire_insn & 0xf0f0ffff) == 0x90100000)
 451           { itype = M32RBF_INSN_DIVU; goto extract_sfmt_div; }
 452         itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 453       case 146:
 454         if ((entire_insn & 0xf0f0ffff) == 0x90200000)
 455           { itype = M32RBF_INSN_REM; goto extract_sfmt_div; }
 456         itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 457       case 147:
 458         if ((entire_insn & 0xf0f0ffff) == 0x90300000)
 459           { itype = M32RBF_INSN_REMU; goto extract_sfmt_div; }
 460         itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 461       case 152: itype = M32RBF_INSN_SRL3; goto extract_sfmt_sll3;
 462       case 154: itype = M32RBF_INSN_SRA3; goto extract_sfmt_sll3;
 463       case 156: itype = M32RBF_INSN_SLL3; goto extract_sfmt_sll3;
 464       case 159:
 465         if ((entire_insn & 0xf0ff0000) == 0x90f00000)
 466           { itype = M32RBF_INSN_LDI16; goto extract_sfmt_ldi16; }
 467         itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 468       case 160: itype = M32RBF_INSN_STB_D; goto extract_sfmt_stb_d;
 469       case 162: itype = M32RBF_INSN_STH_D; goto extract_sfmt_sth_d;
 470       case 164: itype = M32RBF_INSN_ST_D; goto extract_sfmt_st_d;
 471       case 166:
 472         if ((entire_insn & 0xf8f00000) == 0xa0600000)
 473           { itype = M32RBF_INSN_BSET; goto extract_sfmt_bset; }
 474         itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 475       case 167:
 476         if ((entire_insn & 0xf8f00000) == 0xa0700000)
 477           { itype = M32RBF_INSN_BCLR; goto extract_sfmt_bset; }
 478         itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 479       case 168: itype = M32RBF_INSN_LDB_D; goto extract_sfmt_ldb_d;
 480       case 169: itype = M32RBF_INSN_LDUB_D; goto extract_sfmt_ldb_d;
 481       case 170: itype = M32RBF_INSN_LDH_D; goto extract_sfmt_ldh_d;
 482       case 171: itype = M32RBF_INSN_LDUH_D; goto extract_sfmt_ldh_d;
 483       case 172: itype = M32RBF_INSN_LD_D; goto extract_sfmt_ld_d;
 484       case 176: itype = M32RBF_INSN_BEQ; goto extract_sfmt_beq;
 485       case 177: itype = M32RBF_INSN_BNE; goto extract_sfmt_beq;
 486       case 184:
 487         if ((entire_insn & 0xfff00000) == 0xb0800000)
 488           { itype = M32RBF_INSN_BEQZ; goto extract_sfmt_beqz; }
 489         itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 490       case 185:
 491         if ((entire_insn & 0xfff00000) == 0xb0900000)
 492           { itype = M32RBF_INSN_BNEZ; goto extract_sfmt_beqz; }
 493         itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 494       case 186:
 495         if ((entire_insn & 0xfff00000) == 0xb0a00000)
 496           { itype = M32RBF_INSN_BLTZ; goto extract_sfmt_beqz; }
 497         itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 498       case 187:
 499         if ((entire_insn & 0xfff00000) == 0xb0b00000)
 500           { itype = M32RBF_INSN_BGEZ; goto extract_sfmt_beqz; }
 501         itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 502       case 188:
 503         if ((entire_insn & 0xfff00000) == 0xb0c00000)
 504           { itype = M32RBF_INSN_BLEZ; goto extract_sfmt_beqz; }
 505         itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 506       case 189:
 507         if ((entire_insn & 0xfff00000) == 0xb0d00000)
 508           { itype = M32RBF_INSN_BGTZ; goto extract_sfmt_beqz; }
 509         itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 510       case 220:
 511         if ((entire_insn & 0xf0ff0000) == 0xd0c00000)
 512           { itype = M32RBF_INSN_SETH; goto extract_sfmt_seth; }
 513         itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 514       case 224:
 515       case 225:
 516       case 226:
 517       case 227:
 518       case 228:
 519       case 229:
 520       case 230:
 521       case 231:
 522       case 232:
 523       case 233:
 524       case 234:
 525       case 235:
 526       case 236:
 527       case 237:
 528       case 238:
 529       case 239: itype = M32RBF_INSN_LD24; goto extract_sfmt_ld24;
 530       case 240:
 531       case 241:
 532       case 242:
 533       case 243:
 534       case 244:
 535       case 245:
 536       case 246:
 537       case 247:
 538       case 248:
 539       case 249:
 540       case 250:
 541       case 251:
 542       case 252:
 543       case 253:
 544       case 254:
 545       case 255:
 546         {
 547           unsigned int val1 = (((insn >> 8) & (3 << 0)));
 548           switch (val1)
 549           {
 550           case 0:
 551             if ((entire_insn & 0xff000000) == 0xfc000000)
 552               { itype = M32RBF_INSN_BC24; goto extract_sfmt_bc24; }
 553             itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 554           case 1:
 555             if ((entire_insn & 0xff000000) == 0xfd000000)
 556               { itype = M32RBF_INSN_BNC24; goto extract_sfmt_bc24; }
 557             itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 558           case 2:
 559             if ((entire_insn & 0xff000000) == 0xfe000000)
 560               { itype = M32RBF_INSN_BL24; goto extract_sfmt_bl24; }
 561             itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 562           case 3:
 563             if ((entire_insn & 0xff000000) == 0xff000000)
 564               { itype = M32RBF_INSN_BRA24; goto extract_sfmt_bra24; }
 565             itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 566           default: itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 567           }
 568         }
 569       default: itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
 570       }
 571     }
 572   }
 573
 574   /* The instruction has been decoded, now extract the fields.  */
 575
 576  extract_sfmt_empty:
 577   {
 578     const IDESC *idesc = &m32rbf_insn_data[itype];
 579 #define FLD(f) abuf->fields.sfmt_empty.f
 580
 581
 582   /* Record the fields for the semantic handler.  */
 583   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_empty", (char *) 0));
 584
 585 #undef FLD
 586     return idesc;
 587   }
 588
 589  extract_sfmt_add:
 590   {
 591     const IDESC *idesc = &m32rbf_insn_data[itype];
 592     CGEN_INSN_WORD insn = entire_insn;
 593 #define FLD(f) abuf->fields.sfmt_add.f
 594     UINT f_r1;
 595     UINT f_r2;
 596
 597     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
 598     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
 599
 600   /* Record the fields for the semantic handler.  */
 601   FLD (f_r1) = f_r1;
 602   FLD (f_r2) = f_r2;
 603   FLD (i_dr) = & CPU (h_gr)[f_r1];
 604   FLD (i_sr) = & CPU (h_gr)[f_r2];
 605   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
 606
 607 #if WITH_PROFILE_MODEL_P
 608   /* Record the fields for profiling.  */
 609   if (PROFILE_MODEL_P (current_cpu))
 610     {
 611       FLD (in_dr) = f_r1;
 612       FLD (in_sr) = f_r2;
 613       FLD (out_dr) = f_r1;
 614     }
 615 #endif
 616 #undef FLD
 617     return idesc;
 618   }
 619
 620  extract_sfmt_add3:
 621   {
 622     const IDESC *idesc = &m32rbf_insn_data[itype];
 623     CGEN_INSN_WORD insn = entire_insn;
 624 #define FLD(f) abuf->fields.sfmt_add3.f
 625     UINT f_r1;
 626     UINT f_r2;
 627     INT f_simm16;
 628
 629     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
 630     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
 631     f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
 632
 633   /* Record the fields for the semantic handler.  */
 634   FLD (f_simm16) = f_simm16;
 635   FLD (f_r2) = f_r2;
 636   FLD (f_r1) = f_r1;
 637   FLD (i_sr) = & CPU (h_gr)[f_r2];
 638   FLD (i_dr) = & CPU (h_gr)[f_r1];
 639   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_add3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 640
 641 #if WITH_PROFILE_MODEL_P
 642   /* Record the fields for profiling.  */
 643   if (PROFILE_MODEL_P (current_cpu))
 644     {
 645       FLD (in_sr) = f_r2;
 646       FLD (out_dr) = f_r1;
 647     }
 648 #endif
 649 #undef FLD
 650     return idesc;
 651   }
 652
 653  extract_sfmt_and3:
 654   {
 655     const IDESC *idesc = &m32rbf_insn_data[itype];
 656     CGEN_INSN_WORD insn = entire_insn;
 657 #define FLD(f) abuf->fields.sfmt_and3.f
 658     UINT f_r1;
 659     UINT f_r2;
 660     UINT f_uimm16;
 661
 662     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
 663     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
 664     f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
 665
 666   /* Record the fields for the semantic handler.  */
 667   FLD (f_r2) = f_r2;
 668   FLD (f_uimm16) = f_uimm16;
 669   FLD (f_r1) = f_r1;
 670   FLD (i_sr) = & CPU (h_gr)[f_r2];
 671   FLD (i_dr) = & CPU (h_gr)[f_r1];
 672   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_and3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 673
 674 #if WITH_PROFILE_MODEL_P
 675   /* Record the fields for profiling.  */
 676   if (PROFILE_MODEL_P (current_cpu))
 677     {
 678       FLD (in_sr) = f_r2;
 679       FLD (out_dr) = f_r1;
 680     }
 681 #endif
 682 #undef FLD
 683     return idesc;
 684   }
 685
 686  extract_sfmt_or3:
 687   {
 688     const IDESC *idesc = &m32rbf_insn_data[itype];
 689     CGEN_INSN_WORD insn = entire_insn;
 690 #define FLD(f) abuf->fields.sfmt_and3.f
 691     UINT f_r1;
 692     UINT f_r2;
 693     UINT f_uimm16;
 694
 695     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
 696     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
 697     f_uimm16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
 698
 699   /* Record the fields for the semantic handler.  */
 700   FLD (f_r2) = f_r2;
 701   FLD (f_uimm16) = f_uimm16;
 702   FLD (f_r1) = f_r1;
 703   FLD (i_sr) = & CPU (h_gr)[f_r2];
 704   FLD (i_dr) = & CPU (h_gr)[f_r1];
 705   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_or3", "f_r2 0x%x", 'x', f_r2, "f_uimm16 0x%x", 'x', f_uimm16, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 706
 707 #if WITH_PROFILE_MODEL_P
 708   /* Record the fields for profiling.  */
 709   if (PROFILE_MODEL_P (current_cpu))
 710     {
 711       FLD (in_sr) = f_r2;
 712       FLD (out_dr) = f_r1;
 713     }
 714 #endif
 715 #undef FLD
 716     return idesc;
 717   }
 718
 719  extract_sfmt_addi:
 720   {
 721     const IDESC *idesc = &m32rbf_insn_data[itype];
 722     CGEN_INSN_WORD insn = entire_insn;
 723 #define FLD(f) abuf->fields.sfmt_addi.f
 724     UINT f_r1;
 725     INT f_simm8;
 726
 727     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
 728     f_simm8 = EXTRACT_MSB0_SINT (insn, 16, 8, 8);
 729
 730   /* Record the fields for the semantic handler.  */
 731   FLD (f_r1) = f_r1;
 732   FLD (f_simm8) = f_simm8;
 733   FLD (i_dr) = & CPU (h_gr)[f_r1];
 734   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addi", "f_r1 0x%x", 'x', f_r1, "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0));
 735
 736 #if WITH_PROFILE_MODEL_P
 737   /* Record the fields for profiling.  */
 738   if (PROFILE_MODEL_P (current_cpu))
 739     {
 740       FLD (in_dr) = f_r1;
 741       FLD (out_dr) = f_r1;
 742     }
 743 #endif
 744 #undef FLD
 745     return idesc;
 746   }
 747
 748  extract_sfmt_addv:
 749   {
 750     const IDESC *idesc = &m32rbf_insn_data[itype];
 751     CGEN_INSN_WORD insn = entire_insn;
 752 #define FLD(f) abuf->fields.sfmt_add.f
 753     UINT f_r1;
 754     UINT f_r2;
 755
 756     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
 757     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
 758
 759   /* Record the fields for the semantic handler.  */
 760   FLD (f_r1) = f_r1;
 761   FLD (f_r2) = f_r2;
 762   FLD (i_dr) = & CPU (h_gr)[f_r1];
 763   FLD (i_sr) = & CPU (h_gr)[f_r2];
 764   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
 765
 766 #if WITH_PROFILE_MODEL_P
 767   /* Record the fields for profiling.  */
 768   if (PROFILE_MODEL_P (current_cpu))
 769     {
 770       FLD (in_dr) = f_r1;
 771       FLD (in_sr) = f_r2;
 772       FLD (out_dr) = f_r1;
 773     }
 774 #endif
 775 #undef FLD
 776     return idesc;
 777   }
 778
 779  extract_sfmt_addv3:
 780   {
 781     const IDESC *idesc = &m32rbf_insn_data[itype];
 782     CGEN_INSN_WORD insn = entire_insn;
 783 #define FLD(f) abuf->fields.sfmt_add3.f
 784     UINT f_r1;
 785     UINT f_r2;
 786     INT f_simm16;
 787
 788     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
 789     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
 790     f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
 791
 792   /* Record the fields for the semantic handler.  */
 793   FLD (f_simm16) = f_simm16;
 794   FLD (f_r2) = f_r2;
 795   FLD (f_r1) = f_r1;
 796   FLD (i_sr) = & CPU (h_gr)[f_r2];
 797   FLD (i_dr) = & CPU (h_gr)[f_r1];
 798   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addv3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
 799
 800 #if WITH_PROFILE_MODEL_P
 801   /* Record the fields for profiling.  */
 802   if (PROFILE_MODEL_P (current_cpu))
 803     {
 804       FLD (in_sr) = f_r2;
 805       FLD (out_dr) = f_r1;
 806     }
 807 #endif
 808 #undef FLD
 809     return idesc;
 810   }
 811
 812  extract_sfmt_addx:
 813   {
 814     const IDESC *idesc = &m32rbf_insn_data[itype];
 815     CGEN_INSN_WORD insn = entire_insn;
 816 #define FLD(f) abuf->fields.sfmt_add.f
 817     UINT f_r1;
 818     UINT f_r2;
 819
 820     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
 821     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
 822
 823   /* Record the fields for the semantic handler.  */
 824   FLD (f_r1) = f_r1;
 825   FLD (f_r2) = f_r2;
 826   FLD (i_dr) = & CPU (h_gr)[f_r1];
 827   FLD (i_sr) = & CPU (h_gr)[f_r2];
 828   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_addx", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
 829
 830 #if WITH_PROFILE_MODEL_P
 831   /* Record the fields for profiling.  */
 832   if (PROFILE_MODEL_P (current_cpu))
 833     {
 834       FLD (in_dr) = f_r1;
 835       FLD (in_sr) = f_r2;
 836       FLD (out_dr) = f_r1;
 837     }
 838 #endif
 839 #undef FLD
 840     return idesc;
 841   }
 842
 843  extract_sfmt_bc8:
 844   {
 845     const IDESC *idesc = &m32rbf_insn_data[itype];
 846     CGEN_INSN_WORD insn = entire_insn;
 847 #define FLD(f) abuf->fields.sfmt_bl8.f
 848     SI f_disp8;
 849
 850     f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4))));
 851
 852   /* Record the fields for the semantic handler.  */
 853   FLD (i_disp8) = f_disp8;
 854   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
 855
 856 #if WITH_PROFILE_MODEL_P
 857   /* Record the fields for profiling.  */
 858   if (PROFILE_MODEL_P (current_cpu))
 859     {
 860     }
 861 #endif
 862 #undef FLD
 863     return idesc;
 864   }
 865
 866  extract_sfmt_bc24:
 867   {
 868     const IDESC *idesc = &m32rbf_insn_data[itype];
 869     CGEN_INSN_WORD insn = entire_insn;
 870 #define FLD(f) abuf->fields.sfmt_bl24.f
 871     SI f_disp24;
 872
 873     f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc));
 874
 875   /* Record the fields for the semantic handler.  */
 876   FLD (i_disp24) = f_disp24;
 877   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
 878
 879 #if WITH_PROFILE_MODEL_P
 880   /* Record the fields for profiling.  */
 881   if (PROFILE_MODEL_P (current_cpu))
 882     {
 883     }
 884 #endif
 885 #undef FLD
 886     return idesc;
 887   }
 888
 889  extract_sfmt_beq:
 890   {
 891     const IDESC *idesc = &m32rbf_insn_data[itype];
 892     CGEN_INSN_WORD insn = entire_insn;
 893 #define FLD(f) abuf->fields.sfmt_beq.f
 894     UINT f_r1;
 895     UINT f_r2;
 896     SI f_disp16;
 897
 898     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
 899     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
 900     f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) * (4))) + (pc));
 901
 902   /* Record the fields for the semantic handler.  */
 903   FLD (f_r1) = f_r1;
 904   FLD (f_r2) = f_r2;
 905   FLD (i_disp16) = f_disp16;
 906   FLD (i_src1) = & CPU (h_gr)[f_r1];
 907   FLD (i_src2) = & CPU (h_gr)[f_r2];
 908   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beq", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
 909
 910 #if WITH_PROFILE_MODEL_P
 911   /* Record the fields for profiling.  */
 912   if (PROFILE_MODEL_P (current_cpu))
 913     {
 914       FLD (in_src1) = f_r1;
 915       FLD (in_src2) = f_r2;
 916     }
 917 #endif
 918 #undef FLD
 919     return idesc;
 920   }
 921
 922  extract_sfmt_beqz:
 923   {
 924     const IDESC *idesc = &m32rbf_insn_data[itype];
 925     CGEN_INSN_WORD insn = entire_insn;
 926 #define FLD(f) abuf->fields.sfmt_beq.f
 927     UINT f_r2;
 928     SI f_disp16;
 929
 930     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
 931     f_disp16 = ((((EXTRACT_MSB0_SINT (insn, 32, 16, 16)) * (4))) + (pc));
 932
 933   /* Record the fields for the semantic handler.  */
 934   FLD (f_r2) = f_r2;
 935   FLD (i_disp16) = f_disp16;
 936   FLD (i_src2) = & CPU (h_gr)[f_r2];
 937   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_beqz", "f_r2 0x%x", 'x', f_r2, "disp16 0x%x", 'x', f_disp16, "src2 0x%x", 'x', f_r2, (char *) 0));
 938
 939 #if WITH_PROFILE_MODEL_P
 940   /* Record the fields for profiling.  */
 941   if (PROFILE_MODEL_P (current_cpu))
 942     {
 943       FLD (in_src2) = f_r2;
 944     }
 945 #endif
 946 #undef FLD
 947     return idesc;
 948   }
 949
 950  extract_sfmt_bl8:
 951   {
 952     const IDESC *idesc = &m32rbf_insn_data[itype];
 953     CGEN_INSN_WORD insn = entire_insn;
 954 #define FLD(f) abuf->fields.sfmt_bl8.f
 955     SI f_disp8;
 956
 957     f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4))));
 958
 959   /* Record the fields for the semantic handler.  */
 960   FLD (i_disp8) = f_disp8;
 961   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
 962
 963 #if WITH_PROFILE_MODEL_P
 964   /* Record the fields for profiling.  */
 965   if (PROFILE_MODEL_P (current_cpu))
 966     {
 967       FLD (out_h_gr_SI_14) = 14;
 968     }
 969 #endif
 970 #undef FLD
 971     return idesc;
 972   }
 973
 974  extract_sfmt_bl24:
 975   {
 976     const IDESC *idesc = &m32rbf_insn_data[itype];
 977     CGEN_INSN_WORD insn = entire_insn;
 978 #define FLD(f) abuf->fields.sfmt_bl24.f
 979     SI f_disp24;
 980
 981     f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc));
 982
 983   /* Record the fields for the semantic handler.  */
 984   FLD (i_disp24) = f_disp24;
 985   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
 986
 987 #if WITH_PROFILE_MODEL_P
 988   /* Record the fields for profiling.  */
 989   if (PROFILE_MODEL_P (current_cpu))
 990     {
 991       FLD (out_h_gr_SI_14) = 14;
 992     }
 993 #endif
 994 #undef FLD
 995     return idesc;
 996   }
 997
 998  extract_sfmt_bra8:
 999   {
1000     const IDESC *idesc = &m32rbf_insn_data[itype];
1001     CGEN_INSN_WORD insn = entire_insn;
1002 #define FLD(f) abuf->fields.sfmt_bl8.f
1003     SI f_disp8;
1004
1005     f_disp8 = ((((EXTRACT_MSB0_SINT (insn, 16, 8, 8)) * (4))) + (((pc) & (-4))));
1006
1007   /* Record the fields for the semantic handler.  */
1008   FLD (i_disp8) = f_disp8;
1009   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
1010
1011 #if WITH_PROFILE_MODEL_P
1012   /* Record the fields for profiling.  */
1013   if (PROFILE_MODEL_P (current_cpu))
1014     {
1015     }
1016 #endif
1017 #undef FLD
1018     return idesc;
1019   }
1020
1021  extract_sfmt_bra24:
1022   {
1023     const IDESC *idesc = &m32rbf_insn_data[itype];
1024     CGEN_INSN_WORD insn = entire_insn;
1025 #define FLD(f) abuf->fields.sfmt_bl24.f
1026     SI f_disp24;
1027
1028     f_disp24 = ((((EXTRACT_MSB0_SINT (insn, 32, 8, 24)) * (4))) + (pc));
1029
1030   /* Record the fields for the semantic handler.  */
1031   FLD (i_disp24) = f_disp24;
1032   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
1033
1034 #if WITH_PROFILE_MODEL_P
1035   /* Record the fields for profiling.  */
1036   if (PROFILE_MODEL_P (current_cpu))
1037     {
1038     }
1039 #endif
1040 #undef FLD
1041     return idesc;
1042   }
1043
1044  extract_sfmt_cmp:
1045   {
1046     const IDESC *idesc = &m32rbf_insn_data[itype];
1047     CGEN_INSN_WORD insn = entire_insn;
1048 #define FLD(f) abuf->fields.sfmt_st_plus.f
1049     UINT f_r1;
1050     UINT f_r2;
1051
1052     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1053     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1054
1055   /* Record the fields for the semantic handler.  */
1056   FLD (f_r1) = f_r1;
1057   FLD (f_r2) = f_r2;
1058   FLD (i_src1) = & CPU (h_gr)[f_r1];
1059   FLD (i_src2) = & CPU (h_gr)[f_r2];
1060   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmp", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1061
1062 #if WITH_PROFILE_MODEL_P
1063   /* Record the fields for profiling.  */
1064   if (PROFILE_MODEL_P (current_cpu))
1065     {
1066       FLD (in_src1) = f_r1;
1067       FLD (in_src2) = f_r2;
1068     }
1069 #endif
1070 #undef FLD
1071     return idesc;
1072   }
1073
1074  extract_sfmt_cmpi:
1075   {
1076     const IDESC *idesc = &m32rbf_insn_data[itype];
1077     CGEN_INSN_WORD insn = entire_insn;
1078 #define FLD(f) abuf->fields.sfmt_st_d.f
1079     UINT f_r2;
1080     INT f_simm16;
1081
1082     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1083     f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
1084
1085   /* Record the fields for the semantic handler.  */
1086   FLD (f_simm16) = f_simm16;
1087   FLD (f_r2) = f_r2;
1088   FLD (i_src2) = & CPU (h_gr)[f_r2];
1089   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_cmpi", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "src2 0x%x", 'x', f_r2, (char *) 0));
1090
1091 #if WITH_PROFILE_MODEL_P
1092   /* Record the fields for profiling.  */
1093   if (PROFILE_MODEL_P (current_cpu))
1094     {
1095       FLD (in_src2) = f_r2;
1096     }
1097 #endif
1098 #undef FLD
1099     return idesc;
1100   }
1101
1102  extract_sfmt_div:
1103   {
1104     const IDESC *idesc = &m32rbf_insn_data[itype];
1105     CGEN_INSN_WORD insn = entire_insn;
1106 #define FLD(f) abuf->fields.sfmt_add.f
1107     UINT f_r1;
1108     UINT f_r2;
1109
1110     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1111     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1112
1113   /* Record the fields for the semantic handler.  */
1114   FLD (f_r1) = f_r1;
1115   FLD (f_r2) = f_r2;
1116   FLD (i_dr) = & CPU (h_gr)[f_r1];
1117   FLD (i_sr) = & CPU (h_gr)[f_r2];
1118   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_div", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
1119
1120 #if WITH_PROFILE_MODEL_P
1121   /* Record the fields for profiling.  */
1122   if (PROFILE_MODEL_P (current_cpu))
1123     {
1124       FLD (in_dr) = f_r1;
1125       FLD (in_sr) = f_r2;
1126       FLD (out_dr) = f_r1;
1127     }
1128 #endif
1129 #undef FLD
1130     return idesc;
1131   }
1132
1133  extract_sfmt_jl:
1134   {
1135     const IDESC *idesc = &m32rbf_insn_data[itype];
1136     CGEN_INSN_WORD insn = entire_insn;
1137 #define FLD(f) abuf->fields.sfmt_jl.f
1138     UINT f_r2;
1139
1140     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1141
1142   /* Record the fields for the semantic handler.  */
1143   FLD (f_r2) = f_r2;
1144   FLD (i_sr) = & CPU (h_gr)[f_r2];
1145   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jl", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));
1146
1147 #if WITH_PROFILE_MODEL_P
1148   /* Record the fields for profiling.  */
1149   if (PROFILE_MODEL_P (current_cpu))
1150     {
1151       FLD (in_sr) = f_r2;
1152       FLD (out_h_gr_SI_14) = 14;
1153     }
1154 #endif
1155 #undef FLD
1156     return idesc;
1157   }
1158
1159  extract_sfmt_jmp:
1160   {
1161     const IDESC *idesc = &m32rbf_insn_data[itype];
1162     CGEN_INSN_WORD insn = entire_insn;
1163 #define FLD(f) abuf->fields.sfmt_jl.f
1164     UINT f_r2;
1165
1166     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1167
1168   /* Record the fields for the semantic handler.  */
1169   FLD (f_r2) = f_r2;
1170   FLD (i_sr) = & CPU (h_gr)[f_r2];
1171   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_jmp", "f_r2 0x%x", 'x', f_r2, "sr 0x%x", 'x', f_r2, (char *) 0));
1172
1173 #if WITH_PROFILE_MODEL_P
1174   /* Record the fields for profiling.  */
1175   if (PROFILE_MODEL_P (current_cpu))
1176     {
1177       FLD (in_sr) = f_r2;
1178     }
1179 #endif
1180 #undef FLD
1181     return idesc;
1182   }
1183
1184  extract_sfmt_ld:
1185   {
1186     const IDESC *idesc = &m32rbf_insn_data[itype];
1187     CGEN_INSN_WORD insn = entire_insn;
1188 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1189     UINT f_r1;
1190     UINT f_r2;
1191
1192     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1193     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1194
1195   /* Record the fields for the semantic handler.  */
1196   FLD (f_r2) = f_r2;
1197   FLD (f_r1) = f_r1;
1198   FLD (i_sr) = & CPU (h_gr)[f_r2];
1199   FLD (i_dr) = & CPU (h_gr)[f_r1];
1200   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1201
1202 #if WITH_PROFILE_MODEL_P
1203   /* Record the fields for profiling.  */
1204   if (PROFILE_MODEL_P (current_cpu))
1205     {
1206       FLD (in_sr) = f_r2;
1207       FLD (out_dr) = f_r1;
1208     }
1209 #endif
1210 #undef FLD
1211     return idesc;
1212   }
1213
1214  extract_sfmt_ld_d:
1215   {
1216     const IDESC *idesc = &m32rbf_insn_data[itype];
1217     CGEN_INSN_WORD insn = entire_insn;
1218 #define FLD(f) abuf->fields.sfmt_add3.f
1219     UINT f_r1;
1220     UINT f_r2;
1221     INT f_simm16;
1222
1223     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1224     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1225     f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
1226
1227   /* Record the fields for the semantic handler.  */
1228   FLD (f_simm16) = f_simm16;
1229   FLD (f_r2) = f_r2;
1230   FLD (f_r1) = f_r1;
1231   FLD (i_sr) = & CPU (h_gr)[f_r2];
1232   FLD (i_dr) = & CPU (h_gr)[f_r1];
1233   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1234
1235 #if WITH_PROFILE_MODEL_P
1236   /* Record the fields for profiling.  */
1237   if (PROFILE_MODEL_P (current_cpu))
1238     {
1239       FLD (in_sr) = f_r2;
1240       FLD (out_dr) = f_r1;
1241     }
1242 #endif
1243 #undef FLD
1244     return idesc;
1245   }
1246
1247  extract_sfmt_ldb:
1248   {
1249     const IDESC *idesc = &m32rbf_insn_data[itype];
1250     CGEN_INSN_WORD insn = entire_insn;
1251 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1252     UINT f_r1;
1253     UINT f_r2;
1254
1255     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1256     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1257
1258   /* Record the fields for the semantic handler.  */
1259   FLD (f_r2) = f_r2;
1260   FLD (f_r1) = f_r1;
1261   FLD (i_sr) = & CPU (h_gr)[f_r2];
1262   FLD (i_dr) = & CPU (h_gr)[f_r1];
1263   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1264
1265 #if WITH_PROFILE_MODEL_P
1266   /* Record the fields for profiling.  */
1267   if (PROFILE_MODEL_P (current_cpu))
1268     {
1269       FLD (in_sr) = f_r2;
1270       FLD (out_dr) = f_r1;
1271     }
1272 #endif
1273 #undef FLD
1274     return idesc;
1275   }
1276
1277  extract_sfmt_ldb_d:
1278   {
1279     const IDESC *idesc = &m32rbf_insn_data[itype];
1280     CGEN_INSN_WORD insn = entire_insn;
1281 #define FLD(f) abuf->fields.sfmt_add3.f
1282     UINT f_r1;
1283     UINT f_r2;
1284     INT f_simm16;
1285
1286     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1287     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1288     f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
1289
1290   /* Record the fields for the semantic handler.  */
1291   FLD (f_simm16) = f_simm16;
1292   FLD (f_r2) = f_r2;
1293   FLD (f_r1) = f_r1;
1294   FLD (i_sr) = & CPU (h_gr)[f_r2];
1295   FLD (i_dr) = & CPU (h_gr)[f_r1];
1296   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1297
1298 #if WITH_PROFILE_MODEL_P
1299   /* Record the fields for profiling.  */
1300   if (PROFILE_MODEL_P (current_cpu))
1301     {
1302       FLD (in_sr) = f_r2;
1303       FLD (out_dr) = f_r1;
1304     }
1305 #endif
1306 #undef FLD
1307     return idesc;
1308   }
1309
1310  extract_sfmt_ldh:
1311   {
1312     const IDESC *idesc = &m32rbf_insn_data[itype];
1313     CGEN_INSN_WORD insn = entire_insn;
1314 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1315     UINT f_r1;
1316     UINT f_r2;
1317
1318     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1319     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1320
1321   /* Record the fields for the semantic handler.  */
1322   FLD (f_r2) = f_r2;
1323   FLD (f_r1) = f_r1;
1324   FLD (i_sr) = & CPU (h_gr)[f_r2];
1325   FLD (i_dr) = & CPU (h_gr)[f_r1];
1326   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1327
1328 #if WITH_PROFILE_MODEL_P
1329   /* Record the fields for profiling.  */
1330   if (PROFILE_MODEL_P (current_cpu))
1331     {
1332       FLD (in_sr) = f_r2;
1333       FLD (out_dr) = f_r1;
1334     }
1335 #endif
1336 #undef FLD
1337     return idesc;
1338   }
1339
1340  extract_sfmt_ldh_d:
1341   {
1342     const IDESC *idesc = &m32rbf_insn_data[itype];
1343     CGEN_INSN_WORD insn = entire_insn;
1344 #define FLD(f) abuf->fields.sfmt_add3.f
1345     UINT f_r1;
1346     UINT f_r2;
1347     INT f_simm16;
1348
1349     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1350     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1351     f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
1352
1353   /* Record the fields for the semantic handler.  */
1354   FLD (f_simm16) = f_simm16;
1355   FLD (f_r2) = f_r2;
1356   FLD (f_r1) = f_r1;
1357   FLD (i_sr) = & CPU (h_gr)[f_r2];
1358   FLD (i_dr) = & CPU (h_gr)[f_r1];
1359   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldh_d", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1360
1361 #if WITH_PROFILE_MODEL_P
1362   /* Record the fields for profiling.  */
1363   if (PROFILE_MODEL_P (current_cpu))
1364     {
1365       FLD (in_sr) = f_r2;
1366       FLD (out_dr) = f_r1;
1367     }
1368 #endif
1369 #undef FLD
1370     return idesc;
1371   }
1372
1373  extract_sfmt_ld_plus:
1374   {
1375     const IDESC *idesc = &m32rbf_insn_data[itype];
1376     CGEN_INSN_WORD insn = entire_insn;
1377 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1378     UINT f_r1;
1379     UINT f_r2;
1380
1381     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1382     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1383
1384   /* Record the fields for the semantic handler.  */
1385   FLD (f_r2) = f_r2;
1386   FLD (f_r1) = f_r1;
1387   FLD (i_sr) = & CPU (h_gr)[f_r2];
1388   FLD (i_dr) = & CPU (h_gr)[f_r1];
1389   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld_plus", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1390
1391 #if WITH_PROFILE_MODEL_P
1392   /* Record the fields for profiling.  */
1393   if (PROFILE_MODEL_P (current_cpu))
1394     {
1395       FLD (in_sr) = f_r2;
1396       FLD (out_dr) = f_r1;
1397       FLD (out_sr) = f_r2;
1398     }
1399 #endif
1400 #undef FLD
1401     return idesc;
1402   }
1403
1404  extract_sfmt_ld24:
1405   {
1406     const IDESC *idesc = &m32rbf_insn_data[itype];
1407     CGEN_INSN_WORD insn = entire_insn;
1408 #define FLD(f) abuf->fields.sfmt_ld24.f
1409     UINT f_r1;
1410     UINT f_uimm24;
1411
1412     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1413     f_uimm24 = EXTRACT_MSB0_UINT (insn, 32, 8, 24);
1414
1415   /* Record the fields for the semantic handler.  */
1416   FLD (f_r1) = f_r1;
1417   FLD (i_uimm24) = f_uimm24;
1418   FLD (i_dr) = & CPU (h_gr)[f_r1];
1419   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ld24", "f_r1 0x%x", 'x', f_r1, "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0));
1420
1421 #if WITH_PROFILE_MODEL_P
1422   /* Record the fields for profiling.  */
1423   if (PROFILE_MODEL_P (current_cpu))
1424     {
1425       FLD (out_dr) = f_r1;
1426     }
1427 #endif
1428 #undef FLD
1429     return idesc;
1430   }
1431
1432  extract_sfmt_ldi8:
1433   {
1434     const IDESC *idesc = &m32rbf_insn_data[itype];
1435     CGEN_INSN_WORD insn = entire_insn;
1436 #define FLD(f) abuf->fields.sfmt_addi.f
1437     UINT f_r1;
1438     INT f_simm8;
1439
1440     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1441     f_simm8 = EXTRACT_MSB0_SINT (insn, 16, 8, 8);
1442
1443   /* Record the fields for the semantic handler.  */
1444   FLD (f_simm8) = f_simm8;
1445   FLD (f_r1) = f_r1;
1446   FLD (i_dr) = & CPU (h_gr)[f_r1];
1447   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi8", "f_simm8 0x%x", 'x', f_simm8, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
1448
1449 #if WITH_PROFILE_MODEL_P
1450   /* Record the fields for profiling.  */
1451   if (PROFILE_MODEL_P (current_cpu))
1452     {
1453       FLD (out_dr) = f_r1;
1454     }
1455 #endif
1456 #undef FLD
1457     return idesc;
1458   }
1459
1460  extract_sfmt_ldi16:
1461   {
1462     const IDESC *idesc = &m32rbf_insn_data[itype];
1463     CGEN_INSN_WORD insn = entire_insn;
1464 #define FLD(f) abuf->fields.sfmt_add3.f
1465     UINT f_r1;
1466     INT f_simm16;
1467
1468     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1469     f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
1470
1471   /* Record the fields for the semantic handler.  */
1472   FLD (f_simm16) = f_simm16;
1473   FLD (f_r1) = f_r1;
1474   FLD (i_dr) = & CPU (h_gr)[f_r1];
1475   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_ldi16", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
1476
1477 #if WITH_PROFILE_MODEL_P
1478   /* Record the fields for profiling.  */
1479   if (PROFILE_MODEL_P (current_cpu))
1480     {
1481       FLD (out_dr) = f_r1;
1482     }
1483 #endif
1484 #undef FLD
1485     return idesc;
1486   }
1487
1488  extract_sfmt_lock:
1489   {
1490     const IDESC *idesc = &m32rbf_insn_data[itype];
1491     CGEN_INSN_WORD insn = entire_insn;
1492 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1493     UINT f_r1;
1494     UINT f_r2;
1495
1496     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1497     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1498
1499   /* Record the fields for the semantic handler.  */
1500   FLD (f_r2) = f_r2;
1501   FLD (f_r1) = f_r1;
1502   FLD (i_sr) = & CPU (h_gr)[f_r2];
1503   FLD (i_dr) = & CPU (h_gr)[f_r1];
1504   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_lock", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1505
1506 #if WITH_PROFILE_MODEL_P
1507   /* Record the fields for profiling.  */
1508   if (PROFILE_MODEL_P (current_cpu))
1509     {
1510       FLD (in_sr) = f_r2;
1511       FLD (out_dr) = f_r1;
1512     }
1513 #endif
1514 #undef FLD
1515     return idesc;
1516   }
1517
1518  extract_sfmt_machi:
1519   {
1520     const IDESC *idesc = &m32rbf_insn_data[itype];
1521     CGEN_INSN_WORD insn = entire_insn;
1522 #define FLD(f) abuf->fields.sfmt_st_plus.f
1523     UINT f_r1;
1524     UINT f_r2;
1525
1526     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1527     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1528
1529   /* Record the fields for the semantic handler.  */
1530   FLD (f_r1) = f_r1;
1531   FLD (f_r2) = f_r2;
1532   FLD (i_src1) = & CPU (h_gr)[f_r1];
1533   FLD (i_src2) = & CPU (h_gr)[f_r2];
1534   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_machi", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1535
1536 #if WITH_PROFILE_MODEL_P
1537   /* Record the fields for profiling.  */
1538   if (PROFILE_MODEL_P (current_cpu))
1539     {
1540       FLD (in_src1) = f_r1;
1541       FLD (in_src2) = f_r2;
1542     }
1543 #endif
1544 #undef FLD
1545     return idesc;
1546   }
1547
1548  extract_sfmt_mulhi:
1549   {
1550     const IDESC *idesc = &m32rbf_insn_data[itype];
1551     CGEN_INSN_WORD insn = entire_insn;
1552 #define FLD(f) abuf->fields.sfmt_st_plus.f
1553     UINT f_r1;
1554     UINT f_r2;
1555
1556     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1557     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1558
1559   /* Record the fields for the semantic handler.  */
1560   FLD (f_r1) = f_r1;
1561   FLD (f_r2) = f_r2;
1562   FLD (i_src1) = & CPU (h_gr)[f_r1];
1563   FLD (i_src2) = & CPU (h_gr)[f_r2];
1564   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mulhi", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1565
1566 #if WITH_PROFILE_MODEL_P
1567   /* Record the fields for profiling.  */
1568   if (PROFILE_MODEL_P (current_cpu))
1569     {
1570       FLD (in_src1) = f_r1;
1571       FLD (in_src2) = f_r2;
1572     }
1573 #endif
1574 #undef FLD
1575     return idesc;
1576   }
1577
1578  extract_sfmt_mv:
1579   {
1580     const IDESC *idesc = &m32rbf_insn_data[itype];
1581     CGEN_INSN_WORD insn = entire_insn;
1582 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1583     UINT f_r1;
1584     UINT f_r2;
1585
1586     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1587     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1588
1589   /* Record the fields for the semantic handler.  */
1590   FLD (f_r2) = f_r2;
1591   FLD (f_r1) = f_r1;
1592   FLD (i_sr) = & CPU (h_gr)[f_r2];
1593   FLD (i_dr) = & CPU (h_gr)[f_r1];
1594   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mv", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1595
1596 #if WITH_PROFILE_MODEL_P
1597   /* Record the fields for profiling.  */
1598   if (PROFILE_MODEL_P (current_cpu))
1599     {
1600       FLD (in_sr) = f_r2;
1601       FLD (out_dr) = f_r1;
1602     }
1603 #endif
1604 #undef FLD
1605     return idesc;
1606   }
1607
1608  extract_sfmt_mvfachi:
1609   {
1610     const IDESC *idesc = &m32rbf_insn_data[itype];
1611     CGEN_INSN_WORD insn = entire_insn;
1612 #define FLD(f) abuf->fields.sfmt_seth.f
1613     UINT f_r1;
1614
1615     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1616
1617   /* Record the fields for the semantic handler.  */
1618   FLD (f_r1) = f_r1;
1619   FLD (i_dr) = & CPU (h_gr)[f_r1];
1620   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfachi", "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
1621
1622 #if WITH_PROFILE_MODEL_P
1623   /* Record the fields for profiling.  */
1624   if (PROFILE_MODEL_P (current_cpu))
1625     {
1626       FLD (out_dr) = f_r1;
1627     }
1628 #endif
1629 #undef FLD
1630     return idesc;
1631   }
1632
1633  extract_sfmt_mvfc:
1634   {
1635     const IDESC *idesc = &m32rbf_insn_data[itype];
1636     CGEN_INSN_WORD insn = entire_insn;
1637 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1638     UINT f_r1;
1639     UINT f_r2;
1640
1641     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1642     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1643
1644   /* Record the fields for the semantic handler.  */
1645   FLD (f_r2) = f_r2;
1646   FLD (f_r1) = f_r1;
1647   FLD (i_dr) = & CPU (h_gr)[f_r1];
1648   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvfc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
1649
1650 #if WITH_PROFILE_MODEL_P
1651   /* Record the fields for profiling.  */
1652   if (PROFILE_MODEL_P (current_cpu))
1653     {
1654       FLD (out_dr) = f_r1;
1655     }
1656 #endif
1657 #undef FLD
1658     return idesc;
1659   }
1660
1661  extract_sfmt_mvtachi:
1662   {
1663     const IDESC *idesc = &m32rbf_insn_data[itype];
1664     CGEN_INSN_WORD insn = entire_insn;
1665 #define FLD(f) abuf->fields.sfmt_st_plus.f
1666     UINT f_r1;
1667
1668     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1669
1670   /* Record the fields for the semantic handler.  */
1671   FLD (f_r1) = f_r1;
1672   FLD (i_src1) = & CPU (h_gr)[f_r1];
1673   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtachi", "f_r1 0x%x", 'x', f_r1, "src1 0x%x", 'x', f_r1, (char *) 0));
1674
1675 #if WITH_PROFILE_MODEL_P
1676   /* Record the fields for profiling.  */
1677   if (PROFILE_MODEL_P (current_cpu))
1678     {
1679       FLD (in_src1) = f_r1;
1680     }
1681 #endif
1682 #undef FLD
1683     return idesc;
1684   }
1685
1686  extract_sfmt_mvtc:
1687   {
1688     const IDESC *idesc = &m32rbf_insn_data[itype];
1689     CGEN_INSN_WORD insn = entire_insn;
1690 #define FLD(f) abuf->fields.sfmt_ld_plus.f
1691     UINT f_r1;
1692     UINT f_r2;
1693
1694     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1695     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1696
1697   /* Record the fields for the semantic handler.  */
1698   FLD (f_r2) = f_r2;
1699   FLD (f_r1) = f_r1;
1700   FLD (i_sr) = & CPU (h_gr)[f_r2];
1701   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_mvtc", "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
1702
1703 #if WITH_PROFILE_MODEL_P
1704   /* Record the fields for profiling.  */
1705   if (PROFILE_MODEL_P (current_cpu))
1706     {
1707       FLD (in_sr) = f_r2;
1708     }
1709 #endif
1710 #undef FLD
1711     return idesc;
1712   }
1713
1714  extract_sfmt_nop:
1715   {
1716     const IDESC *idesc = &m32rbf_insn_data[itype];
1717 #define FLD(f) abuf->fields.sfmt_empty.f
1718
1719
1720   /* Record the fields for the semantic handler.  */
1721   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_nop", (char *) 0));
1722
1723 #undef FLD
1724     return idesc;
1725   }
1726
1727  extract_sfmt_rac:
1728   {
1729     const IDESC *idesc = &m32rbf_insn_data[itype];
1730 #define FLD(f) abuf->fields.sfmt_empty.f
1731
1732
1733   /* Record the fields for the semantic handler.  */
1734   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rac", (char *) 0));
1735
1736 #undef FLD
1737     return idesc;
1738   }
1739
1740  extract_sfmt_rte:
1741   {
1742     const IDESC *idesc = &m32rbf_insn_data[itype];
1743 #define FLD(f) abuf->fields.sfmt_empty.f
1744
1745
1746   /* Record the fields for the semantic handler.  */
1747   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_rte", (char *) 0));
1748
1749 #if WITH_PROFILE_MODEL_P
1750   /* Record the fields for profiling.  */
1751   if (PROFILE_MODEL_P (current_cpu))
1752     {
1753     }
1754 #endif
1755 #undef FLD
1756     return idesc;
1757   }
1758
1759  extract_sfmt_seth:
1760   {
1761     const IDESC *idesc = &m32rbf_insn_data[itype];
1762     CGEN_INSN_WORD insn = entire_insn;
1763 #define FLD(f) abuf->fields.sfmt_seth.f
1764     UINT f_r1;
1765     UINT f_hi16;
1766
1767     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1768     f_hi16 = EXTRACT_MSB0_UINT (insn, 32, 16, 16);
1769
1770   /* Record the fields for the semantic handler.  */
1771   FLD (f_hi16) = f_hi16;
1772   FLD (f_r1) = f_r1;
1773   FLD (i_dr) = & CPU (h_gr)[f_r1];
1774   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_seth", "f_hi16 0x%x", 'x', f_hi16, "f_r1 0x%x", 'x', f_r1, "dr 0x%x", 'x', f_r1, (char *) 0));
1775
1776 #if WITH_PROFILE_MODEL_P
1777   /* Record the fields for profiling.  */
1778   if (PROFILE_MODEL_P (current_cpu))
1779     {
1780       FLD (out_dr) = f_r1;
1781     }
1782 #endif
1783 #undef FLD
1784     return idesc;
1785   }
1786
1787  extract_sfmt_sll3:
1788   {
1789     const IDESC *idesc = &m32rbf_insn_data[itype];
1790     CGEN_INSN_WORD insn = entire_insn;
1791 #define FLD(f) abuf->fields.sfmt_add3.f
1792     UINT f_r1;
1793     UINT f_r2;
1794     INT f_simm16;
1795
1796     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1797     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1798     f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
1799
1800   /* Record the fields for the semantic handler.  */
1801   FLD (f_simm16) = f_simm16;
1802   FLD (f_r2) = f_r2;
1803   FLD (f_r1) = f_r1;
1804   FLD (i_sr) = & CPU (h_gr)[f_r2];
1805   FLD (i_dr) = & CPU (h_gr)[f_r1];
1806   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sll3", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1807
1808 #if WITH_PROFILE_MODEL_P
1809   /* Record the fields for profiling.  */
1810   if (PROFILE_MODEL_P (current_cpu))
1811     {
1812       FLD (in_sr) = f_r2;
1813       FLD (out_dr) = f_r1;
1814     }
1815 #endif
1816 #undef FLD
1817     return idesc;
1818   }
1819
1820  extract_sfmt_slli:
1821   {
1822     const IDESC *idesc = &m32rbf_insn_data[itype];
1823     CGEN_INSN_WORD insn = entire_insn;
1824 #define FLD(f) abuf->fields.sfmt_slli.f
1825     UINT f_r1;
1826     UINT f_uimm5;
1827
1828     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1829     f_uimm5 = EXTRACT_MSB0_UINT (insn, 16, 11, 5);
1830
1831   /* Record the fields for the semantic handler.  */
1832   FLD (f_r1) = f_r1;
1833   FLD (f_uimm5) = f_uimm5;
1834   FLD (i_dr) = & CPU (h_gr)[f_r1];
1835   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_slli", "f_r1 0x%x", 'x', f_r1, "f_uimm5 0x%x", 'x', f_uimm5, "dr 0x%x", 'x', f_r1, (char *) 0));
1836
1837 #if WITH_PROFILE_MODEL_P
1838   /* Record the fields for profiling.  */
1839   if (PROFILE_MODEL_P (current_cpu))
1840     {
1841       FLD (in_dr) = f_r1;
1842       FLD (out_dr) = f_r1;
1843     }
1844 #endif
1845 #undef FLD
1846     return idesc;
1847   }
1848
1849  extract_sfmt_st:
1850   {
1851     const IDESC *idesc = &m32rbf_insn_data[itype];
1852     CGEN_INSN_WORD insn = entire_insn;
1853 #define FLD(f) abuf->fields.sfmt_st_plus.f
1854     UINT f_r1;
1855     UINT f_r2;
1856
1857     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1858     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1859
1860   /* Record the fields for the semantic handler.  */
1861   FLD (f_r1) = f_r1;
1862   FLD (f_r2) = f_r2;
1863   FLD (i_src1) = & CPU (h_gr)[f_r1];
1864   FLD (i_src2) = & CPU (h_gr)[f_r2];
1865   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1866
1867 #if WITH_PROFILE_MODEL_P
1868   /* Record the fields for profiling.  */
1869   if (PROFILE_MODEL_P (current_cpu))
1870     {
1871       FLD (in_src1) = f_r1;
1872       FLD (in_src2) = f_r2;
1873     }
1874 #endif
1875 #undef FLD
1876     return idesc;
1877   }
1878
1879  extract_sfmt_st_d:
1880   {
1881     const IDESC *idesc = &m32rbf_insn_data[itype];
1882     CGEN_INSN_WORD insn = entire_insn;
1883 #define FLD(f) abuf->fields.sfmt_st_d.f
1884     UINT f_r1;
1885     UINT f_r2;
1886     INT f_simm16;
1887
1888     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1889     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1890     f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
1891
1892   /* Record the fields for the semantic handler.  */
1893   FLD (f_simm16) = f_simm16;
1894   FLD (f_r1) = f_r1;
1895   FLD (f_r2) = f_r2;
1896   FLD (i_src1) = & CPU (h_gr)[f_r1];
1897   FLD (i_src2) = & CPU (h_gr)[f_r2];
1898   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1899
1900 #if WITH_PROFILE_MODEL_P
1901   /* Record the fields for profiling.  */
1902   if (PROFILE_MODEL_P (current_cpu))
1903     {
1904       FLD (in_src1) = f_r1;
1905       FLD (in_src2) = f_r2;
1906     }
1907 #endif
1908 #undef FLD
1909     return idesc;
1910   }
1911
1912  extract_sfmt_stb:
1913   {
1914     const IDESC *idesc = &m32rbf_insn_data[itype];
1915     CGEN_INSN_WORD insn = entire_insn;
1916 #define FLD(f) abuf->fields.sfmt_st_plus.f
1917     UINT f_r1;
1918     UINT f_r2;
1919
1920     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1921     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1922
1923   /* Record the fields for the semantic handler.  */
1924   FLD (f_r1) = f_r1;
1925   FLD (f_r2) = f_r2;
1926   FLD (i_src1) = & CPU (h_gr)[f_r1];
1927   FLD (i_src2) = & CPU (h_gr)[f_r2];
1928   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1929
1930 #if WITH_PROFILE_MODEL_P
1931   /* Record the fields for profiling.  */
1932   if (PROFILE_MODEL_P (current_cpu))
1933     {
1934       FLD (in_src1) = f_r1;
1935       FLD (in_src2) = f_r2;
1936     }
1937 #endif
1938 #undef FLD
1939     return idesc;
1940   }
1941
1942  extract_sfmt_stb_d:
1943   {
1944     const IDESC *idesc = &m32rbf_insn_data[itype];
1945     CGEN_INSN_WORD insn = entire_insn;
1946 #define FLD(f) abuf->fields.sfmt_st_d.f
1947     UINT f_r1;
1948     UINT f_r2;
1949     INT f_simm16;
1950
1951     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
1952     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
1953     f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
1954
1955   /* Record the fields for the semantic handler.  */
1956   FLD (f_simm16) = f_simm16;
1957   FLD (f_r1) = f_r1;
1958   FLD (f_r2) = f_r2;
1959   FLD (i_src1) = & CPU (h_gr)[f_r1];
1960   FLD (i_src2) = & CPU (h_gr)[f_r2];
1961   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_stb_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1962
1963 #if WITH_PROFILE_MODEL_P
1964   /* Record the fields for profiling.  */
1965   if (PROFILE_MODEL_P (current_cpu))
1966     {
1967       FLD (in_src1) = f_r1;
1968       FLD (in_src2) = f_r2;
1969     }
1970 #endif
1971 #undef FLD
1972     return idesc;
1973   }
1974
1975  extract_sfmt_sth:
1976   {
1977     const IDESC *idesc = &m32rbf_insn_data[itype];
1978     CGEN_INSN_WORD insn = entire_insn;
1979 #define FLD(f) abuf->fields.sfmt_st_plus.f
1980     UINT f_r1;
1981     UINT f_r2;
1982
1983     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
1984     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
1985
1986   /* Record the fields for the semantic handler.  */
1987   FLD (f_r1) = f_r1;
1988   FLD (f_r2) = f_r2;
1989   FLD (i_src1) = & CPU (h_gr)[f_r1];
1990   FLD (i_src2) = & CPU (h_gr)[f_r2];
1991   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1992
1993 #if WITH_PROFILE_MODEL_P
1994   /* Record the fields for profiling.  */
1995   if (PROFILE_MODEL_P (current_cpu))
1996     {
1997       FLD (in_src1) = f_r1;
1998       FLD (in_src2) = f_r2;
1999     }
2000 #endif
2001 #undef FLD
2002     return idesc;
2003   }
2004
2005  extract_sfmt_sth_d:
2006   {
2007     const IDESC *idesc = &m32rbf_insn_data[itype];
2008     CGEN_INSN_WORD insn = entire_insn;
2009 #define FLD(f) abuf->fields.sfmt_st_d.f
2010     UINT f_r1;
2011     UINT f_r2;
2012     INT f_simm16;
2013
2014     f_r1 = EXTRACT_MSB0_UINT (insn, 32, 4, 4);
2015     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
2016     f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
2017
2018   /* Record the fields for the semantic handler.  */
2019   FLD (f_simm16) = f_simm16;
2020   FLD (f_r1) = f_r1;
2021   FLD (f_r2) = f_r2;
2022   FLD (i_src1) = & CPU (h_gr)[f_r1];
2023   FLD (i_src2) = & CPU (h_gr)[f_r2];
2024   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_sth_d", "f_simm16 0x%x", 'x', f_simm16, "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2025
2026 #if WITH_PROFILE_MODEL_P
2027   /* Record the fields for profiling.  */
2028   if (PROFILE_MODEL_P (current_cpu))
2029     {
2030       FLD (in_src1) = f_r1;
2031       FLD (in_src2) = f_r2;
2032     }
2033 #endif
2034 #undef FLD
2035     return idesc;
2036   }
2037
2038  extract_sfmt_st_plus:
2039   {
2040     const IDESC *idesc = &m32rbf_insn_data[itype];
2041     CGEN_INSN_WORD insn = entire_insn;
2042 #define FLD(f) abuf->fields.sfmt_st_plus.f
2043     UINT f_r1;
2044     UINT f_r2;
2045
2046     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2047     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2048
2049   /* Record the fields for the semantic handler.  */
2050   FLD (f_r1) = f_r1;
2051   FLD (f_r2) = f_r2;
2052   FLD (i_src1) = & CPU (h_gr)[f_r1];
2053   FLD (i_src2) = & CPU (h_gr)[f_r2];
2054   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_st_plus", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2055
2056 #if WITH_PROFILE_MODEL_P
2057   /* Record the fields for profiling.  */
2058   if (PROFILE_MODEL_P (current_cpu))
2059     {
2060       FLD (in_src1) = f_r1;
2061       FLD (in_src2) = f_r2;
2062       FLD (out_src2) = f_r2;
2063     }
2064 #endif
2065 #undef FLD
2066     return idesc;
2067   }
2068
2069  extract_sfmt_trap:
2070   {
2071     const IDESC *idesc = &m32rbf_insn_data[itype];
2072     CGEN_INSN_WORD insn = entire_insn;
2073 #define FLD(f) abuf->fields.sfmt_trap.f
2074     UINT f_uimm4;
2075
2076     f_uimm4 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2077
2078   /* Record the fields for the semantic handler.  */
2079   FLD (f_uimm4) = f_uimm4;
2080   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_trap", "f_uimm4 0x%x", 'x', f_uimm4, (char *) 0));
2081
2082 #if WITH_PROFILE_MODEL_P
2083   /* Record the fields for profiling.  */
2084   if (PROFILE_MODEL_P (current_cpu))
2085     {
2086     }
2087 #endif
2088 #undef FLD
2089     return idesc;
2090   }
2091
2092  extract_sfmt_unlock:
2093   {
2094     const IDESC *idesc = &m32rbf_insn_data[itype];
2095     CGEN_INSN_WORD insn = entire_insn;
2096 #define FLD(f) abuf->fields.sfmt_st_plus.f
2097     UINT f_r1;
2098     UINT f_r2;
2099
2100     f_r1 = EXTRACT_MSB0_UINT (insn, 16, 4, 4);
2101     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2102
2103   /* Record the fields for the semantic handler.  */
2104   FLD (f_r1) = f_r1;
2105   FLD (f_r2) = f_r2;
2106   FLD (i_src1) = & CPU (h_gr)[f_r1];
2107   FLD (i_src2) = & CPU (h_gr)[f_r2];
2108   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_unlock", "f_r1 0x%x", 'x', f_r1, "f_r2 0x%x", 'x', f_r2, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2109
2110 #if WITH_PROFILE_MODEL_P
2111   /* Record the fields for profiling.  */
2112   if (PROFILE_MODEL_P (current_cpu))
2113     {
2114       FLD (in_src1) = f_r1;
2115       FLD (in_src2) = f_r2;
2116     }
2117 #endif
2118 #undef FLD
2119     return idesc;
2120   }
2121
2122  extract_sfmt_clrpsw:
2123   {
2124     const IDESC *idesc = &m32rbf_insn_data[itype];
2125     CGEN_INSN_WORD insn = entire_insn;
2126 #define FLD(f) abuf->fields.sfmt_clrpsw.f
2127     UINT f_uimm8;
2128
2129     f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8);
2130
2131   /* Record the fields for the semantic handler.  */
2132   FLD (f_uimm8) = f_uimm8;
2133   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_clrpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0));
2134
2135 #undef FLD
2136     return idesc;
2137   }
2138
2139  extract_sfmt_setpsw:
2140   {
2141     const IDESC *idesc = &m32rbf_insn_data[itype];
2142     CGEN_INSN_WORD insn = entire_insn;
2143 #define FLD(f) abuf->fields.sfmt_clrpsw.f
2144     UINT f_uimm8;
2145
2146     f_uimm8 = EXTRACT_MSB0_UINT (insn, 16, 8, 8);
2147
2148   /* Record the fields for the semantic handler.  */
2149   FLD (f_uimm8) = f_uimm8;
2150   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_setpsw", "f_uimm8 0x%x", 'x', f_uimm8, (char *) 0));
2151
2152 #undef FLD
2153     return idesc;
2154   }
2155
2156  extract_sfmt_bset:
2157   {
2158     const IDESC *idesc = &m32rbf_insn_data[itype];
2159     CGEN_INSN_WORD insn = entire_insn;
2160 #define FLD(f) abuf->fields.sfmt_bset.f
2161     UINT f_uimm3;
2162     UINT f_r2;
2163     INT f_simm16;
2164
2165     f_uimm3 = EXTRACT_MSB0_UINT (insn, 32, 5, 3);
2166     f_r2 = EXTRACT_MSB0_UINT (insn, 32, 12, 4);
2167     f_simm16 = EXTRACT_MSB0_SINT (insn, 32, 16, 16);
2168
2169   /* Record the fields for the semantic handler.  */
2170   FLD (f_simm16) = f_simm16;
2171   FLD (f_r2) = f_r2;
2172   FLD (f_uimm3) = f_uimm3;
2173   FLD (i_sr) = & CPU (h_gr)[f_r2];
2174   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_bset", "f_simm16 0x%x", 'x', f_simm16, "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0));
2175
2176 #if WITH_PROFILE_MODEL_P
2177   /* Record the fields for profiling.  */
2178   if (PROFILE_MODEL_P (current_cpu))
2179     {
2180       FLD (in_sr) = f_r2;
2181     }
2182 #endif
2183 #undef FLD
2184     return idesc;
2185   }
2186
2187  extract_sfmt_btst:
2188   {
2189     const IDESC *idesc = &m32rbf_insn_data[itype];
2190     CGEN_INSN_WORD insn = entire_insn;
2191 #define FLD(f) abuf->fields.sfmt_bset.f
2192     UINT f_uimm3;
2193     UINT f_r2;
2194
2195     f_uimm3 = EXTRACT_MSB0_UINT (insn, 16, 5, 3);
2196     f_r2 = EXTRACT_MSB0_UINT (insn, 16, 12, 4);
2197
2198   /* Record the fields for the semantic handler.  */
2199   FLD (f_r2) = f_r2;
2200   FLD (f_uimm3) = f_uimm3;
2201   FLD (i_sr) = & CPU (h_gr)[f_r2];
2202   CGEN_TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "sfmt_btst", "f_r2 0x%x", 'x', f_r2, "f_uimm3 0x%x", 'x', f_uimm3, "sr 0x%x", 'x', f_r2, (char *) 0));
2203
2204 #if WITH_PROFILE_MODEL_P
2205   /* Record the fields for profiling.  */
2206   if (PROFILE_MODEL_P (current_cpu))
2207     {
2208       FLD (in_sr) = f_r2;
2209     }
2210 #endif
2211 #undef FLD
2212     return idesc;
2213   }
2214
2215 }