gdb/arch/arm-linux.c

   1 /* Common target dependent code for GNU/Linux on ARM systems.
   2
   3    Copyright (C) 1999-2024 Free Software Foundation, Inc.
   4
   5    This file is part of GDB.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #include "gdbsupport/common-regcache.h"
  21 #include "arch/arm.h"
  22 #include "arm-linux.h"
  23 #include "arch/arm-get-next-pcs.h"
  24
  25 /* Calculate the offset from stack pointer of the pc register on the stack
  26    in the case of a sigreturn or sigreturn_rt syscall.  */
  27 int
  28 arm_linux_sigreturn_next_pc_offset (unsigned long sp,
  29                                     unsigned long sp_data,
  30                                     unsigned long svc_number,
  31                                     int is_sigreturn)
  32 {
  33   /* Offset of R0 register.  */
  34   int r0_offset = 0;
  35   /* Offset of PC register.  */
  36   int pc_offset = 0;
  37
  38   if (is_sigreturn)
  39     {
  40       if (sp_data == ARM_NEW_SIGFRAME_MAGIC)
  41         r0_offset = ARM_UCONTEXT_SIGCONTEXT + ARM_SIGCONTEXT_R0;
  42       else
  43         r0_offset = ARM_SIGCONTEXT_R0;
  44     }
  45   else
  46     {
  47       if (sp_data == sp + ARM_OLD_RT_SIGFRAME_SIGINFO)
  48         r0_offset = ARM_OLD_RT_SIGFRAME_UCONTEXT;
  49       else
  50         r0_offset = ARM_NEW_RT_SIGFRAME_UCONTEXT;
  51
  52       r0_offset += ARM_UCONTEXT_SIGCONTEXT + ARM_SIGCONTEXT_R0;
  53     }
  54
  55   pc_offset = r0_offset + ARM_INT_REGISTER_SIZE * ARM_PC_REGNUM;
  56
  57   return pc_offset;
  58 }
  59
  60 /* Implementation of "fixup" method of struct arm_get_next_pcs_ops
  61    for arm-linux.  */
  62
  63 CORE_ADDR
  64 arm_linux_get_next_pcs_fixup (struct arm_get_next_pcs *self,
  65                               CORE_ADDR nextpc)
  66 {
  67   /* The Linux kernel offers some user-mode helpers in a high page.  We can
  68      not read this page (as of 2.6.23), and even if we could then we
  69      couldn't set breakpoints in it, and even if we could then the atomic
  70      operations would fail when interrupted.  They are all (tail) called
  71      as functions and return to the address in LR.  However, when GDB single
  72      step this instruction, this instruction isn't executed yet, and LR
  73      may not be updated yet.  In other words, GDB can get the target
  74      address from LR if this instruction isn't BL or BLX.  */
  75   if (nextpc > 0xffff0000)
  76     {
  77       int bl_blx_p = 0;
  78       CORE_ADDR pc = regcache_read_pc (self->regcache);
  79       int pc_incr = 0;
  80
  81       if (self->ops->is_thumb (self))
  82         {
  83           unsigned short inst1
  84             = self->ops->read_mem_uint (pc, 2, self->byte_order_for_code);
  85
  86           if (bits (inst1, 8, 15) == 0x47 && bit (inst1, 7))
  87             {
  88               /* BLX Rm */
  89               bl_blx_p = 1;
  90               pc_incr = 2;
  91             }
  92           else if (thumb_insn_size (inst1) == 4)
  93             {
  94               unsigned short inst2;
  95
  96               inst2 = self->ops->read_mem_uint (pc + 2, 2,
  97                                                 self->byte_order_for_code);
  98
  99               if ((inst1 & 0xf800) == 0xf000 && bits (inst2, 14, 15) == 0x3)
 100                 {
 101                   /* BL <label> and BLX <label> */
 102                   bl_blx_p = 1;
 103                   pc_incr = 4;
 104                 }
 105             }
 106
 107           pc_incr = MAKE_THUMB_ADDR (pc_incr);
 108         }
 109       else
 110         {
 111           unsigned int insn
 112             = self->ops->read_mem_uint (pc, 4, self->byte_order_for_code);
 113
 114           if (bits (insn, 28, 31) == INST_NV)
 115             {
 116               if (bits (insn, 25, 27) == 0x5) /* BLX <label> */
 117                 bl_blx_p = 1;
 118             }
 119           else
 120             {
 121               if (bits (insn, 24, 27) == 0xb  /* BL <label> */
 122                   || bits (insn, 4, 27) == 0x12fff3 /* BLX Rm */)
 123                 bl_blx_p = 1;
 124             }
 125
 126           pc_incr = 4;
 127         }
 128
 129       /* If the instruction BL or BLX, the target address is the following
 130          instruction of BL or BLX, otherwise, the target address is in LR
 131          already.  */
 132       if (bl_blx_p)
 133         nextpc = pc + pc_incr;
 134       else
 135         nextpc = regcache_raw_get_unsigned (self->regcache, ARM_LR_REGNUM);
 136     }
 137   return nextpc;
 138 }