gdb/arch/arm.c

   1 /* Common target dependent code for GDB on ARM systems.
   2
   3    Copyright (C) 1988-2024 Free Software Foundation, Inc.
   4
   5    This file is part of GDB.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #include "gdbsupport/common-regcache.h"
  21 #include "arm.h"
  22
  23 #include "../features/arm/arm-core.c"
  24 #include "../features/arm/arm-tls.c"
  25 #include "../features/arm/arm-vfpv2.c"
  26 #include "../features/arm/arm-vfpv3.c"
  27 #include "../features/arm/xscale-iwmmxt.c"
  28 #include "../features/arm/arm-m-profile.c"
  29 #include "../features/arm/arm-m-profile-with-fpa.c"
  30 #include "../features/arm/arm-m-profile-mve.c"
  31 #include "../features/arm/arm-m-system.c"
  32
  33 /* See arm.h.  */
  34
  35 int
  36 thumb_insn_size (unsigned short inst1)
  37 {
  38   if ((inst1 & 0xe000) == 0xe000 && (inst1 & 0x1800) != 0)
  39     return 4;
  40   else
  41     return 2;
  42 }
  43
  44 /* See arm.h.  */
  45
  46 int
  47 condition_true (unsigned long cond, unsigned long status_reg)
  48 {
  49   if (cond == INST_AL || cond == INST_NV)
  50     return 1;
  51
  52   switch (cond)
  53     {
  54     case INST_EQ:
  55       return ((status_reg & FLAG_Z) != 0);
  56     case INST_NE:
  57       return ((status_reg & FLAG_Z) == 0);
  58     case INST_CS:
  59       return ((status_reg & FLAG_C) != 0);
  60     case INST_CC:
  61       return ((status_reg & FLAG_C) == 0);
  62     case INST_MI:
  63       return ((status_reg & FLAG_N) != 0);
  64     case INST_PL:
  65       return ((status_reg & FLAG_N) == 0);
  66     case INST_VS:
  67       return ((status_reg & FLAG_V) != 0);
  68     case INST_VC:
  69       return ((status_reg & FLAG_V) == 0);
  70     case INST_HI:
  71       return ((status_reg & (FLAG_C | FLAG_Z)) == FLAG_C);
  72     case INST_LS:
  73       return ((status_reg & (FLAG_C | FLAG_Z)) != FLAG_C);
  74     case INST_GE:
  75       return (((status_reg & FLAG_N) == 0) == ((status_reg & FLAG_V) == 0));
  76     case INST_LT:
  77       return (((status_reg & FLAG_N) == 0) != ((status_reg & FLAG_V) == 0));
  78     case INST_GT:
  79       return (((status_reg & FLAG_Z) == 0)
  80               && (((status_reg & FLAG_N) == 0)
  81                   == ((status_reg & FLAG_V) == 0)));
  82     case INST_LE:
  83       return (((status_reg & FLAG_Z) != 0)
  84               || (((status_reg & FLAG_N) == 0)
  85                   != ((status_reg & FLAG_V) == 0)));
  86     }
  87   return 1;
  88 }
  89
  90
  91 /* See arm.h.  */
  92
  93 int
  94 thumb_advance_itstate (unsigned int itstate)
  95 {
  96   /* Preserve IT[7:5], the first three bits of the condition.  Shift
  97      the upcoming condition flags left by one bit.  */
  98   itstate = (itstate & 0xe0) | ((itstate << 1) & 0x1f);
  99
 100   /* If we have finished the IT block, clear the state.  */
 101   if ((itstate & 0x0f) == 0)
 102     itstate = 0;
 103
 104   return itstate;
 105 }
 106
 107 /* See arm.h.  */
 108
 109 int
 110 arm_instruction_changes_pc (uint32_t this_instr)
 111 {
 112   if (bits (this_instr, 28, 31) == INST_NV)
 113     /* Unconditional instructions.  */
 114     switch (bits (this_instr, 24, 27))
 115       {
 116       case 0xa:
 117       case 0xb:
 118         /* Branch with Link and change to Thumb.  */
 119         return 1;
 120       case 0xc:
 121       case 0xd:
 122       case 0xe:
 123         /* Coprocessor register transfer.  */
 124         if (bits (this_instr, 12, 15) == 15)
 125           error (_("Invalid update to pc in instruction"));
 126         return 0;
 127       default:
 128         return 0;
 129       }
 130   else
 131     switch (bits (this_instr, 25, 27))
 132       {
 133       case 0x0:
 134         if (bits (this_instr, 23, 24) == 2 && bit (this_instr, 20) == 0)
 135           {
 136             /* Multiplies and extra load/stores.  */
 137             if (bit (this_instr, 4) == 1 && bit (this_instr, 7) == 1)
 138               /* Neither multiplies nor extension load/stores are allowed
 139                  to modify PC.  */
 140               return 0;
 141
 142             /* Otherwise, miscellaneous instructions.  */
 143
 144             /* BX <reg>, BXJ <reg>, BLX <reg> */
 145             if (bits (this_instr, 4, 27) == 0x12fff1
 146                 || bits (this_instr, 4, 27) == 0x12fff2
 147                 || bits (this_instr, 4, 27) == 0x12fff3)
 148               return 1;
 149
 150             /* Other miscellaneous instructions are unpredictable if they
 151                modify PC.  */
 152             return 0;
 153           }
 154         /* Data processing instruction.  */
 155         [[fallthrough]];
 156
 157       case 0x1:
 158         if (bits (this_instr, 12, 15) == 15)
 159           return 1;
 160         else
 161           return 0;
 162
 163       case 0x2:
 164       case 0x3:
 165         /* Media instructions and architecturally undefined instructions.  */
 166         if (bits (this_instr, 25, 27) == 3 && bit (this_instr, 4) == 1)
 167           return 0;
 168
 169         /* Stores.  */
 170         if (bit (this_instr, 20) == 0)
 171           return 0;
 172
 173         /* Loads.  */
 174         if (bits (this_instr, 12, 15) == ARM_PC_REGNUM)
 175           return 1;
 176         else
 177           return 0;
 178
 179       case 0x4:
 180         /* Load/store multiple.  */
 181         if (bit (this_instr, 20) == 1 && bit (this_instr, 15) == 1)
 182           return 1;
 183         else
 184           return 0;
 185
 186       case 0x5:
 187         /* Branch and branch with link.  */
 188         return 1;
 189
 190       case 0x6:
 191       case 0x7:
 192         /* Coprocessor transfers or SWIs can not affect PC.  */
 193         return 0;
 194
 195       default:
 196         internal_error (_("bad value in switch"));
 197       }
 198 }
 199
 200 /* See arm.h.  */
 201
 202 int
 203 thumb_instruction_changes_pc (unsigned short inst)
 204 {
 205   if ((inst & 0xff00) == 0xbd00)        /* pop {rlist, pc} */
 206     return 1;
 207
 208   if ((inst & 0xf000) == 0xd000)        /* conditional branch */
 209     return 1;
 210
 211   if ((inst & 0xf800) == 0xe000)        /* unconditional branch */
 212     return 1;
 213
 214   if ((inst & 0xff00) == 0x4700)        /* bx REG, blx REG */
 215     return 1;
 216
 217   if ((inst & 0xff87) == 0x4687)        /* mov pc, REG */
 218     return 1;
 219
 220   if ((inst & 0xf500) == 0xb100)        /* CBNZ or CBZ.  */
 221     return 1;
 222
 223   return 0;
 224 }
 225
 226
 227 /* See arm.h.  */
 228
 229 int
 230 thumb2_instruction_changes_pc (unsigned short inst1, unsigned short inst2)
 231 {
 232   if ((inst1 & 0xf800) == 0xf000 && (inst2 & 0x8000) == 0x8000)
 233     {
 234       /* Branches and miscellaneous control instructions.  */
 235
 236       if ((inst2 & 0x1000) != 0 || (inst2 & 0xd001) == 0xc000)
 237         {
 238           /* B, BL, BLX.  */
 239           return 1;
 240         }
 241       else if (inst1 == 0xf3de && (inst2 & 0xff00) == 0x3f00)
 242         {
 243           /* SUBS PC, LR, #imm8.  */
 244           return 1;
 245         }
 246       else if ((inst2 & 0xd000) == 0x8000 && (inst1 & 0x0380) != 0x0380)
 247         {
 248           /* Conditional branch.  */
 249           return 1;
 250         }
 251
 252       return 0;
 253     }
 254
 255   if ((inst1 & 0xfe50) == 0xe810)
 256     {
 257       /* Load multiple or RFE.  */
 258
 259       if (bit (inst1, 7) && !bit (inst1, 8))
 260         {
 261           /* LDMIA or POP */
 262           if (bit (inst2, 15))
 263             return 1;
 264         }
 265       else if (!bit (inst1, 7) && bit (inst1, 8))
 266         {
 267           /* LDMDB */
 268           if (bit (inst2, 15))
 269             return 1;
 270         }
 271       else if (bit (inst1, 7) && bit (inst1, 8))
 272         {
 273           /* RFEIA */
 274           return 1;
 275         }
 276       else if (!bit (inst1, 7) && !bit (inst1, 8))
 277         {
 278           /* RFEDB */
 279           return 1;
 280         }
 281
 282       return 0;
 283     }
 284
 285   if ((inst1 & 0xffef) == 0xea4f && (inst2 & 0xfff0) == 0x0f00)
 286     {
 287       /* MOV PC or MOVS PC.  */
 288       return 1;
 289     }
 290
 291   if ((inst1 & 0xff70) == 0xf850 && (inst2 & 0xf000) == 0xf000)
 292     {
 293       /* LDR PC.  */
 294       if (bits (inst1, 0, 3) == 15)
 295         return 1;
 296       if (bit (inst1, 7))
 297         return 1;
 298       if (bit (inst2, 11))
 299         return 1;
 300       if ((inst2 & 0x0fc0) == 0x0000)
 301         return 1;
 302
 303       return 0;
 304     }
 305
 306   if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf000)
 307     {
 308       /* TBB.  */
 309       return 1;
 310     }
 311
 312   if ((inst1 & 0xfff0) == 0xe8d0 && (inst2 & 0xfff0) == 0xf010)
 313     {
 314       /* TBH.  */
 315       return 1;
 316     }
 317
 318   return 0;
 319 }
 320
 321 /* See arm.h.  */
 322
 323 unsigned long
 324 shifted_reg_val (reg_buffer_common *regcache, unsigned long inst,
 325                  int carry, unsigned long pc_val, unsigned long status_reg)
 326 {
 327   unsigned long res, shift;
 328   int rm = bits (inst, 0, 3);
 329   unsigned long shifttype = bits (inst, 5, 6);
 330
 331   if (bit (inst, 4))
 332     {
 333       int rs = bits (inst, 8, 11);
 334       shift = (rs == 15
 335                ? pc_val + 8
 336                : regcache_raw_get_unsigned (regcache, rs)) & 0xFF;
 337     }
 338   else
 339     shift = bits (inst, 7, 11);
 340
 341   res = (rm == ARM_PC_REGNUM
 342          ? (pc_val + (bit (inst, 4) ? 12 : 8))
 343          : regcache_raw_get_unsigned (regcache, rm));
 344
 345   switch (shifttype)
 346     {
 347     case 0:                     /* LSL */
 348       res = shift >= 32 ? 0 : res << shift;
 349       break;
 350
 351     case 1:                     /* LSR */
 352       res = shift >= 32 ? 0 : res >> shift;
 353       break;
 354
 355     case 2:                     /* ASR */
 356       if (shift >= 32)
 357         shift = 31;
 358       res = ((res & 0x80000000L)
 359              ? ~((~res) >> shift) : res >> shift);
 360       break;
 361
 362     case 3:                     /* ROR/RRX */
 363       shift &= 31;
 364       if (shift == 0)
 365         res = (res >> 1) | (carry ? 0x80000000L : 0);
 366       else
 367         res = (res >> shift) | (res << (32 - shift));
 368       break;
 369     }
 370
 371   return res & 0xffffffff;
 372 }
 373
 374 /* See arch/arm.h.  */
 375
 376 target_desc *
 377 arm_create_target_description (arm_fp_type fp_type, bool tls)
 378 {
 379   target_desc_up tdesc = allocate_target_description ();
 380
 381 #ifndef IN_PROCESS_AGENT
 382   if (fp_type == ARM_FP_TYPE_IWMMXT)
 383     set_tdesc_architecture (tdesc.get (), "iwmmxt");
 384   else
 385     set_tdesc_architecture (tdesc.get (), "arm");
 386 #endif
 387
 388   long regnum = 0;
 389
 390   regnum = create_feature_arm_arm_core (tdesc.get (), regnum);
 391
 392   switch (fp_type)
 393     {
 394     case ARM_FP_TYPE_NONE:
 395       break;
 396
 397     case ARM_FP_TYPE_VFPV2:
 398       regnum = create_feature_arm_arm_vfpv2 (tdesc.get (), regnum);
 399       break;
 400
 401     case ARM_FP_TYPE_VFPV3:
 402       regnum = create_feature_arm_arm_vfpv3 (tdesc.get (), regnum);
 403       break;
 404
 405     case ARM_FP_TYPE_IWMMXT:
 406       regnum = create_feature_arm_xscale_iwmmxt (tdesc.get (), regnum);
 407       break;
 408
 409     default:
 410       error (_("Invalid Arm FP type: %d"), fp_type);
 411     }
 412
 413   if (tls)
 414     regnum = create_feature_arm_arm_tls (tdesc.get (), regnum);
 415
 416   return tdesc.release ();
 417 }
 418
 419 /* See arch/arm.h.  */
 420
 421 target_desc *
 422 arm_create_mprofile_target_description (arm_m_profile_type m_type)
 423 {
 424   target_desc *tdesc = allocate_target_description ().release ();
 425
 426 #ifndef IN_PROCESS_AGENT
 427   set_tdesc_architecture (tdesc, "arm");
 428 #endif
 429
 430   long regnum = 0;
 431
 432   switch (m_type)
 433     {
 434     case ARM_M_TYPE_M_PROFILE:
 435       regnum = create_feature_arm_arm_m_profile (tdesc, regnum);
 436       break;
 437
 438     case ARM_M_TYPE_VFP_D16:
 439       regnum = create_feature_arm_arm_m_profile (tdesc, regnum);
 440       regnum = create_feature_arm_arm_vfpv2 (tdesc, regnum);
 441       break;
 442
 443     case ARM_M_TYPE_WITH_FPA:
 444       regnum = create_feature_arm_arm_m_profile_with_fpa (tdesc, regnum);
 445       break;
 446
 447     case ARM_M_TYPE_MVE:
 448       regnum = create_feature_arm_arm_m_profile (tdesc, regnum);
 449       regnum = create_feature_arm_arm_vfpv2 (tdesc, regnum);
 450       regnum = create_feature_arm_arm_m_profile_mve (tdesc, regnum);
 451       break;
 452
 453     case ARM_M_TYPE_SYSTEM:
 454       regnum = create_feature_arm_arm_m_profile (tdesc, regnum);
 455       regnum = create_feature_arm_arm_m_system (tdesc, regnum);
 456       break;
 457
 458     default:
 459       error (_("Invalid Arm M type: %d"), m_type);
 460     }
 461
 462   return tdesc;
 463 }