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Add translations for various sub-directories
[binutils-gdb.git] / gdb / csky-tdep.c
blob4f41a51b576f5dc67fcc523e93d9bc8e834bc27b
1 /* Target-dependent code for the CSKY architecture, for GDB.
2
3 Copyright (C) 2010-2024 Free Software Foundation, Inc.
4
5 Contributed by C-SKY Microsystems and Mentor Graphics.
6
7 This file is part of GDB.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21
22 #include "extract-store-integer.h"
23 #include "gdbsupport/gdb_assert.h"
24 #include "frame.h"
25 #include "inferior.h"
26 #include "symtab.h"
27 #include "value.h"
28 #include "cli/cli-cmds.h"
29 #include "language.h"
30 #include "gdbcore.h"
31 #include "symfile.h"
32 #include "objfiles.h"
33 #include "gdbtypes.h"
34 #include "target.h"
35 #include "arch-utils.h"
36 #include "regcache.h"
37 #include "osabi.h"
38 #include "block.h"
39 #include "reggroups.h"
40 #include "elf/csky.h"
41 #include "elf-bfd.h"
42 #include "symcat.h"
43 #include "sim-regno.h"
44 #include "dis-asm.h"
45 #include "frame-unwind.h"
46 #include "frame-base.h"
47 #include "trad-frame.h"
48 #include "infcall.h"
49 #include "floatformat.h"
50 #include "remote.h"
51 #include "target-descriptions.h"
52 #include "dwarf2/frame.h"
53 #include "user-regs.h"
54 #include "valprint.h"
55 #include "csky-tdep.h"
56 #include "regset.h"
57 #include "opcode/csky.h"
58 #include <algorithm>
59 #include <vector>
60
61 /* Control debugging information emitted in this file. */
62
63 static bool csky_debug = false;
64
65 static const reggroup *cr_reggroup;
66 static const reggroup *fr_reggroup;
67 static const reggroup *vr_reggroup;
68 static const reggroup *mmu_reggroup;
69 static const reggroup *prof_reggroup;
70
71 static const char *csky_supported_tdesc_feature_names[] = {
72 (const char *)"org.gnu.csky.abiv2.gpr",
73 (const char *)"org.gnu.csky.abiv2.fpu",
74 (const char *)"org.gnu.csky.abiv2.cr",
75 (const char *)"org.gnu.csky.abiv2.fvcr",
76 (const char *)"org.gnu.csky.abiv2.mmu",
77 (const char *)"org.gnu.csky.abiv2.tee",
78 (const char *)"org.gnu.csky.abiv2.fpu2",
79 (const char *)"org.gnu.csky.abiv2.bank0",
80 (const char *)"org.gnu.csky.abiv2.bank1",
81 (const char *)"org.gnu.csky.abiv2.bank2",
82 (const char *)"org.gnu.csky.abiv2.bank3",
83 (const char *)"org.gnu.csky.abiv2.bank4",
84 (const char *)"org.gnu.csky.abiv2.bank5",
85 (const char *)"org.gnu.csky.abiv2.bank6",
86 (const char *)"org.gnu.csky.abiv2.bank7",
87 (const char *)"org.gnu.csky.abiv2.bank8",
88 (const char *)"org.gnu.csky.abiv2.bank9",
89 (const char *)"org.gnu.csky.abiv2.bank10",
90 (const char *)"org.gnu.csky.abiv2.bank11",
91 (const char *)"org.gnu.csky.abiv2.bank12",
92 (const char *)"org.gnu.csky.abiv2.bank13",
93 (const char *)"org.gnu.csky.abiv2.bank14",
94 (const char *)"org.gnu.csky.abiv2.bank15",
95 (const char *)"org.gnu.csky.abiv2.bank16",
96 (const char *)"org.gnu.csky.abiv2.bank17",
97 (const char *)"org.gnu.csky.abiv2.bank18",
98 (const char *)"org.gnu.csky.abiv2.bank19",
99 (const char *)"org.gnu.csky.abiv2.bank20",
100 (const char *)"org.gnu.csky.abiv2.bank21",
101 (const char *)"org.gnu.csky.abiv2.bank22",
102 (const char *)"org.gnu.csky.abiv2.bank23",
103 (const char *)"org.gnu.csky.abiv2.bank24",
104 (const char *)"org.gnu.csky.abiv2.bank25",
105 (const char *)"org.gnu.csky.abiv2.bank26",
106 (const char *)"org.gnu.csky.abiv2.bank27",
107 (const char *)"org.gnu.csky.abiv2.bank28",
108 (const char *)"org.gnu.csky.abiv2.bank29",
109 (const char *)"org.gnu.csky.abiv2.bank30",
110 (const char *)"org.gnu.csky.abiv2.bank31"
111 };
112
113 struct csky_supported_tdesc_register
114 {
115 char name[16];
116 int num;
117 };
118
119 static const struct csky_supported_tdesc_register csky_supported_gpr_regs[] = {
120 {"r0", 0},
121 {"r1", 1},
122 {"r2", 2},
123 {"r3", 3},
124 {"r4", 4},
125 {"r5", 5},
126 {"r6", 6},
127 {"r7", 7},
128 {"r8", 8},
129 {"r9", 9},
130 {"r10", 10},
131 {"r11", 11},
132 {"r12", 12},
133 {"r13", 13},
134 {"r14", 14},
135 {"r15", 15},
136 {"r16", 16},
137 {"r17", 17},
138 {"r18", 18},
139 {"r19", 19},
140 {"r20", 20},
141 {"r21", 21},
142 {"r22", 22},
143 {"r23", 23},
144 {"r24", 24},
145 {"r25", 25},
146 {"r26", 26},
147 {"r27", 27},
148 {"r28", 28},
149 {"r28", 28},
150 {"r29", 29},
151 {"r30", 30},
152 {"r31", 31},
153 {"hi", CSKY_HI_REGNUM},
154 {"lo", CSKY_LO_REGNUM},
155 {"pc", CSKY_PC_REGNUM}
156 };
157
158 static const struct csky_supported_tdesc_register csky_supported_fpu_regs[] = {
159 /* fr0~fr15. */
160 {"fr0", CSKY_FR0_REGNUM + 0},
161 {"fr1", CSKY_FR0_REGNUM + 1},
162 {"fr2", CSKY_FR0_REGNUM + 2},
163 {"fr3", CSKY_FR0_REGNUM + 3},
164 {"fr4", CSKY_FR0_REGNUM + 4},
165 {"fr5", CSKY_FR0_REGNUM + 5},
166 {"fr6", CSKY_FR0_REGNUM + 6},
167 {"fr7", CSKY_FR0_REGNUM + 7},
168 {"fr8", CSKY_FR0_REGNUM + 8},
169 {"fr9", CSKY_FR0_REGNUM + 9},
170 {"fr10", CSKY_FR0_REGNUM + 10},
171 {"fr11", CSKY_FR0_REGNUM + 11},
172 {"fr12", CSKY_FR0_REGNUM + 12},
173 {"fr13", CSKY_FR0_REGNUM + 13},
174 {"fr14", CSKY_FR0_REGNUM + 14},
175 {"fr15", CSKY_FR0_REGNUM + 15},
176 /* fr16~fr31. */
177 {"fr16", CSKY_FR16_REGNUM + 0},
178 {"fr17", CSKY_FR16_REGNUM + 1},
179 {"fr18", CSKY_FR16_REGNUM + 2},
180 {"fr19", CSKY_FR16_REGNUM + 3},
181 {"fr20", CSKY_FR16_REGNUM + 4},
182 {"fr21", CSKY_FR16_REGNUM + 5},
183 {"fr22", CSKY_FR16_REGNUM + 6},
184 {"fr23", CSKY_FR16_REGNUM + 7},
185 {"fr24", CSKY_FR16_REGNUM + 8},
186 {"fr25", CSKY_FR16_REGNUM + 9},
187 {"fr26", CSKY_FR16_REGNUM + 10},
188 {"fr27", CSKY_FR16_REGNUM + 11},
189 {"fr28", CSKY_FR16_REGNUM + 12},
190 {"fr29", CSKY_FR16_REGNUM + 13},
191 {"fr30", CSKY_FR16_REGNUM + 14},
192 {"fr31", CSKY_FR16_REGNUM + 15},
193 /* vr0~vr15. */
194 {"vr0", CSKY_VR0_REGNUM + 0},
195 {"vr1", CSKY_VR0_REGNUM + 1},
196 {"vr2", CSKY_VR0_REGNUM + 2},
197 {"vr3", CSKY_VR0_REGNUM + 3},
198 {"vr4", CSKY_VR0_REGNUM + 4},
199 {"vr5", CSKY_VR0_REGNUM + 5},
200 {"vr6", CSKY_VR0_REGNUM + 6},
201 {"vr7", CSKY_VR0_REGNUM + 7},
202 {"vr8", CSKY_VR0_REGNUM + 8},
203 {"vr9", CSKY_VR0_REGNUM + 9},
204 {"vr10", CSKY_VR0_REGNUM + 10},
205 {"vr11", CSKY_VR0_REGNUM + 11},
206 {"vr12", CSKY_VR0_REGNUM + 12},
207 {"vr13", CSKY_VR0_REGNUM + 13},
208 {"vr14", CSKY_VR0_REGNUM + 14},
209 {"vr15", CSKY_VR0_REGNUM + 15},
210 /* fpu control registers. */
211 {"fcr", CSKY_FCR_REGNUM + 0},
212 {"fid", CSKY_FCR_REGNUM + 1},
213 {"fesr", CSKY_FCR_REGNUM + 2},
214 };
215
216 static const struct csky_supported_tdesc_register csky_supported_ar_regs[] = {
217 {"ar0", CSKY_AR0_REGNUM + 0},
218 {"ar1", CSKY_AR0_REGNUM + 1},
219 {"ar2", CSKY_AR0_REGNUM + 2},
220 {"ar3", CSKY_AR0_REGNUM + 3},
221 {"ar4", CSKY_AR0_REGNUM + 4},
222 {"ar5", CSKY_AR0_REGNUM + 5},
223 {"ar6", CSKY_AR0_REGNUM + 6},
224 {"ar7", CSKY_AR0_REGNUM + 7},
225 {"ar8", CSKY_AR0_REGNUM + 8},
226 {"ar9", CSKY_AR0_REGNUM + 9},
227 {"ar10", CSKY_AR0_REGNUM + 10},
228 {"ar11", CSKY_AR0_REGNUM + 11},
229 {"ar12", CSKY_AR0_REGNUM + 12},
230 {"ar13", CSKY_AR0_REGNUM + 13},
231 {"ar14", CSKY_AR0_REGNUM + 14},
232 {"ar15", CSKY_AR0_REGNUM + 15},
233 };
234
235 static const struct csky_supported_tdesc_register csky_supported_bank0_regs[] = {
236 {"cr0", CSKY_CR0_REGNUM + 0},
237 {"cr1", CSKY_CR0_REGNUM + 1},
238 {"cr2", CSKY_CR0_REGNUM + 2},
239 {"cr3", CSKY_CR0_REGNUM + 3},
240 {"cr4", CSKY_CR0_REGNUM + 4},
241 {"cr5", CSKY_CR0_REGNUM + 5},
242 {"cr6", CSKY_CR0_REGNUM + 6},
243 {"cr7", CSKY_CR0_REGNUM + 7},
244 {"cr8", CSKY_CR0_REGNUM + 8},
245 {"cr9", CSKY_CR0_REGNUM + 9},
246 {"cr10", CSKY_CR0_REGNUM + 10},
247 {"cr11", CSKY_CR0_REGNUM + 11},
248 {"cr12", CSKY_CR0_REGNUM + 12},
249 {"cr13", CSKY_CR0_REGNUM + 13},
250 {"cr14", CSKY_CR0_REGNUM + 14},
251 {"cr15", CSKY_CR0_REGNUM + 15},
252 {"cr16", CSKY_CR0_REGNUM + 16},
253 {"cr17", CSKY_CR0_REGNUM + 17},
254 {"cr18", CSKY_CR0_REGNUM + 18},
255 {"cr19", CSKY_CR0_REGNUM + 19},
256 {"cr20", CSKY_CR0_REGNUM + 20},
257 {"cr21", CSKY_CR0_REGNUM + 21},
258 {"cr22", CSKY_CR0_REGNUM + 22},
259 {"cr23", CSKY_CR0_REGNUM + 23},
260 {"cr24", CSKY_CR0_REGNUM + 24},
261 {"cr25", CSKY_CR0_REGNUM + 25},
262 {"cr26", CSKY_CR0_REGNUM + 26},
263 {"cr27", CSKY_CR0_REGNUM + 27},
264 {"cr28", CSKY_CR0_REGNUM + 28},
265 {"cr29", CSKY_CR0_REGNUM + 29},
266 {"cr30", CSKY_CR0_REGNUM + 30},
267 {"cr31", CSKY_CR0_REGNUM + 31}
268 };
269
270 static const struct csky_supported_tdesc_register csky_supported_mmu_regs[] = {
271 {"mcr0", 128},
272 {"mcr2", 129},
273 {"mcr3", 130},
274 {"mcr4", 131},
275 {"mcr6", 132},
276 {"mcr8", 133},
277 {"mcr29", 134},
278 {"mcr30", 135},
279 {"mcr31", 136}
280 };
281
282 static const struct csky_supported_tdesc_register csky_supported_bank15_regs[] = {
283 {"cp15cp1", 253},
284 {"cp15cp5", 254},
285 {"cp15cp7", 255},
286 {"cp15cp9", 256},
287 {"cp15cp10", 257},
288 {"cp15cp11", 258},
289 {"cp15cp12", 259},
290 {"cp15cp13", 260},
291 {"cp15cp14", 261},
292 {"cp15cp15", 262},
293 {"cp15cp16", 263},
294 {"cp15cp17", 264},
295 {"cp15cp18", 265},
296 {"cp15cp19", 266},
297 {"cp15cp20", 267},
298 {"cp15cp21", 268},
299 {"cp15cp22", 269},
300 {"cp15cp23", 270},
301 {"cp15cp24", 271},
302 {"cp15cp25", 272},
303 {"cp15cp26", 273},
304 {"cp15cp27", 274},
305 {"cp15cp28", 275},
306 };
307
308 static const struct csky_supported_tdesc_register csky_supported_alias_regs[] = {
309 /* Alias register names for Bank0. */
310 {"psr", CSKY_CR0_REGNUM + 0},
311 {"vbr", CSKY_CR0_REGNUM + 1},
312 {"epsr", CSKY_CR0_REGNUM + 2},
313 {"fpsr", CSKY_CR0_REGNUM + 3},
314 {"epc", CSKY_CR0_REGNUM + 4},
315 {"fpc", CSKY_CR0_REGNUM + 5},
316 {"ss0", CSKY_CR0_REGNUM + 6},
317 {"ss1", CSKY_CR0_REGNUM + 7},
318 {"ss2", CSKY_CR0_REGNUM + 8},
319 {"ss3", CSKY_CR0_REGNUM + 9},
320 {"ss4", CSKY_CR0_REGNUM + 10},
321 {"gcr", CSKY_CR0_REGNUM + 11},
322 {"gsr", CSKY_CR0_REGNUM + 12},
323 {"cpuid", CSKY_CR0_REGNUM + 13},
324 {"ccr", CSKY_CR0_REGNUM + 18},
325 {"capr", CSKY_CR0_REGNUM + 19},
326 {"pacr", CSKY_CR0_REGNUM + 20},
327 {"prsr", CSKY_CR0_REGNUM + 21},
328 {"chr", CSKY_CR0_REGNUM + 31},
329 /* Alias register names for MMU. */
330 {"mir", 128},
331 {"mel0", 129},
332 {"mel1", 130},
333 {"meh", 131},
334 {"mpr", 132},
335 {"mcir", 133},
336 {"mpgd", 134},
337 {"msa0", 135},
338 {"msa1", 136},
339 /* Alias register names for Bank1. */
340 {"ebr", 190},
341 {"errlc", 195},
342 {"erraddr", 196},
343 {"errsts", 197},
344 {"errinj", 198},
345 {"usp", 203},
346 {"int_sp", 204},
347 {"itcmcr", 211},
348 {"dtcmcr", 212},
349 {"cindex", 215},
350 {"cdata0", 216},
351 {"cdata1", 217},
352 {"cdata2", 218},
353 {"cins", 220},
354 /* Alias register names for Bank3. */
355 {"sepsr", 221},
356 {"t_wssr", 221},
357 {"sevbr", 222},
358 {"t_wrcr", 222},
359 {"seepsr", 223},
360 {"seepc", 225},
361 {"nsssp", 227},
362 {"t_usp", 228},
363 {"dcr", 229},
364 {"t_pcr", 230},
365 };
366
367 /* Functions declaration. */
368
369 static const char *
370 csky_pseudo_register_name (struct gdbarch *gdbarch, int regno);
371
372 /* Get csky supported registers's count for tdesc xml. */
373
374 static int
375 csky_get_supported_tdesc_registers_count()
376 {
377 int count = 0;
378 count += ARRAY_SIZE (csky_supported_gpr_regs);
379 count += ARRAY_SIZE (csky_supported_fpu_regs);
380 count += ARRAY_SIZE (csky_supported_ar_regs);
381 count += ARRAY_SIZE (csky_supported_bank0_regs);
382 count += ARRAY_SIZE (csky_supported_mmu_regs);
383 count += ARRAY_SIZE (csky_supported_bank15_regs);
384 count += ARRAY_SIZE (csky_supported_alias_regs);
385 /* Bank1~Bank14, Bank16~Bank31. */
386 count += 32 * (14 + 16);
387 return count;
388 }
389
390 /* Return a supported register according to index. */
391
392 static const struct csky_supported_tdesc_register *
393 csky_get_supported_register_by_index (int index)
394 {
395 static struct csky_supported_tdesc_register tdesc_reg;
396 int count = 0;
397 int multi, remain;
398 int count_gpr = ARRAY_SIZE (csky_supported_gpr_regs);
399 int count_fpu = ARRAY_SIZE (csky_supported_fpu_regs);
400 int count_ar = ARRAY_SIZE (csky_supported_ar_regs);
401 int count_bank0 = ARRAY_SIZE (csky_supported_bank0_regs);
402 int count_mmu = ARRAY_SIZE (csky_supported_mmu_regs);
403 int count_bank15 = ARRAY_SIZE (csky_supported_bank15_regs);
404 int count_alias = ARRAY_SIZE (csky_supported_alias_regs);
405
406 count = count_gpr;
407 if (index < count)
408 return &csky_supported_gpr_regs[index];
409 if (index < (count + count_fpu))
410 return &csky_supported_fpu_regs[index - count];
411 count += count_fpu;
412 if (index < (count + count_ar))
413 return &csky_supported_ar_regs[index - count];
414 count += count_ar;
415 if (index < (count + count_bank0))
416 return &csky_supported_bank0_regs[index - count];
417 count += count_bank0;
418 if (index < (count + count_mmu))
419 return &csky_supported_mmu_regs[index - count];
420 count += count_mmu;
421 if (index < (count + count_bank15))
422 return &csky_supported_bank15_regs[index - count];
423 count += count_bank15;
424 if (index < (count + count_alias))
425 return &csky_supported_alias_regs[index - count];
426 count += count_alias;
427 index -= count;
428 multi = index / 32;
429 remain = index % 32;
430 switch (multi)
431 {
432 case 0: /* Bank1. */
433 {
434 sprintf (tdesc_reg.name, "cp1cr%d", remain);
435 tdesc_reg.num = 189 + remain;
436 }
437 break;
438 case 1: /* Bank2. */
439 {
440 sprintf (tdesc_reg.name, "cp2cr%d", remain);
441 tdesc_reg.num = 276 + remain;
442 }
443 break;
444 case 2: /* Bank3. */
445 {
446 sprintf (tdesc_reg.name, "cp3cr%d", remain);
447 tdesc_reg.num = 221 + remain;
448 }
449 break;
450 case 3: /* Bank4. */
451 case 4: /* Bank5. */
452 case 5: /* Bank6. */
453 case 6: /* Bank7. */
454 case 7: /* Bank8. */
455 case 8: /* Bank9. */
456 case 9: /* Bank10. */
457 case 10: /* Bank11. */
458 case 11: /* Bank12. */
459 case 12: /* Bank13. */
460 case 13: /* Bank14. */
461 {
462 /* Regitsers in Bank4~14 have continuous regno with start 308. */
463 sprintf (tdesc_reg.name, "cp%dcr%d", (multi + 1), remain);
464 tdesc_reg.num = 308 + ((multi - 3) * 32) + remain;
465 }
466 break;
467 case 14: /* Bank16. */
468 case 15: /* Bank17. */
469 case 16: /* Bank18. */
470 case 17: /* Bank19. */
471 case 18: /* Bank20. */
472 case 19: /* Bank21. */
473 case 20: /* Bank22. */
474 case 21: /* Bank23. */
475 case 22: /* Bank24. */
476 case 23: /* Bank25. */
477 case 24: /* Bank26. */
478 case 25: /* Bank27. */
479 case 26: /* Bank28. */
480 case 27: /* Bank29. */
481 case 28: /* Bank30. */
482 case 29: /* Bank31. */
483 {
484 /* Regitsers in Bank16~31 have continuous regno with start 660. */
485 sprintf (tdesc_reg.name, "cp%dcr%d", (multi + 2), remain);
486 tdesc_reg.num = 660 + ((multi - 14) * 32) + remain;
487 }
488 break;
489 default:
490 return NULL;
491 }
492 return &tdesc_reg;
493 }
494
495 /* Convenience function to print debug messages in prologue analysis. */
496
497 static void
498 print_savedreg_msg (int regno, int offsets[], bool print_continuing)
499 {
500 gdb_printf (gdb_stdlog, "csky: r%d saved at offset 0x%x\n",
501 regno, offsets[regno]);
502 if (print_continuing)
503 gdb_printf (gdb_stdlog, "csky: continuing\n");
504 }
505
506 /* Check whether the instruction at ADDR is 16-bit or not. */
507
508 static int
509 csky_pc_is_csky16 (struct gdbarch *gdbarch, CORE_ADDR addr)
510 {
511 gdb_byte target_mem[2];
512 int status;
513 unsigned int insn;
514 int ret = 1;
515 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
516
517 status = target_read_memory (addr, target_mem, 2);
518 /* Assume a 16-bit instruction if we can't read memory. */
519 if (status)
520 return 1;
521
522 /* Get instruction from memory. */
523 insn = extract_unsigned_integer (target_mem, 2, byte_order);
524 if ((insn & CSKY_32_INSN_MASK) == CSKY_32_INSN_MASK)
525 ret = 0;
526 else if (insn == CSKY_BKPT_INSN)
527 {
528 /* Check for 32-bit bkpt instruction which is all 0. */
529 status = target_read_memory (addr + 2, target_mem, 2);
530 if (status)
531 return 1;
532
533 insn = extract_unsigned_integer (target_mem, 2, byte_order);
534 if (insn == CSKY_BKPT_INSN)
535 ret = 0;
536 }
537 return ret;
538 }
539
540 /* Get one instruction at ADDR and store it in INSN. Return 2 for
541 a 16-bit instruction or 4 for a 32-bit instruction. */
542
543 static int
544 csky_get_insn (struct gdbarch *gdbarch, CORE_ADDR addr, unsigned int *insn)
545 {
546 gdb_byte target_mem[2];
547 unsigned int insn_type;
548 int status;
549 int insn_len = 2;
550 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
551
552 status = target_read_memory (addr, target_mem, 2);
553 if (status)
554 memory_error (TARGET_XFER_E_IO, addr);
555
556 insn_type = extract_unsigned_integer (target_mem, 2, byte_order);
557 if (CSKY_32_INSN_MASK == (insn_type & CSKY_32_INSN_MASK))
558 {
559 status = target_read_memory (addr + 2, target_mem, 2);
560 if (status)
561 memory_error (TARGET_XFER_E_IO, addr);
562 insn_type = ((insn_type << 16)
563 | extract_unsigned_integer (target_mem, 2, byte_order));
564 insn_len = 4;
565 }
566 *insn = insn_type;
567 return insn_len;
568 }
569
570 /* Implement the read_pc gdbarch method. */
571
572 static CORE_ADDR
573 csky_read_pc (readable_regcache *regcache)
574 {
575 ULONGEST pc;
576 regcache->cooked_read (CSKY_PC_REGNUM, &pc);
577 return pc;
578 }
579
580 /* Implement the write_pc gdbarch method. */
581
582 static void
583 csky_write_pc (regcache *regcache, CORE_ADDR val)
584 {
585 regcache_cooked_write_unsigned (regcache, CSKY_PC_REGNUM, val);
586 }
587
588 /* C-Sky ABI register names. */
589
590 static const char * const csky_register_names[] =
591 {
592 /* General registers 0 - 31. */
593 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
594 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
595 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
596 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
597
598 /* DSP hilo registers 36 and 37. */
599 "", "", "", "", "hi", "lo", "", "",
600
601 /* FPU/VPU general registers 40 - 71. */
602 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
603 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
604 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
605 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
606
607 /* Program counter 72. */
608 "pc",
609
610 /* Optional registers (ar) 73 - 88. */
611 "ar0", "ar1", "ar2", "ar3", "ar4", "ar5", "ar6", "ar7",
612 "ar8", "ar9", "ar10", "ar11", "ar12", "ar13", "ar14", "ar15",
613
614 /* Control registers (cr) 89 - 119. */
615 "psr", "vbr", "epsr", "fpsr", "epc", "fpc", "ss0", "ss1",
616 "ss2", "ss3", "ss4", "gcr", "gsr", "cr13", "cr14", "cr15",
617 "cr16", "cr17", "cr18", "cr19", "cr20", "cr21", "cr22", "cr23",
618 "cr24", "cr25", "cr26", "cr27", "cr28", "cr29", "cr30", "cr31",
619
620 /* FPU/VPU control registers 121 ~ 123. */
621 /* User sp 127. */
622 "fid", "fcr", "fesr", "", "", "", "usp",
623
624 /* MMU control registers: 128 - 136. */
625 "mcr0", "mcr2", "mcr3", "mcr4", "mcr6", "mcr8", "mcr29", "mcr30",
626 "mcr31", "", "", "",
627
628 /* Profiling control registers 140 - 143. */
629 /* Profiling software general registers 144 - 157. */
630 "profcr0", "profcr1", "profcr2", "profcr3", "profsgr0", "profsgr1",
631 "profsgr2", "profsgr3", "profsgr4", "profsgr5", "profsgr6", "profsgr7",
632 "profsgr8", "profsgr9", "profsgr10","profsgr11","profsgr12", "profsgr13",
633 "", "",
634
635 /* Profiling architecture general registers 160 - 174. */
636 "profagr0", "profagr1", "profagr2", "profagr3", "profagr4", "profagr5",
637 "profagr6", "profagr7", "profagr8", "profagr9", "profagr10","profagr11",
638 "profagr12","profagr13","profagr14", "",
639
640 /* Profiling extension general registers 176 - 188. */
641 "profxgr0", "profxgr1", "profxgr2", "profxgr3", "profxgr4", "profxgr5",
642 "profxgr6", "profxgr7", "profxgr8", "profxgr9", "profxgr10","profxgr11",
643 "profxgr12",
644
645 /* Control registers in bank1. */
646 "", "", "", "", "", "", "", "",
647 "", "", "", "", "", "", "", "",
648 "cp1cr16", "cp1cr17", "cp1cr18", "cp1cr19", "cp1cr20", "", "", "",
649 "", "", "", "", "", "", "", "",
650
651 /* Control registers in bank3 (ICE). */
652 "sepsr", "sevbr", "seepsr", "", "seepc", "", "nsssp", "seusp",
653 "sedcr", "", "", "", "", "", "", "",
654 "", "", "", "", "", "", "", "",
655 "", "", "", "", "", "", "", ""
656 };
657
658 /* Implement the register_name gdbarch method. */
659
660 static const char *
661 csky_register_name (struct gdbarch *gdbarch, int reg_nr)
662 {
663 if (reg_nr >= gdbarch_num_regs (gdbarch))
664 return csky_pseudo_register_name (gdbarch, reg_nr);
665
666 if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
667 return tdesc_register_name (gdbarch, reg_nr);
668
669 return csky_register_names[reg_nr];
670 }
671
672 /* Construct vector type for vrx registers. */
673
674 static struct type *
675 csky_vector_type (struct gdbarch *gdbarch)
676 {
677 const struct builtin_type *bt = builtin_type (gdbarch);
678
679 struct type *t;
680
681 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vec128i",
682 TYPE_CODE_UNION);
683
684 append_composite_type_field (t, "u32",
685 init_vector_type (bt->builtin_int32, 4));
686 append_composite_type_field (t, "u16",
687 init_vector_type (bt->builtin_int16, 8));
688 append_composite_type_field (t, "u8",
689 init_vector_type (bt->builtin_int8, 16));
690
691 t->set_is_vector (true);
692 t->set_name ("builtin_type_vec128i");
693
694 return t;
695 }
696
697 /* Return the GDB type object for the "standard" data type
698 of data in register N. */
699
700 static struct type *
701 csky_register_type (struct gdbarch *gdbarch, int reg_nr)
702 {
703 int num_regs = gdbarch_num_regs (gdbarch);
704 csky_gdbarch_tdep *tdep
705 = gdbarch_tdep<csky_gdbarch_tdep> (gdbarch);
706
707 if (tdep->fv_pseudo_registers_count)
708 {
709 if ((reg_nr >= num_regs)
710 && (reg_nr < (num_regs + tdep->fv_pseudo_registers_count)))
711 return builtin_type (gdbarch)->builtin_int32;
712 }
713
714 /* Vector register has 128 bits, and only in ck810. Just return
715 csky_vector_type(), not check tdesc_has_registers(), is in case
716 of some GDB stub does not describe type for Vector registers
717 in the target-description-xml. */
718 if ((reg_nr >= CSKY_VR0_REGNUM) && (reg_nr <= CSKY_VR0_REGNUM + 15))
719 return csky_vector_type (gdbarch);
720
721 /* If type has been described in tdesc-xml, use it. */
722 if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
723 {
724 struct type *tdesc_t = tdesc_register_type (gdbarch, reg_nr);
725 if (tdesc_t)
726 return tdesc_t;
727 }
728
729 /* PC, EPC, FPC is a text pointer. */
730 if ((reg_nr == CSKY_PC_REGNUM) || (reg_nr == CSKY_EPC_REGNUM)
731 || (reg_nr == CSKY_FPC_REGNUM))
732 return builtin_type (gdbarch)->builtin_func_ptr;
733
734 /* VBR is a data pointer. */
735 if (reg_nr == CSKY_VBR_REGNUM)
736 return builtin_type (gdbarch)->builtin_data_ptr;
737
738 /* Float register has 64 bits, and only in ck810. */
739 if ((reg_nr >=CSKY_FR0_REGNUM) && (reg_nr <= CSKY_FR0_REGNUM + 15))
740 {
741 type_allocator alloc (gdbarch);
742 return init_float_type (alloc, 64, "builtin_type_csky_ext",
743 floatformats_ieee_double);
744 }
745
746 /* Profiling general register has 48 bits, we use 64bit. */
747 if ((reg_nr >= CSKY_PROFGR_REGNUM) && (reg_nr <= CSKY_PROFGR_REGNUM + 44))
748 return builtin_type (gdbarch)->builtin_uint64;
749
750 if (reg_nr == CSKY_SP_REGNUM)
751 return builtin_type (gdbarch)->builtin_data_ptr;
752
753 /* Others are 32 bits. */
754 return builtin_type (gdbarch)->builtin_int32;
755 }
756
757 /* Data structure to marshall items in a dummy stack frame when
758 calling a function in the inferior. */
759
760 struct csky_stack_item
761 {
762 csky_stack_item (int len_, const gdb_byte *data_)
763 : len (len_), data (data_)
764 {}
765
766 int len;
767 const gdb_byte *data;
768 };
769
770 /* Implement the push_dummy_call gdbarch method. */
771
772 static CORE_ADDR
773 csky_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
774 struct regcache *regcache, CORE_ADDR bp_addr,
775 int nargs, struct value **args, CORE_ADDR sp,
776 function_call_return_method return_method,
777 CORE_ADDR struct_addr)
778 {
779 int argnum;
780 int argreg = CSKY_ABI_A0_REGNUM;
781 int last_arg_regnum = CSKY_ABI_LAST_ARG_REGNUM;
782 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
783 std::vector<csky_stack_item> stack_items;
784
785 /* Set the return address. For CSKY, the return breakpoint is
786 always at BP_ADDR. */
787 regcache_cooked_write_unsigned (regcache, CSKY_LR_REGNUM, bp_addr);
788
789 /* The struct_return pointer occupies the first parameter
790 passing register. */
791 if (return_method == return_method_struct)
792 {
793 if (csky_debug)
794 {
795 gdb_printf (gdb_stdlog,
796 "csky: struct return in %s = %s\n",
797 gdbarch_register_name (gdbarch, argreg),
798 paddress (gdbarch, struct_addr));
799 }
800 regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
801 argreg++;
802 }
803
804 /* Put parameters into argument registers in REGCACHE.
805 In ABI argument registers are r0 through r3. */
806 for (argnum = 0; argnum < nargs; argnum++)
807 {
808 int len;
809 struct type *arg_type;
810 const gdb_byte *val;
811
812 arg_type = check_typedef (args[argnum]->type ());
813 len = arg_type->length ();
814 val = args[argnum]->contents ().data ();
815
816 /* Copy the argument to argument registers or the dummy stack.
817 Large arguments are split between registers and stack.
818
819 If len < 4, there is no need to worry about endianness since
820 the arguments will always be stored in the low address. */
821 if (len < 4)
822 {
823 CORE_ADDR regval
824 = extract_unsigned_integer (val, len, byte_order);
825 regcache_cooked_write_unsigned (regcache, argreg, regval);
826 argreg++;
827 }
828 else
829 {
830 while (len > 0)
831 {
832 int partial_len = len < 4 ? len : 4;
833 if (argreg <= last_arg_regnum)
834 {
835 /* The argument is passed in an argument register. */
836 CORE_ADDR regval
837 = extract_unsigned_integer (val, partial_len,
838 byte_order);
839 if (byte_order == BFD_ENDIAN_BIG)
840 regval <<= (4 - partial_len) * 8;
841
842 /* Put regval into register in REGCACHE. */
843 regcache_cooked_write_unsigned (regcache, argreg,
844 regval);
845 argreg++;
846 }
847 else
848 {
849 /* The argument should be pushed onto the dummy stack. */
850 stack_items.emplace_back (4, val);
851 }
852 len -= partial_len;
853 val += partial_len;
854 }
855 }
856 }
857
858 /* Transfer the dummy stack frame to the target. */
859 std::vector<csky_stack_item>::reverse_iterator iter;
860 for (iter = stack_items.rbegin (); iter != stack_items.rend (); ++iter)
861 {
862 sp -= iter->len;
863 write_memory (sp, iter->data, iter->len);
864 }
865
866 /* Finally, update the SP register. */
867 regcache_cooked_write_unsigned (regcache, CSKY_SP_REGNUM, sp);
868 return sp;
869 }
870
871 /* Implement the return_value gdbarch method. */
872
873 static enum return_value_convention
874 csky_return_value (struct gdbarch *gdbarch, struct value *function,
875 struct type *valtype, struct regcache *regcache,
876 gdb_byte *readbuf, const gdb_byte *writebuf)
877 {
878 CORE_ADDR regval;
879 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
880 int len = valtype->length ();
881 unsigned int ret_regnum = CSKY_RET_REGNUM;
882
883 /* Csky abi specifies that return values larger than 8 bytes
884 are put on the stack. */
885 if (len > 8)
886 return RETURN_VALUE_STRUCT_CONVENTION;
887 else
888 {
889 if (readbuf != NULL)
890 {
891 ULONGEST tmp;
892 /* By using store_unsigned_integer we avoid having to do
893 anything special for small big-endian values. */
894 regcache->cooked_read (ret_regnum, &tmp);
895 store_unsigned_integer (readbuf, (len > 4 ? 4 : len),
896 byte_order, tmp);
897 if (len > 4)
898 {
899 regcache->cooked_read (ret_regnum + 1, &tmp);
900 store_unsigned_integer (readbuf + 4, 4, byte_order, tmp);
901 }
902 }
903 if (writebuf != NULL)
904 {
905 regval = extract_unsigned_integer (writebuf, len > 4 ? 4 : len,
906 byte_order);
907 regcache_cooked_write_unsigned (regcache, ret_regnum, regval);
908 if (len > 4)
909 {
910 regval = extract_unsigned_integer ((gdb_byte *) writebuf + 4,
911 4, byte_order);
912 regcache_cooked_write_unsigned (regcache, ret_regnum + 1,
913 regval);
914 }
915
916 }
917 return RETURN_VALUE_REGISTER_CONVENTION;
918 }
919 }
920
921 /* Implement the frame_align gdbarch method.
922
923 Adjust the address downward (direction of stack growth) so that it
924 is correctly aligned for a new stack frame. */
925
926 static CORE_ADDR
927 csky_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
928 {
929 return align_down (addr, 4);
930 }
931
932 /* Unwind cache used for gdbarch fallback unwinder. */
933
934 struct csky_unwind_cache
935 {
936 /* The stack pointer at the time this frame was created; i.e. the
937 caller's stack pointer when this function was called. It is used
938 to identify this frame. */
939 CORE_ADDR prev_sp;
940
941 /* The frame base for this frame is just prev_sp - frame size.
942 FRAMESIZE is the distance from the frame pointer to the
943 initial stack pointer. */
944 int framesize;
945
946 /* The register used to hold the frame pointer for this frame. */
947 int framereg;
948
949 /* Saved register offsets. */
950 trad_frame_saved_reg *saved_regs;
951 };
952
953 /* Do prologue analysis, returning the PC of the first instruction
954 after the function prologue. */
955
956 static CORE_ADDR
957 csky_analyze_prologue (struct gdbarch *gdbarch,
958 CORE_ADDR start_pc,
959 CORE_ADDR limit_pc,
960 CORE_ADDR end_pc,
961 const frame_info_ptr &this_frame,
962 struct csky_unwind_cache *this_cache,
963 lr_type_t lr_type)
964 {
965 CORE_ADDR addr;
966 unsigned int insn, rn;
967 int framesize = 0;
968 int stacksize = 0;
969 int register_offsets[CSKY_NUM_GREGS_SAVED_GREGS];
970 int insn_len;
971 /* For adjusting fp. */
972 int is_fp_saved = 0;
973 int adjust_fp = 0;
974
975 /* REGISTER_OFFSETS will contain offsets from the top of the frame
976 (NOT the frame pointer) for the various saved registers, or -1
977 if the register is not saved. */
978 for (rn = 0; rn < CSKY_NUM_GREGS_SAVED_GREGS; rn++)
979 register_offsets[rn] = -1;
980
981 /* Analyze the prologue. Things we determine from analyzing the
982 prologue include the size of the frame and which registers are
983 saved (and where). */
984 if (csky_debug)
985 {
986 gdb_printf (gdb_stdlog,
987 "csky: Scanning prologue: start_pc = 0x%x,"
988 "limit_pc = 0x%x\n", (unsigned int) start_pc,
989 (unsigned int) limit_pc);
990 }
991
992 /* Default to 16 bit instruction. */
993 insn_len = 2;
994 stacksize = 0;
995 for (addr = start_pc; addr < limit_pc; addr += insn_len)
996 {
997 /* Get next insn. */
998 insn_len = csky_get_insn (gdbarch, addr, &insn);
999
1000 /* Check if 32 bit. */
1001 if (insn_len == 4)
1002 {
1003 /* subi32 sp,sp oimm12. */
1004 if (CSKY_32_IS_SUBI0 (insn))
1005 {
1006 /* Got oimm12. */
1007 int offset = CSKY_32_SUBI_IMM (insn);
1008 if (csky_debug)
1009 {
1010 gdb_printf (gdb_stdlog,
1011 "csky: got subi sp,%d; continuing\n",
1012 offset);
1013 }
1014 stacksize += offset;
1015 continue;
1016 }
1017 /* stm32 ry-rz,(sp). */
1018 else if (CSKY_32_IS_STMx0 (insn))
1019 {
1020 /* Spill register(s). */
1021 int start_register;
1022 int reg_count;
1023 int offset;
1024
1025 /* BIG WARNING! The CKCore ABI does not restrict functions
1026 to taking only one stack allocation. Therefore, when
1027 we save a register, we record the offset of where it was
1028 saved relative to the current stacksize. This will
1029 then give an offset from the SP upon entry to our
1030 function. Remember, stacksize is NOT constant until
1031 we're done scanning the prologue. */
1032 start_register = CSKY_32_STM_VAL_REGNUM (insn);
1033 reg_count = CSKY_32_STM_SIZE (insn);
1034 if (csky_debug)
1035 {
1036 gdb_printf (gdb_stdlog,
1037 "csky: got stm r%d-r%d,(sp)\n",
1038 start_register,
1039 start_register + reg_count);
1040 }
1041
1042 for (rn = start_register, offset = 0;
1043 rn <= start_register + reg_count;
1044 rn++, offset += 4)
1045 {
1046 register_offsets[rn] = stacksize - offset;
1047 if (csky_debug)
1048 {
1049 gdb_printf (gdb_stdlog,
1050 "csky: r%d saved at 0x%x"
1051 " (offset %d)\n",
1052 rn, register_offsets[rn],
1053 offset);
1054 }
1055 }
1056 if (csky_debug)
1057 gdb_printf (gdb_stdlog, "csky: continuing\n");
1058 continue;
1059 }
1060 /* stw ry,(sp,disp). */
1061 else if (CSKY_32_IS_STWx0 (insn))
1062 {
1063 /* Spill register: see note for IS_STM above. */
1064 int disp;
1065
1066 rn = CSKY_32_ST_VAL_REGNUM (insn);
1067 disp = CSKY_32_ST_OFFSET (insn);
1068 register_offsets[rn] = stacksize - disp;
1069 if (csky_debug)
1070 print_savedreg_msg (rn, register_offsets, true);
1071 continue;
1072 }
1073 else if (CSKY_32_IS_MOV_FP_SP (insn))
1074 {
1075 /* SP is saved to FP reg, means code afer prologue may
1076 modify SP. */
1077 is_fp_saved = 1;
1078 adjust_fp = stacksize;
1079 continue;
1080 }
1081 else if (CSKY_32_IS_MFCR_EPSR (insn))
1082 {
1083 unsigned int insn2;
1084 addr += 4;
1085 int mfcr_regnum = insn & 0x1f;
1086 insn_len = csky_get_insn (gdbarch, addr, &insn2);
1087 if (insn_len == 2)
1088 {
1089 int stw_regnum = (insn2 >> 5) & 0x7;
1090 if (CSKY_16_IS_STWx0 (insn2) && (mfcr_regnum == stw_regnum))
1091 {
1092 int offset;
1093
1094 /* CSKY_EPSR_REGNUM. */
1095 rn = CSKY_NUM_GREGS;
1096 offset = CSKY_16_STWx0_OFFSET (insn2);
1097 register_offsets[rn] = stacksize - offset;
1098 if (csky_debug)
1099 print_savedreg_msg (rn, register_offsets, true);
1100 continue;
1101 }
1102 break;
1103 }
1104 else
1105 {
1106 /* INSN_LEN == 4. */
1107 int stw_regnum = (insn2 >> 21) & 0x1f;
1108 if (CSKY_32_IS_STWx0 (insn2) && (mfcr_regnum == stw_regnum))
1109 {
1110 int offset;
1111
1112 /* CSKY_EPSR_REGNUM. */
1113 rn = CSKY_NUM_GREGS;
1114 offset = CSKY_32_ST_OFFSET (insn2);
1115 register_offsets[rn] = framesize - offset;
1116 if (csky_debug)
1117 print_savedreg_msg (rn, register_offsets, true);
1118 continue;
1119 }
1120 break;
1121 }
1122 }
1123 else if (CSKY_32_IS_MFCR_FPSR (insn))
1124 {
1125 unsigned int insn2;
1126 addr += 4;
1127 int mfcr_regnum = insn & 0x1f;
1128 insn_len = csky_get_insn (gdbarch, addr, &insn2);
1129 if (insn_len == 2)
1130 {
1131 int stw_regnum = (insn2 >> 5) & 0x7;
1132 if (CSKY_16_IS_STWx0 (insn2) && (mfcr_regnum
1133 == stw_regnum))
1134 {
1135 int offset;
1136
1137 /* CSKY_FPSR_REGNUM. */
1138 rn = CSKY_NUM_GREGS + 1;
1139 offset = CSKY_16_STWx0_OFFSET (insn2);
1140 register_offsets[rn] = stacksize - offset;
1141 if (csky_debug)
1142 print_savedreg_msg (rn, register_offsets, true);
1143 continue;
1144 }
1145 break;
1146 }
1147 else
1148 {
1149 /* INSN_LEN == 4. */
1150 int stw_regnum = (insn2 >> 21) & 0x1f;
1151 if (CSKY_32_IS_STWx0 (insn2) && (mfcr_regnum == stw_regnum))
1152 {
1153 int offset;
1154
1155 /* CSKY_FPSR_REGNUM. */
1156 rn = CSKY_NUM_GREGS + 1;
1157 offset = CSKY_32_ST_OFFSET (insn2);
1158 register_offsets[rn] = framesize - offset;
1159 if (csky_debug)
1160 print_savedreg_msg (rn, register_offsets, true);
1161 continue;
1162 }
1163 break;
1164 }
1165 }
1166 else if (CSKY_32_IS_MFCR_EPC (insn))
1167 {
1168 unsigned int insn2;
1169 addr += 4;
1170 int mfcr_regnum = insn & 0x1f;
1171 insn_len = csky_get_insn (gdbarch, addr, &insn2);
1172 if (insn_len == 2)
1173 {
1174 int stw_regnum = (insn2 >> 5) & 0x7;
1175 if (CSKY_16_IS_STWx0 (insn2) && (mfcr_regnum == stw_regnum))
1176 {
1177 int offset;
1178
1179 /* CSKY_EPC_REGNUM. */
1180 rn = CSKY_NUM_GREGS + 2;
1181 offset = CSKY_16_STWx0_OFFSET (insn2);
1182 register_offsets[rn] = stacksize - offset;
1183 if (csky_debug)
1184 print_savedreg_msg (rn, register_offsets, true);
1185 continue;
1186 }
1187 break;
1188 }
1189 else
1190 {
1191 /* INSN_LEN == 4. */
1192 int stw_regnum = (insn2 >> 21) & 0x1f;
1193 if (CSKY_32_IS_STWx0 (insn2) && (mfcr_regnum == stw_regnum))
1194 {
1195 int offset;
1196
1197 /* CSKY_EPC_REGNUM. */
1198 rn = CSKY_NUM_GREGS + 2;
1199 offset = CSKY_32_ST_OFFSET (insn2);
1200 register_offsets[rn] = framesize - offset;
1201 if (csky_debug)
1202 print_savedreg_msg (rn, register_offsets, true);
1203 continue;
1204 }
1205 break;
1206 }
1207 }
1208 else if (CSKY_32_IS_MFCR_FPC (insn))
1209 {
1210 unsigned int insn2;
1211 addr += 4;
1212 int mfcr_regnum = insn & 0x1f;
1213 insn_len = csky_get_insn (gdbarch, addr, &insn2);
1214 if (insn_len == 2)
1215 {
1216 int stw_regnum = (insn2 >> 5) & 0x7;
1217 if (CSKY_16_IS_STWx0 (insn2) && (mfcr_regnum == stw_regnum))
1218 {
1219 int offset;
1220
1221 /* CSKY_FPC_REGNUM. */
1222 rn = CSKY_NUM_GREGS + 3;
1223 offset = CSKY_16_STWx0_OFFSET (insn2);
1224 register_offsets[rn] = stacksize - offset;
1225 if (csky_debug)
1226 print_savedreg_msg (rn, register_offsets, true);
1227 continue;
1228 }
1229 break;
1230 }
1231 else
1232 {
1233 /* INSN_LEN == 4. */
1234 int stw_regnum = (insn2 >> 21) & 0x1f;
1235 if (CSKY_32_IS_STWx0 (insn2) && (mfcr_regnum == stw_regnum))
1236 {
1237 int offset;
1238
1239 /* CSKY_FPC_REGNUM. */
1240 rn = CSKY_NUM_GREGS + 3;
1241 offset = CSKY_32_ST_OFFSET (insn2);
1242 register_offsets[rn] = framesize - offset;
1243 if (csky_debug)
1244 print_savedreg_msg (rn, register_offsets, true);
1245 continue;
1246 }
1247 break;
1248 }
1249 }
1250 else if (CSKY_32_IS_PUSH (insn))
1251 {
1252 /* Push for 32_bit. */
1253 if (CSKY_32_IS_PUSH_R29 (insn))
1254 {
1255 stacksize += 4;
1256 register_offsets[29] = stacksize;
1257 if (csky_debug)
1258 print_savedreg_msg (29, register_offsets, false);
1259 }
1260 if (CSKY_32_PUSH_LIST2 (insn))
1261 {
1262 int num = CSKY_32_PUSH_LIST2 (insn);
1263 int tmp = 0;
1264 stacksize += num * 4;
1265 if (csky_debug)
1266 {
1267 gdb_printf (gdb_stdlog,
1268 "csky: push regs_array: r16-r%d\n",
1269 16 + num - 1);
1270 }
1271 for (rn = 16; rn <= 16 + num - 1; rn++)
1272 {
1273 register_offsets[rn] = stacksize - tmp;
1274 if (csky_debug)
1275 {
1276 gdb_printf (gdb_stdlog,
1277 "csky: r%d saved at 0x%x"
1278 " (offset %d)\n", rn,
1279 register_offsets[rn], tmp);
1280 }
1281 tmp += 4;
1282 }
1283 }
1284 if (CSKY_32_IS_PUSH_R15 (insn))
1285 {
1286 stacksize += 4;
1287 register_offsets[15] = stacksize;
1288 if (csky_debug)
1289 print_savedreg_msg (15, register_offsets, false);
1290 }
1291 if (CSKY_32_PUSH_LIST1 (insn))
1292 {
1293 int num = CSKY_32_PUSH_LIST1 (insn);
1294 int tmp = 0;
1295 stacksize += num * 4;
1296 if (csky_debug)
1297 {
1298 gdb_printf (gdb_stdlog,
1299 "csky: push regs_array: r4-r%d\n",
1300 4 + num - 1);
1301 }
1302 for (rn = 4; rn <= 4 + num - 1; rn++)
1303 {
1304 register_offsets[rn] = stacksize - tmp;
1305 if (csky_debug)
1306 {
1307 gdb_printf (gdb_stdlog,
1308 "csky: r%d saved at 0x%x"
1309 " (offset %d)\n", rn,
1310 register_offsets[rn], tmp);
1311 }
1312 tmp += 4;
1313 }
1314 }
1315
1316 framesize = stacksize;
1317 if (csky_debug)
1318 gdb_printf (gdb_stdlog, "csky: continuing\n");
1319 continue;
1320 }
1321 else if (CSKY_32_IS_LRW4 (insn) || CSKY_32_IS_MOVI4 (insn)
1322 || CSKY_32_IS_MOVIH4 (insn) || CSKY_32_IS_BMASKI4 (insn))
1323 {
1324 int adjust = 0;
1325 int offset = 0;
1326 unsigned int insn2;
1327
1328 if (csky_debug)
1329 {
1330 gdb_printf (gdb_stdlog,
1331 "csky: looking at large frame\n");
1332 }
1333 if (CSKY_32_IS_LRW4 (insn))
1334 {
1335 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1336 int literal_addr = (addr + ((insn & 0xffff) << 2))
1337 & 0xfffffffc;
1338 adjust = read_memory_unsigned_integer (literal_addr, 4,
1339 byte_order);
1340 }
1341 else if (CSKY_32_IS_MOVI4 (insn))
1342 adjust = (insn & 0xffff);
1343 else if (CSKY_32_IS_MOVIH4 (insn))
1344 adjust = (insn & 0xffff) << 16;
1345 else
1346 {
1347 /* CSKY_32_IS_BMASKI4 (insn). */
1348 adjust = (1 << (((insn & 0x3e00000) >> 21) + 1)) - 1;
1349 }
1350
1351 if (csky_debug)
1352 {
1353 gdb_printf (gdb_stdlog,
1354 "csky: base stacksize=0x%x\n", adjust);
1355
1356 /* May have zero or more insns which modify r4. */
1357 gdb_printf (gdb_stdlog,
1358 "csky: looking for r4 adjusters...\n");
1359 }
1360
1361 offset = 4;
1362 insn_len = csky_get_insn (gdbarch, addr + offset, &insn2);
1363 while (CSKY_IS_R4_ADJUSTER (insn2))
1364 {
1365 if (CSKY_32_IS_ADDI4 (insn2))
1366 {
1367 int imm = (insn2 & 0xfff) + 1;
1368 adjust += imm;
1369 if (csky_debug)
1370 {
1371 gdb_printf (gdb_stdlog,
1372 "csky: addi r4,%d\n", imm);
1373 }
1374 }
1375 else if (CSKY_32_IS_SUBI4 (insn2))
1376 {
1377 int imm = (insn2 & 0xfff) + 1;
1378 adjust -= imm;
1379 if (csky_debug)
1380 {
1381 gdb_printf (gdb_stdlog,
1382 "csky: subi r4,%d\n", imm);
1383 }
1384 }
1385 else if (CSKY_32_IS_NOR4 (insn2))
1386 {
1387 adjust = ~adjust;
1388 if (csky_debug)
1389 {
1390 gdb_printf (gdb_stdlog,
1391 "csky: nor r4,r4,r4\n");
1392 }
1393 }
1394 else if (CSKY_32_IS_ROTLI4 (insn2))
1395 {
1396 int imm = ((insn2 >> 21) & 0x1f);
1397 int temp = adjust >> (32 - imm);
1398 adjust <<= imm;
1399 adjust |= temp;
1400 if (csky_debug)
1401 {
1402 gdb_printf (gdb_stdlog,
1403 "csky: rotli r4,r4,%d\n", imm);
1404 }
1405 }
1406 else if (CSKY_32_IS_LISI4 (insn2))
1407 {
1408 int imm = ((insn2 >> 21) & 0x1f);
1409 adjust <<= imm;
1410 if (csky_debug)
1411 {
1412 gdb_printf (gdb_stdlog,
1413 "csky: lsli r4,r4,%d\n", imm);
1414 }
1415 }
1416 else if (CSKY_32_IS_BSETI4 (insn2))
1417 {
1418 int imm = ((insn2 >> 21) & 0x1f);
1419 adjust |= (1 << imm);
1420 if (csky_debug)
1421 {
1422 gdb_printf (gdb_stdlog,
1423 "csky: bseti r4,r4 %d\n", imm);
1424 }
1425 }
1426 else if (CSKY_32_IS_BCLRI4 (insn2))
1427 {
1428 int imm = ((insn2 >> 21) & 0x1f);
1429 adjust &= ~(1 << imm);
1430 if (csky_debug)
1431 {
1432 gdb_printf (gdb_stdlog,
1433 "csky: bclri r4,r4 %d\n", imm);
1434 }
1435 }
1436 else if (CSKY_32_IS_IXH4 (insn2))
1437 {
1438 adjust *= 3;
1439 if (csky_debug)
1440 {
1441 gdb_printf (gdb_stdlog,
1442 "csky: ixh r4,r4,r4\n");
1443 }
1444 }
1445 else if (CSKY_32_IS_IXW4 (insn2))
1446 {
1447 adjust *= 5;
1448 if (csky_debug)
1449 {
1450 gdb_printf (gdb_stdlog,
1451 "csky: ixw r4,r4,r4\n");
1452 }
1453 }
1454 else if (CSKY_16_IS_ADDI4 (insn2))
1455 {
1456 int imm = (insn2 & 0xff) + 1;
1457 adjust += imm;
1458 if (csky_debug)
1459 {
1460 gdb_printf (gdb_stdlog,
1461 "csky: addi r4,%d\n", imm);
1462 }
1463 }
1464 else if (CSKY_16_IS_SUBI4 (insn2))
1465 {
1466 int imm = (insn2 & 0xff) + 1;
1467 adjust -= imm;
1468 if (csky_debug)
1469 {
1470 gdb_printf (gdb_stdlog,
1471 "csky: subi r4,%d\n", imm);
1472 }
1473 }
1474 else if (CSKY_16_IS_NOR4 (insn2))
1475 {
1476 adjust = ~adjust;
1477 if (csky_debug)
1478 {
1479 gdb_printf (gdb_stdlog,
1480 "csky: nor r4,r4\n");
1481 }
1482 }
1483 else if (CSKY_16_IS_BSETI4 (insn2))
1484 {
1485 int imm = (insn2 & 0x1f);
1486 adjust |= (1 << imm);
1487 if (csky_debug)
1488 {
1489 gdb_printf (gdb_stdlog,
1490 "csky: bseti r4, %d\n", imm);
1491 }
1492 }
1493 else if (CSKY_16_IS_BCLRI4 (insn2))
1494 {
1495 int imm = (insn2 & 0x1f);
1496 adjust &= ~(1 << imm);
1497 if (csky_debug)
1498 {
1499 gdb_printf (gdb_stdlog,
1500 "csky: bclri r4, %d\n", imm);
1501 }
1502 }
1503 else if (CSKY_16_IS_LSLI4 (insn2))
1504 {
1505 int imm = (insn2 & 0x1f);
1506 adjust <<= imm;
1507 if (csky_debug)
1508 {
1509 gdb_printf (gdb_stdlog,
1510 "csky: lsli r4,r4, %d\n", imm);
1511 }
1512 }
1513
1514 offset += insn_len;
1515 insn_len = csky_get_insn (gdbarch, addr + offset, &insn2);
1516 };
1517
1518 if (csky_debug)
1519 {
1520 gdb_printf (gdb_stdlog, "csky: done looking for"
1521 " r4 adjusters\n");
1522 }
1523
1524 /* If the next insn adjusts the stack pointer, we keep
1525 everything; if not, we scrap it and we've found the
1526 end of the prologue. */
1527 if (CSKY_IS_SUBU4 (insn2))
1528 {
1529 addr += offset;
1530 stacksize += adjust;
1531 if (csky_debug)
1532 {
1533 gdb_printf (gdb_stdlog,
1534 "csky: found stack adjustment of"
1535 " 0x%x bytes.\n", adjust);
1536 gdb_printf (gdb_stdlog,
1537 "csky: skipping to new address %s\n",
1538 core_addr_to_string_nz (addr));
1539 gdb_printf (gdb_stdlog,
1540 "csky: continuing\n");
1541 }
1542 continue;
1543 }
1544
1545 /* None of these instructions are prologue, so don't touch
1546 anything. */
1547 if (csky_debug)
1548 {
1549 gdb_printf (gdb_stdlog,
1550 "csky: no subu sp,sp,r4; NOT altering"
1551 " stacksize.\n");
1552 }
1553 break;
1554 }
1555 }
1556 else
1557 {
1558 /* insn_len != 4. */
1559
1560 /* subi.sp sp,disp. */
1561 if (CSKY_16_IS_SUBI0 (insn))
1562 {
1563 int offset = CSKY_16_SUBI_IMM (insn);
1564 if (csky_debug)
1565 {
1566 gdb_printf (gdb_stdlog,
1567 "csky: got subi r0,%d; continuing\n",
1568 offset);
1569 }
1570 stacksize += offset;
1571 continue;
1572 }
1573 /* stw.16 rz,(sp,disp). */
1574 else if (CSKY_16_IS_STWx0 (insn))
1575 {
1576 /* Spill register: see note for IS_STM above. */
1577 int disp;
1578
1579 rn = CSKY_16_ST_VAL_REGNUM (insn);
1580 disp = CSKY_16_ST_OFFSET (insn);
1581 register_offsets[rn] = stacksize - disp;
1582 if (csky_debug)
1583 print_savedreg_msg (rn, register_offsets, true);
1584 continue;
1585 }
1586 else if (CSKY_16_IS_MOV_FP_SP (insn))
1587 {
1588 /* SP is saved to FP reg, means prologue may modify SP. */
1589 is_fp_saved = 1;
1590 adjust_fp = stacksize;
1591 continue;
1592 }
1593 else if (CSKY_16_IS_PUSH (insn))
1594 {
1595 /* Push for 16_bit. */
1596 int offset = 0;
1597 if (CSKY_16_IS_PUSH_R15 (insn))
1598 {
1599 stacksize += 4;
1600 register_offsets[15] = stacksize;
1601 if (csky_debug)
1602 print_savedreg_msg (15, register_offsets, false);
1603 offset += 4;
1604 }
1605 if (CSKY_16_PUSH_LIST1 (insn))
1606 {
1607 int num = CSKY_16_PUSH_LIST1 (insn);
1608 int tmp = 0;
1609 stacksize += num * 4;
1610 offset += num * 4;
1611 if (csky_debug)
1612 {
1613 gdb_printf (gdb_stdlog,
1614 "csky: push regs_array: r4-r%d\n",
1615 4 + num - 1);
1616 }
1617 for (rn = 4; rn <= 4 + num - 1; rn++)
1618 {
1619 register_offsets[rn] = stacksize - tmp;
1620 if (csky_debug)
1621 {
1622 gdb_printf (gdb_stdlog,
1623 "csky: r%d saved at 0x%x"
1624 " (offset %d)\n", rn,
1625 register_offsets[rn], offset);
1626 }
1627 tmp += 4;
1628 }
1629 }
1630
1631 framesize = stacksize;
1632 if (csky_debug)
1633 gdb_printf (gdb_stdlog, "csky: continuing\n");
1634 continue;
1635 }
1636 else if (CSKY_16_IS_LRW4 (insn) || CSKY_16_IS_MOVI4 (insn))
1637 {
1638 int adjust = 0;
1639 unsigned int insn2;
1640
1641 if (csky_debug)
1642 {
1643 gdb_printf (gdb_stdlog,
1644 "csky: looking at large frame\n");
1645 }
1646 if (CSKY_16_IS_LRW4 (insn))
1647 {
1648 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1649 int offset = ((insn & 0x300) >> 3) | (insn & 0x1f);
1650 int literal_addr = (addr + ( offset << 2)) & 0xfffffffc;
1651 adjust = read_memory_unsigned_integer (literal_addr, 4,
1652 byte_order);
1653 }
1654 else
1655 {
1656 /* CSKY_16_IS_MOVI4 (insn). */
1657 adjust = (insn & 0xff);
1658 }
1659
1660 if (csky_debug)
1661 {
1662 gdb_printf (gdb_stdlog,
1663 "csky: base stacksize=0x%x\n", adjust);
1664 }
1665
1666 /* May have zero or more instructions which modify r4. */
1667 if (csky_debug)
1668 {
1669 gdb_printf (gdb_stdlog,
1670 "csky: looking for r4 adjusters...\n");
1671 }
1672 int offset = 2;
1673 insn_len = csky_get_insn (gdbarch, addr + offset, &insn2);
1674 while (CSKY_IS_R4_ADJUSTER (insn2))
1675 {
1676 if (CSKY_32_IS_ADDI4 (insn2))
1677 {
1678 int imm = (insn2 & 0xfff) + 1;
1679 adjust += imm;
1680 if (csky_debug)
1681 {
1682 gdb_printf (gdb_stdlog,
1683 "csky: addi r4,%d\n", imm);
1684 }
1685 }
1686 else if (CSKY_32_IS_SUBI4 (insn2))
1687 {
1688 int imm = (insn2 & 0xfff) + 1;
1689 adjust -= imm;
1690 if (csky_debug)
1691 {
1692 gdb_printf (gdb_stdlog,
1693 "csky: subi r4,%d\n", imm);
1694 }
1695 }
1696 else if (CSKY_32_IS_NOR4 (insn2))
1697 {
1698 adjust = ~adjust;
1699 if (csky_debug)
1700 {
1701 gdb_printf (gdb_stdlog,
1702 "csky: nor r4,r4,r4\n");
1703 }
1704 }
1705 else if (CSKY_32_IS_ROTLI4 (insn2))
1706 {
1707 int imm = ((insn2 >> 21) & 0x1f);
1708 int temp = adjust >> (32 - imm);
1709 adjust <<= imm;
1710 adjust |= temp;
1711 if (csky_debug)
1712 {
1713 gdb_printf (gdb_stdlog,
1714 "csky: rotli r4,r4,%d\n", imm);
1715 }
1716 }
1717 else if (CSKY_32_IS_LISI4 (insn2))
1718 {
1719 int imm = ((insn2 >> 21) & 0x1f);
1720 adjust <<= imm;
1721 if (csky_debug)
1722 {
1723 gdb_printf (gdb_stdlog,
1724 "csky: lsli r4,r4,%d\n", imm);
1725 }
1726 }
1727 else if (CSKY_32_IS_BSETI4 (insn2))
1728 {
1729 int imm = ((insn2 >> 21) & 0x1f);
1730 adjust |= (1 << imm);
1731 if (csky_debug)
1732 {
1733 gdb_printf (gdb_stdlog,
1734 "csky: bseti r4,r4 %d\n", imm);
1735 }
1736 }
1737 else if (CSKY_32_IS_BCLRI4 (insn2))
1738 {
1739 int imm = ((insn2 >> 21) & 0x1f);
1740 adjust &= ~(1 << imm);
1741 if (csky_debug)
1742 {
1743 gdb_printf (gdb_stdlog,
1744 "csky: bclri r4,r4 %d\n", imm);
1745 }
1746 }
1747 else if (CSKY_32_IS_IXH4 (insn2))
1748 {
1749 adjust *= 3;
1750 if (csky_debug)
1751 {
1752 gdb_printf (gdb_stdlog,
1753 "csky: ixh r4,r4,r4\n");
1754 }
1755 }
1756 else if (CSKY_32_IS_IXW4 (insn2))
1757 {
1758 adjust *= 5;
1759 if (csky_debug)
1760 {
1761 gdb_printf (gdb_stdlog,
1762 "csky: ixw r4,r4,r4\n");
1763 }
1764 }
1765 else if (CSKY_16_IS_ADDI4 (insn2))
1766 {
1767 int imm = (insn2 & 0xff) + 1;
1768 adjust += imm;
1769 if (csky_debug)
1770 {
1771 gdb_printf (gdb_stdlog,
1772 "csky: addi r4,%d\n", imm);
1773 }
1774 }
1775 else if (CSKY_16_IS_SUBI4 (insn2))
1776 {
1777 int imm = (insn2 & 0xff) + 1;
1778 adjust -= imm;
1779 if (csky_debug)
1780 {
1781 gdb_printf (gdb_stdlog,
1782 "csky: subi r4,%d\n", imm);
1783 }
1784 }
1785 else if (CSKY_16_IS_NOR4 (insn2))
1786 {
1787 adjust = ~adjust;
1788 if (csky_debug)
1789 {
1790 gdb_printf (gdb_stdlog,
1791 "csky: nor r4,r4\n");
1792 }
1793 }
1794 else if (CSKY_16_IS_BSETI4 (insn2))
1795 {
1796 int imm = (insn2 & 0x1f);
1797 adjust |= (1 << imm);
1798 if (csky_debug)
1799 {
1800 gdb_printf (gdb_stdlog,
1801 "csky: bseti r4, %d\n", imm);
1802 }
1803 }
1804 else if (CSKY_16_IS_BCLRI4 (insn2))
1805 {
1806 int imm = (insn2 & 0x1f);
1807 adjust &= ~(1 << imm);
1808 if (csky_debug)
1809 {
1810 gdb_printf (gdb_stdlog,
1811 "csky: bclri r4, %d\n", imm);
1812 }
1813 }
1814 else if (CSKY_16_IS_LSLI4 (insn2))
1815 {
1816 int imm = (insn2 & 0x1f);
1817 adjust <<= imm;
1818 if (csky_debug)
1819 {
1820 gdb_printf (gdb_stdlog,
1821 "csky: lsli r4,r4, %d\n", imm);
1822 }
1823 }
1824
1825 offset += insn_len;
1826 insn_len = csky_get_insn (gdbarch, addr + offset, &insn2);
1827 };
1828
1829 if (csky_debug)
1830 {
1831 gdb_printf (gdb_stdlog, "csky: "
1832 "done looking for r4 adjusters\n");
1833 }
1834
1835 /* If the next instruction adjusts the stack pointer, we keep
1836 everything; if not, we scrap it and we've found the end
1837 of the prologue. */
1838 if (CSKY_IS_SUBU4 (insn2))
1839 {
1840 addr += offset;
1841 stacksize += adjust;
1842 if (csky_debug)
1843 {
1844 gdb_printf (gdb_stdlog, "csky: "
1845 "found stack adjustment of 0x%x"
1846 " bytes.\n", adjust);
1847 gdb_printf (gdb_stdlog, "csky: "
1848 "skipping to new address %s\n",
1849 core_addr_to_string_nz (addr));
1850 gdb_printf (gdb_stdlog, "csky: continuing\n");
1851 }
1852 continue;
1853 }
1854
1855 /* None of these instructions are prologue, so don't touch
1856 anything. */
1857 if (csky_debug)
1858 {
1859 gdb_printf (gdb_stdlog, "csky: no subu sp,r4; "
1860 "NOT altering stacksize.\n");
1861 }
1862 break;
1863 }
1864 }
1865
1866 /* This is not a prologue instruction, so stop here. */
1867 if (csky_debug)
1868 {
1869 gdb_printf (gdb_stdlog, "csky: insn is not a prologue"
1870 " insn -- ending scan\n");
1871 }
1872 break;
1873 }
1874
1875 if (this_cache)
1876 {
1877 CORE_ADDR unwound_fp;
1878 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1879 this_cache->framesize = framesize;
1880
1881 if (is_fp_saved)
1882 {
1883 this_cache->framereg = CSKY_FP_REGNUM;
1884 unwound_fp = get_frame_register_unsigned (this_frame,
1885 this_cache->framereg);
1886 this_cache->prev_sp = unwound_fp + adjust_fp;
1887 }
1888 else
1889 {
1890 this_cache->framereg = CSKY_SP_REGNUM;
1891 unwound_fp = get_frame_register_unsigned (this_frame,
1892 this_cache->framereg);
1893 this_cache->prev_sp = unwound_fp + stacksize;
1894 }
1895
1896 /* Note where saved registers are stored. The offsets in
1897 REGISTER_OFFSETS are computed relative to the top of the frame. */
1898 for (rn = 0; rn < CSKY_NUM_GREGS; rn++)
1899 {
1900 if (register_offsets[rn] >= 0)
1901 {
1902 this_cache->saved_regs[rn].set_addr (this_cache->prev_sp
1903 - register_offsets[rn]);
1904 if (csky_debug)
1905 {
1906 CORE_ADDR rn_value = read_memory_unsigned_integer (
1907 this_cache->saved_regs[rn].addr (), 4, byte_order);
1908 gdb_printf (gdb_stdlog, "Saved register %s "
1909 "stored at 0x%08lx, value=0x%08lx\n",
1910 csky_register_names[rn],
1911 (unsigned long)
1912 this_cache->saved_regs[rn].addr (),
1913 (unsigned long) rn_value);
1914 }
1915 }
1916 }
1917 if (lr_type == LR_TYPE_EPC)
1918 {
1919 /* rte || epc . */
1920 this_cache->saved_regs[CSKY_PC_REGNUM]
1921 = this_cache->saved_regs[CSKY_EPC_REGNUM];
1922 }
1923 else if (lr_type == LR_TYPE_FPC)
1924 {
1925 /* rfi || fpc . */
1926 this_cache->saved_regs[CSKY_PC_REGNUM]
1927 = this_cache->saved_regs[CSKY_FPC_REGNUM];
1928 }
1929 else
1930 {
1931 this_cache->saved_regs[CSKY_PC_REGNUM]
1932 = this_cache->saved_regs[CSKY_LR_REGNUM];
1933 }
1934 }
1935
1936 return addr;
1937 }
1938
1939 /* Detect whether PC is at a point where the stack frame has been
1940 destroyed. */
1941
1942 static int
1943 csky_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
1944 {
1945 unsigned int insn;
1946 CORE_ADDR addr;
1947 CORE_ADDR func_start, func_end;
1948
1949 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
1950 return 0;
1951
1952 bool fp_saved = false;
1953 int insn_len;
1954 for (addr = func_start; addr < func_end; addr += insn_len)
1955 {
1956 /* Get next insn. */
1957 insn_len = csky_get_insn (gdbarch, addr, &insn);
1958
1959 if (insn_len == 2)
1960 {
1961 /* Is sp is saved to fp. */
1962 if (CSKY_16_IS_MOV_FP_SP (insn))
1963 fp_saved = true;
1964 /* If sp was saved to fp and now being restored from
1965 fp then it indicates the start of epilog. */
1966 else if (fp_saved && CSKY_16_IS_MOV_SP_FP (insn))
1967 return pc >= addr;
1968 }
1969 }
1970 return 0;
1971 }
1972
1973 /* Implement the skip_prologue gdbarch hook. */
1974
1975 static CORE_ADDR
1976 csky_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1977 {
1978 CORE_ADDR func_addr, func_end;
1979 const int default_search_limit = 128;
1980
1981 /* See if we can find the end of the prologue using the symbol table. */
1982 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
1983 {
1984 CORE_ADDR post_prologue_pc
1985 = skip_prologue_using_sal (gdbarch, func_addr);
1986
1987 if (post_prologue_pc != 0)
1988 return std::max (pc, post_prologue_pc);
1989 }
1990 else
1991 func_end = pc + default_search_limit;
1992
1993 /* Find the end of prologue. Default lr_type. */
1994 return csky_analyze_prologue (gdbarch, pc, func_end, func_end,
1995 NULL, NULL, LR_TYPE_R15);
1996 }
1997
1998 /* Implement the breakpoint_kind_from_pc gdbarch method. */
1999
2000 static int
2001 csky_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
2002 {
2003 if (csky_pc_is_csky16 (gdbarch, *pcptr))
2004 return CSKY_INSN_SIZE16;
2005 else
2006 return CSKY_INSN_SIZE32;
2007 }
2008
2009 /* Implement the sw_breakpoint_from_kind gdbarch method. */
2010
2011 static const gdb_byte *
2012 csky_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
2013 {
2014 *size = kind;
2015 if (kind == CSKY_INSN_SIZE16)
2016 {
2017 static gdb_byte csky_16_breakpoint[] = { 0, 0 };
2018 return csky_16_breakpoint;
2019 }
2020 else
2021 {
2022 static gdb_byte csky_32_breakpoint[] = { 0, 0, 0, 0 };
2023 return csky_32_breakpoint;
2024 }
2025 }
2026
2027 /* Determine link register type. */
2028
2029 static lr_type_t
2030 csky_analyze_lr_type (struct gdbarch *gdbarch,
2031 CORE_ADDR start_pc, CORE_ADDR end_pc)
2032 {
2033 CORE_ADDR addr;
2034 unsigned int insn, insn_len;
2035 insn_len = 2;
2036
2037 for (addr = start_pc; addr < end_pc; addr += insn_len)
2038 {
2039 insn_len = csky_get_insn (gdbarch, addr, &insn);
2040 if (insn_len == 4)
2041 {
2042 if (CSKY_32_IS_MFCR_EPSR (insn) || CSKY_32_IS_MFCR_EPC (insn)
2043 || CSKY_32_IS_RTE (insn))
2044 return LR_TYPE_EPC;
2045 }
2046 else if (CSKY_32_IS_MFCR_FPSR (insn) || CSKY_32_IS_MFCR_FPC (insn)
2047 || CSKY_32_IS_RFI (insn))
2048 return LR_TYPE_FPC;
2049 else if (CSKY_32_IS_JMP (insn) || CSKY_32_IS_BR (insn)
2050 || CSKY_32_IS_JMPIX (insn) || CSKY_32_IS_JMPI (insn))
2051 return LR_TYPE_R15;
2052 else
2053 {
2054 /* 16 bit instruction. */
2055 if (CSKY_16_IS_JMP (insn) || CSKY_16_IS_BR (insn)
2056 || CSKY_16_IS_JMPIX (insn))
2057 return LR_TYPE_R15;
2058 }
2059 }
2060 return LR_TYPE_R15;
2061 }
2062
2063 /* Heuristic unwinder. */
2064
2065 static struct csky_unwind_cache *
2066 csky_frame_unwind_cache (const frame_info_ptr &this_frame)
2067 {
2068 CORE_ADDR prologue_start, prologue_end, func_end, prev_pc, block_addr;
2069 struct csky_unwind_cache *cache;
2070 const struct block *bl;
2071 unsigned long func_size = 0;
2072 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2073 unsigned int sp_regnum = CSKY_SP_REGNUM;
2074
2075 /* Default lr type is r15. */
2076 lr_type_t lr_type = LR_TYPE_R15;
2077
2078 cache = FRAME_OBSTACK_ZALLOC (struct csky_unwind_cache);
2079 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2080
2081 /* Assume there is no frame until proven otherwise. */
2082 cache->framereg = sp_regnum;
2083
2084 cache->framesize = 0;
2085
2086 prev_pc = get_frame_pc (this_frame);
2087 block_addr = get_frame_address_in_block (this_frame);
2088 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
2089 &func_end) == 0)
2090 /* We couldn't find a function containing block_addr, so bail out
2091 and hope for the best. */
2092 return cache;
2093
2094 /* Get the (function) symbol matching prologue_start. */
2095 bl = block_for_pc (prologue_start);
2096 if (bl != NULL)
2097 func_size = bl->end () - bl->start ();
2098 else
2099 {
2100 bound_minimal_symbol msymbol
2101 = lookup_minimal_symbol_by_pc (prologue_start);
2102 if (msymbol.minsym != NULL)
2103 func_size = msymbol.minsym->size ();
2104 }
2105
2106 /* If FUNC_SIZE is 0 we may have a special-case use of lr
2107 e.g. exception or interrupt. */
2108 if (func_size == 0)
2109 lr_type = csky_analyze_lr_type (gdbarch, prologue_start, func_end);
2110
2111 prologue_end = std::min (func_end, prev_pc);
2112
2113 /* Analyze the function prologue. */
2114 csky_analyze_prologue (gdbarch, prologue_start, prologue_end,
2115 func_end, this_frame, cache, lr_type);
2116
2117 /* gdbarch_sp_regnum contains the value and not the address. */
2118 cache->saved_regs[sp_regnum].set_value (cache->prev_sp);
2119 return cache;
2120 }
2121
2122 /* Implement the this_id function for the normal unwinder. */
2123
2124 static void
2125 csky_frame_this_id (const frame_info_ptr &this_frame,
2126 void **this_prologue_cache, struct frame_id *this_id)
2127 {
2128 struct csky_unwind_cache *cache;
2129 struct frame_id id;
2130
2131 if (*this_prologue_cache == NULL)
2132 *this_prologue_cache = csky_frame_unwind_cache (this_frame);
2133 cache = (struct csky_unwind_cache *) *this_prologue_cache;
2134
2135 /* This marks the outermost frame. */
2136 if (cache->prev_sp == 0)
2137 return;
2138
2139 id = frame_id_build (cache->prev_sp, get_frame_func (this_frame));
2140 *this_id = id;
2141 }
2142
2143 /* Implement the prev_register function for the normal unwinder. */
2144
2145 static struct value *
2146 csky_frame_prev_register (const frame_info_ptr &this_frame,
2147 void **this_prologue_cache, int regnum)
2148 {
2149 struct csky_unwind_cache *cache;
2150
2151 if (*this_prologue_cache == NULL)
2152 *this_prologue_cache = csky_frame_unwind_cache (this_frame);
2153 cache = (struct csky_unwind_cache *) *this_prologue_cache;
2154
2155 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
2156 regnum);
2157 }
2158
2159 /* Data structures for the normal prologue-analysis-based
2160 unwinder. */
2161
2162 static const struct frame_unwind_legacy csky_unwind_cache (
2163 "cski prologue",
2164 NORMAL_FRAME,
2165 FRAME_UNWIND_ARCH,
2166 default_frame_unwind_stop_reason,
2167 csky_frame_this_id,
2168 csky_frame_prev_register,
2169 NULL,
2170 default_frame_sniffer,
2171 NULL,
2172 NULL
2173 );
2174
2175 static CORE_ADDR
2176 csky_check_long_branch (const frame_info_ptr &frame, CORE_ADDR pc)
2177 {
2178 gdb_byte buf[8];
2179 struct gdbarch *gdbarch = get_frame_arch (frame);
2180 enum bfd_endian byte_order_for_code
2181 = gdbarch_byte_order_for_code (gdbarch);
2182
2183 if (target_read_memory (pc, buf, 8) == 0)
2184 {
2185 unsigned int data0
2186 = extract_unsigned_integer (buf, 4, byte_order_for_code);
2187 unsigned int data1
2188 = extract_unsigned_integer (buf + 4, 4, byte_order_for_code);
2189
2190 /* Case: jmpi [pc+4] : 0xeac00001
2191 .long addr */
2192 if (data0 == CSKY_JMPI_PC_4)
2193 return data1;
2194
2195 /* Case: lrw t1, [pc+8] : 0xea8d0002
2196 jmp t1 : 0x7834
2197 nop : 0x6c03
2198 .long addr */
2199 if ((data0 == CSKY_LRW_T1_PC_8) && (data1 == CSKY_JMP_T1_VS_NOP))
2200 {
2201 if (target_read_memory (pc + 8, buf, 4) == 0)
2202 return extract_unsigned_integer (buf, 4, byte_order_for_code);
2203 }
2204
2205 return 0;
2206 }
2207
2208 return 0;
2209 }
2210
2211 static int
2212 csky_stub_unwind_sniffer (const struct frame_unwind *self,
2213 const frame_info_ptr &this_frame,
2214 void **this_prologue_cache)
2215 {
2216 CORE_ADDR addr_in_block, pc;
2217 gdb_byte dummy[4];
2218 const char *name;
2219 CORE_ADDR start_addr;
2220
2221 /* Get pc */
2222 addr_in_block = get_frame_address_in_block (this_frame);
2223 pc = get_frame_pc (this_frame);
2224
2225 if (in_plt_section (addr_in_block)
2226 || target_read_memory (pc, dummy, 4) != 0)
2227 return 1;
2228
2229 /* Find the starting address and name of the function containing the PC. */
2230 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
2231 {
2232 start_addr = csky_check_long_branch (this_frame, pc);
2233 /* if not long branch, return 0. */
2234 if (start_addr != 0)
2235 return 1;
2236
2237 return 0;
2238 }
2239
2240 return 0;
2241 }
2242
2243 static struct csky_unwind_cache *
2244 csky_make_stub_cache (const frame_info_ptr &this_frame)
2245 {
2246 struct csky_unwind_cache *cache;
2247
2248 cache = FRAME_OBSTACK_ZALLOC (struct csky_unwind_cache);
2249 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2250 cache->prev_sp = get_frame_register_unsigned (this_frame, CSKY_SP_REGNUM);
2251
2252 return cache;
2253 }
2254
2255 static void
2256 csky_stub_this_id (const frame_info_ptr &this_frame,
2257 void **this_cache,
2258 struct frame_id *this_id)
2259 {
2260 struct csky_unwind_cache *cache;
2261
2262 if (*this_cache == NULL)
2263 *this_cache = csky_make_stub_cache (this_frame);
2264 cache = (struct csky_unwind_cache *) *this_cache;
2265
2266 /* Our frame ID for a stub frame is the current SP and LR. */
2267 *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame));
2268 }
2269
2270 static struct value *
2271 csky_stub_prev_register (const frame_info_ptr &this_frame,
2272 void **this_cache,
2273 int prev_regnum)
2274 {
2275 struct csky_unwind_cache *cache;
2276
2277 if (*this_cache == NULL)
2278 *this_cache = csky_make_stub_cache (this_frame);
2279 cache = (struct csky_unwind_cache *) *this_cache;
2280
2281 /* If we are asked to unwind the PC, then return the LR. */
2282 if (prev_regnum == CSKY_PC_REGNUM)
2283 {
2284 CORE_ADDR lr;
2285
2286 lr = frame_unwind_register_unsigned (this_frame, CSKY_LR_REGNUM);
2287 return frame_unwind_got_constant (this_frame, prev_regnum, lr);
2288 }
2289
2290 if (prev_regnum == CSKY_SP_REGNUM)
2291 return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp);
2292
2293 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
2294 prev_regnum);
2295 }
2296
2297 static const frame_unwind_legacy csky_stub_unwind (
2298 "csky stub",
2299 NORMAL_FRAME,
2300 FRAME_UNWIND_ARCH,
2301 default_frame_unwind_stop_reason,
2302 csky_stub_this_id,
2303 csky_stub_prev_register,
2304 NULL,
2305 csky_stub_unwind_sniffer
2306 );
2307
2308 /* Implement the this_base, this_locals, and this_args hooks
2309 for the normal unwinder. */
2310
2311 static CORE_ADDR
2312 csky_frame_base_address (const frame_info_ptr &this_frame, void **this_cache)
2313 {
2314 struct csky_unwind_cache *cache;
2315
2316 if (*this_cache == NULL)
2317 *this_cache = csky_frame_unwind_cache (this_frame);
2318 cache = (struct csky_unwind_cache *) *this_cache;
2319
2320 return cache->prev_sp - cache->framesize;
2321 }
2322
2323 static const struct frame_base csky_frame_base = {
2324 &csky_unwind_cache,
2325 csky_frame_base_address,
2326 csky_frame_base_address,
2327 csky_frame_base_address
2328 };
2329
2330 /* Initialize register access method. */
2331
2332 static void
2333 csky_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
2334 struct dwarf2_frame_state_reg *reg,
2335 const frame_info_ptr &this_frame)
2336 {
2337 if (regnum == gdbarch_pc_regnum (gdbarch))
2338 reg->how = DWARF2_FRAME_REG_RA;
2339 else if (regnum == gdbarch_sp_regnum (gdbarch))
2340 reg->how = DWARF2_FRAME_REG_CFA;
2341 }
2342
2343 /* Create csky register groups. */
2344
2345 static void
2346 csky_init_reggroup ()
2347 {
2348 cr_reggroup = reggroup_new ("cr", USER_REGGROUP);
2349 fr_reggroup = reggroup_new ("fr", USER_REGGROUP);
2350 vr_reggroup = reggroup_new ("vr", USER_REGGROUP);
2351 mmu_reggroup = reggroup_new ("mmu", USER_REGGROUP);
2352 prof_reggroup = reggroup_new ("profiling", USER_REGGROUP);
2353 }
2354
2355 /* Add register groups into reggroup list. */
2356
2357 static void
2358 csky_add_reggroups (struct gdbarch *gdbarch)
2359 {
2360 reggroup_add (gdbarch, cr_reggroup);
2361 reggroup_add (gdbarch, fr_reggroup);
2362 reggroup_add (gdbarch, vr_reggroup);
2363 reggroup_add (gdbarch, mmu_reggroup);
2364 reggroup_add (gdbarch, prof_reggroup);
2365 }
2366
2367 /* Return the groups that a CSKY register can be categorised into. */
2368
2369 static int
2370 csky_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2371 const struct reggroup *reggroup)
2372 {
2373 int raw_p;
2374
2375 if (gdbarch_register_name (gdbarch, regnum)[0] == '\0')
2376 return 0;
2377
2378 if (reggroup == all_reggroup)
2379 return 1;
2380
2381 raw_p = regnum < gdbarch_num_regs (gdbarch);
2382 if (reggroup == save_reggroup || reggroup == restore_reggroup)
2383 return raw_p;
2384
2385 if ((((regnum >= CSKY_R0_REGNUM) && (regnum <= CSKY_R0_REGNUM + 31))
2386 || (regnum == CSKY_PC_REGNUM)
2387 || (regnum == CSKY_EPC_REGNUM)
2388 || (regnum == CSKY_CR0_REGNUM)
2389 || (regnum == CSKY_EPSR_REGNUM))
2390 && (reggroup == general_reggroup))
2391 return 1;
2392
2393 if (((regnum == CSKY_PC_REGNUM)
2394 || ((regnum >= CSKY_CR0_REGNUM)
2395 && (regnum <= CSKY_CR0_REGNUM + 30)))
2396 && (reggroup == cr_reggroup))
2397 return 2;
2398
2399 if ((((regnum >= CSKY_VR0_REGNUM) && (regnum <= CSKY_VR0_REGNUM + 15))
2400 || ((regnum >= CSKY_FCR_REGNUM)
2401 && (regnum <= CSKY_FCR_REGNUM + 2)))
2402 && (reggroup == vr_reggroup))
2403 return 3;
2404
2405 if (((regnum >= CSKY_MMU_REGNUM) && (regnum <= CSKY_MMU_REGNUM + 8))
2406 && (reggroup == mmu_reggroup))
2407 return 4;
2408
2409 if (((regnum >= CSKY_PROFCR_REGNUM)
2410 && (regnum <= CSKY_PROFCR_REGNUM + 48))
2411 && (reggroup == prof_reggroup))
2412 return 5;
2413
2414 if ((((regnum >= CSKY_FR0_REGNUM) && (regnum <= CSKY_FR0_REGNUM + 15))
2415 || ((regnum >= CSKY_FCR_REGNUM) && (regnum <= CSKY_FCR_REGNUM + 2)))
2416 && (reggroup == fr_reggroup))
2417 return 6;
2418
2419 if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
2420 {
2421 if (tdesc_register_in_reggroup_p (gdbarch, regnum, reggroup) > 0)
2422 return 7;
2423 }
2424
2425 return 0;
2426 }
2427
2428 /* Implement the dwarf2_reg_to_regnum gdbarch method. */
2429
2430 static int
2431 csky_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int dw_reg)
2432 {
2433 /* For GPRs. */
2434 if (dw_reg >= CSKY_R0_REGNUM && dw_reg <= CSKY_R0_REGNUM + 31)
2435 return dw_reg;
2436
2437 /* For Hi, Lo, PC. */
2438 if (dw_reg == CSKY_HI_REGNUM || dw_reg == CSKY_LO_REGNUM
2439 || dw_reg == CSKY_PC_REGNUM)
2440 return dw_reg;
2441
2442 /* For Float and Vector pseudo registers. */
2443 if (dw_reg >= FV_PSEUDO_REGNO_FIRST && dw_reg <= FV_PSEUDO_REGNO_LAST)
2444 {
2445 char name_buf[4];
2446
2447 xsnprintf (name_buf, sizeof (name_buf), "s%d",
2448 dw_reg - FV_PSEUDO_REGNO_FIRST);
2449 return user_reg_map_name_to_regnum (gdbarch, name_buf,
2450 strlen (name_buf));
2451 }
2452
2453 /* Others, unknown. */
2454 return -1;
2455 }
2456
2457 /* Check whether xml has discribled the essential regs. */
2458
2459 static int
2460 csky_essential_reg_check (const struct csky_supported_tdesc_register *reg)
2461 {
2462 if ((strcmp (reg->name , "pc") == 0)
2463 && (reg->num == CSKY_PC_REGNUM))
2464 return CSKY_TDESC_REGS_PC_NUMBERED;
2465 else if ((strcmp (reg->name , "r14") == 0)
2466 && (reg->num == CSKY_SP_REGNUM))
2467 return CSKY_TDESC_REGS_SP_NUMBERED;
2468 else if ((strcmp (reg->name , "r15") == 0)
2469 && (reg->num == CSKY_LR_REGNUM))
2470 return CSKY_TDESC_REGS_LR_NUMBERED;
2471 else
2472 return 0;
2473 }
2474
2475 /* Check whether xml has discribled the fr0~fr15 regs. */
2476
2477 static int
2478 csky_fr0_fr15_reg_check (const struct csky_supported_tdesc_register *reg) {
2479 int i = 0;
2480 for (i = 0; i < 16; i++)
2481 {
2482 if ((strcmp (reg->name, csky_supported_fpu_regs[i].name) == 0)
2483 && (csky_supported_fpu_regs[i].num == reg->num))
2484 return (1 << i);
2485 }
2486
2487 return 0;
2488 };
2489
2490 /* Check whether xml has discribled the fr16~fr31 regs. */
2491
2492 static int
2493 csky_fr16_fr31_reg_check (const struct csky_supported_tdesc_register *reg) {
2494 int i = 0;
2495 for (i = 0; i < 16; i++)
2496 {
2497 if ((strcmp (reg->name, csky_supported_fpu_regs[i + 16].name) == 0)
2498 && (csky_supported_fpu_regs[i + 16].num == reg->num))
2499 return (1 << i);
2500 }
2501
2502 return 0;
2503 };
2504
2505 /* Check whether xml has discribled the vr0~vr15 regs. */
2506
2507 static int
2508 csky_vr0_vr15_reg_check (const struct csky_supported_tdesc_register *reg) {
2509 int i = 0;
2510 for (i = 0; i < 16; i++)
2511 {
2512 if ((strcmp (reg->name, csky_supported_fpu_regs[i + 32].name) == 0)
2513 && (csky_supported_fpu_regs[i + 32].num == reg->num))
2514 return (1 << i);
2515 }
2516
2517 return 0;
2518 };
2519
2520 /* Return pseudo reg's name. */
2521
2522 static const char *
2523 csky_pseudo_register_name (struct gdbarch *gdbarch, int regno)
2524 {
2525 int num_regs = gdbarch_num_regs (gdbarch);
2526 csky_gdbarch_tdep *tdep
2527 = gdbarch_tdep<csky_gdbarch_tdep> (gdbarch);
2528
2529 regno -= num_regs;
2530
2531 if (tdep->fv_pseudo_registers_count)
2532 {
2533 static const char *const fv_pseudo_names[] = {
2534 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
2535 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
2536 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
2537 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
2538 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39",
2539 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47",
2540 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55",
2541 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63",
2542 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71",
2543 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79",
2544 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87",
2545 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95",
2546 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103",
2547 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111",
2548 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119",
2549 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127",
2550 };
2551
2552 if (regno < tdep->fv_pseudo_registers_count)
2553 {
2554 if ((regno < 64) && ((regno % 4) >= 2) && !tdep->has_vr0)
2555 return "";
2556 else if ((regno >= 64) && ((regno % 4) >= 2))
2557 return "";
2558 else
2559 return fv_pseudo_names[regno];
2560 }
2561 }
2562
2563 return "";
2564 }
2565
2566 /* Read for csky pseudo regs. */
2567
2568 static enum register_status
2569 csky_pseudo_register_read (struct gdbarch *gdbarch,
2570 struct readable_regcache *regcache,
2571 int regnum, gdb_byte *buf)
2572 {
2573 int num_regs = gdbarch_num_regs (gdbarch);
2574 csky_gdbarch_tdep *tdep
2575 = gdbarch_tdep<csky_gdbarch_tdep> (gdbarch);
2576
2577 regnum -= num_regs;
2578
2579 if (regnum < tdep->fv_pseudo_registers_count)
2580 {
2581 enum register_status status;
2582 int gdb_regnum = 0;
2583 int offset = 0;
2584 gdb_byte reg_buf[16];
2585
2586 /* Ensure getting s0~s63 from vrx if tdep->has_vr0 is true. */
2587 if (tdep->has_vr0)
2588 {
2589 if (regnum < 64)
2590 {
2591 gdb_regnum = CSKY_VR0_REGNUM + (regnum / 4);
2592 offset = (regnum % 4) * 4;
2593 }
2594 else
2595 {
2596 gdb_regnum = CSKY_FR16_REGNUM + ((regnum - 64) / 4);
2597 if ((regnum % 4) >= 2)
2598 return REG_UNAVAILABLE;
2599 offset = (regnum % 2) * 4;
2600 }
2601 }
2602 else
2603 {
2604 gdb_regnum = CSKY_FR0_REGNUM + (regnum / 4);
2605 if ((regnum % 4) >= 2)
2606 return REG_UNAVAILABLE;
2607 offset = (regnum % 2) * 4;
2608 }
2609
2610 status = regcache->raw_read (gdb_regnum, reg_buf);
2611 if (status == REG_VALID)
2612 memcpy (buf, reg_buf + offset, 4);
2613 return status;
2614 }
2615
2616 return REG_UNKNOWN;
2617 }
2618
2619 /* Write for csky pseudo regs. */
2620
2621 static void
2622 csky_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2623 int regnum, const gdb_byte *buf)
2624 {
2625 int num_regs = gdbarch_num_regs (gdbarch);
2626 csky_gdbarch_tdep *tdep
2627 = gdbarch_tdep<csky_gdbarch_tdep> (gdbarch);
2628
2629 regnum -= num_regs;
2630
2631 if (regnum < tdep->fv_pseudo_registers_count)
2632 {
2633 gdb_byte reg_buf[16];
2634 int gdb_regnum = 0;
2635 int offset = 0;
2636
2637 if (tdep->has_vr0)
2638 {
2639 if (regnum < 64)
2640 {
2641 gdb_regnum = CSKY_VR0_REGNUM + (regnum / 4);
2642 offset = (regnum % 4) * 4;
2643 }
2644 else
2645 {
2646 gdb_regnum = CSKY_FR16_REGNUM + ((regnum - 64) / 4);
2647 if ((regnum % 4) >= 2)
2648 return;
2649 offset = (regnum % 2) * 4;
2650 }
2651 }
2652 else
2653 {
2654 gdb_regnum = CSKY_FR0_REGNUM + (regnum / 4);
2655 if ((regnum % 4) >= 2)
2656 return;
2657 offset = (regnum % 2) * 4;
2658 }
2659
2660 regcache->raw_read (gdb_regnum, reg_buf);
2661 memcpy (reg_buf + offset, buf, 4);
2662 regcache->raw_write (gdb_regnum, reg_buf);
2663 return;
2664 }
2665
2666 return;
2667 }
2668
2669 /* Initialize the current architecture based on INFO. If possible,
2670 re-use an architecture from ARCHES, which is a list of
2671 architectures already created during this debugging session.
2672
2673 Called at program startup, when reading a core file, and when
2674 reading a binary file. */
2675
2676 static struct gdbarch *
2677 csky_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2678 {
2679 /* Analyze info.abfd. */
2680 unsigned int fpu_abi = 0;
2681 unsigned int vdsp_version = 0;
2682 unsigned int fpu_hardfp = 0;
2683 /* Analyze info.target_desc */
2684 int num_regs = 0;
2685 int has_fr0 = 0;
2686 int has_fr16 = 0;
2687 int has_vr0 = 0;
2688 tdesc_arch_data_up tdesc_data;
2689
2690 if (tdesc_has_registers (info.target_desc))
2691 {
2692 int valid_p = 0;
2693 int numbered = 0;
2694 int index = 0;
2695 int i = 0;
2696 int feature_names_count = ARRAY_SIZE (csky_supported_tdesc_feature_names);
2697 int support_tdesc_regs_count
2698 = csky_get_supported_tdesc_registers_count();
2699 const struct csky_supported_tdesc_register *tdesc_reg;
2700 const struct tdesc_feature *feature;
2701
2702 tdesc_data = tdesc_data_alloc ();
2703 for (index = 0; index < feature_names_count; index ++)
2704 {
2705 feature = tdesc_find_feature (info.target_desc,
2706 csky_supported_tdesc_feature_names[index]);
2707 if (feature != NULL)
2708 {
2709 for (i = 0; i < support_tdesc_regs_count; i++)
2710 {
2711 tdesc_reg = csky_get_supported_register_by_index (i);
2712 if (!tdesc_reg)
2713 break;
2714 numbered = tdesc_numbered_register (feature, tdesc_data.get(),
2715 tdesc_reg->num,
2716 tdesc_reg->name);
2717 if (numbered) {
2718 valid_p |= csky_essential_reg_check (tdesc_reg);
2719 has_fr0 |= csky_fr0_fr15_reg_check (tdesc_reg);
2720 has_fr16 |= csky_fr16_fr31_reg_check (tdesc_reg);
2721 has_vr0 |= csky_vr0_vr15_reg_check (tdesc_reg);
2722 if (num_regs < tdesc_reg->num)
2723 num_regs = tdesc_reg->num;
2724 }
2725 }
2726 }
2727 }
2728 if (valid_p != CSKY_TDESC_REGS_ESSENTIAL_VALUE)
2729 return NULL;
2730 }
2731
2732 /* When the type of bfd file is srec(or any files are not elf),
2733 the E_FLAGS will be not credible. */
2734 if (info.abfd != NULL && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
2735 {
2736 /* Get FPU, VDSP build options. */
2737 fpu_abi = bfd_elf_get_obj_attr_int (info.abfd,
2738 OBJ_ATTR_PROC,
2739 Tag_CSKY_FPU_ABI);
2740 vdsp_version = bfd_elf_get_obj_attr_int (info.abfd,
2741 OBJ_ATTR_PROC,
2742 Tag_CSKY_VDSP_VERSION);
2743 fpu_hardfp = bfd_elf_get_obj_attr_int (info.abfd,
2744 OBJ_ATTR_PROC,
2745 Tag_CSKY_FPU_HARDFP);
2746 }
2747
2748 /* Find a candidate among the list of pre-declared architectures. */
2749 for (arches = gdbarch_list_lookup_by_info (arches, &info);
2750 arches != NULL;
2751 arches = gdbarch_list_lookup_by_info (arches->next, &info))
2752 {
2753 csky_gdbarch_tdep *tdep
2754 = gdbarch_tdep<csky_gdbarch_tdep> (arches->gdbarch);
2755 if (fpu_abi != tdep->fpu_abi)
2756 continue;
2757 if (vdsp_version != tdep->vdsp_version)
2758 continue;
2759 if (fpu_hardfp != tdep->fpu_hardfp)
2760 continue;
2761
2762 /* Found a match. */
2763 return arches->gdbarch;
2764 }
2765
2766 /* None found, create a new architecture from the information
2767 provided. */
2768 gdbarch *gdbarch
2769 = gdbarch_alloc (&info, gdbarch_tdep_up (new csky_gdbarch_tdep));
2770 csky_gdbarch_tdep *tdep = gdbarch_tdep<csky_gdbarch_tdep> (gdbarch);
2771
2772 tdep->fpu_abi = fpu_abi;
2773 tdep->vdsp_version = vdsp_version;
2774 tdep->fpu_hardfp = fpu_hardfp;
2775
2776 if (tdesc_data != NULL)
2777 {
2778 if ((has_vr0 == CSKY_FULL16_ONEHOT_VALUE)
2779 && (has_fr16 == CSKY_FULL16_ONEHOT_VALUE))
2780 {
2781 tdep->has_vr0 = 1;
2782 tdep->fv_pseudo_registers_count = 128;
2783 }
2784 else if ((has_vr0 == CSKY_FULL16_ONEHOT_VALUE)
2785 && (has_fr16 != CSKY_FULL16_ONEHOT_VALUE))
2786 {
2787 tdep->has_vr0 = 1;
2788 tdep->fv_pseudo_registers_count = 64;
2789 }
2790 else if ((has_fr0 == CSKY_FULL16_ONEHOT_VALUE)
2791 && (has_vr0 != CSKY_FULL16_ONEHOT_VALUE))
2792 {
2793 tdep->has_vr0 = 0;
2794 tdep->fv_pseudo_registers_count = 64;
2795 }
2796 else
2797 {
2798 tdep->has_vr0 = 0;
2799 tdep->fv_pseudo_registers_count = 0;
2800 }
2801 }
2802 else
2803 {
2804 tdep->has_vr0 = 1;
2805 tdep->fv_pseudo_registers_count = 64;
2806 }
2807
2808 /* Target data types. */
2809 set_gdbarch_ptr_bit (gdbarch, 32);
2810 set_gdbarch_addr_bit (gdbarch, 32);
2811 set_gdbarch_short_bit (gdbarch, 16);
2812 set_gdbarch_int_bit (gdbarch, 32);
2813 set_gdbarch_long_bit (gdbarch, 32);
2814 set_gdbarch_long_long_bit (gdbarch, 64);
2815 set_gdbarch_float_bit (gdbarch, 32);
2816 set_gdbarch_double_bit (gdbarch, 64);
2817 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
2818 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
2819
2820 /* Information about the target architecture. */
2821 set_gdbarch_return_value (gdbarch, csky_return_value);
2822 set_gdbarch_breakpoint_kind_from_pc (gdbarch, csky_breakpoint_kind_from_pc);
2823 set_gdbarch_sw_breakpoint_from_kind (gdbarch, csky_sw_breakpoint_from_kind);
2824
2825 /* Register architecture. */
2826 set_gdbarch_num_regs (gdbarch, CSKY_NUM_REGS);
2827 set_gdbarch_pc_regnum (gdbarch, CSKY_PC_REGNUM);
2828 set_gdbarch_sp_regnum (gdbarch, CSKY_SP_REGNUM);
2829 set_gdbarch_register_name (gdbarch, csky_register_name);
2830 set_gdbarch_register_type (gdbarch, csky_register_type);
2831 set_gdbarch_read_pc (gdbarch, csky_read_pc);
2832 set_gdbarch_write_pc (gdbarch, csky_write_pc);
2833 csky_add_reggroups (gdbarch);
2834 set_gdbarch_register_reggroup_p (gdbarch, csky_register_reggroup_p);
2835 set_gdbarch_stab_reg_to_regnum (gdbarch, csky_dwarf_reg_to_regnum);
2836 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, csky_dwarf_reg_to_regnum);
2837 dwarf2_frame_set_init_reg (gdbarch, csky_dwarf2_frame_init_reg);
2838
2839 /* Functions to analyze frames. */
2840 frame_base_set_default (gdbarch, &csky_frame_base);
2841 set_gdbarch_skip_prologue (gdbarch, csky_skip_prologue);
2842 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2843 set_gdbarch_frame_align (gdbarch, csky_frame_align);
2844 set_gdbarch_stack_frame_destroyed_p (gdbarch, csky_stack_frame_destroyed_p);
2845
2846 /* Functions handling dummy frames. */
2847 set_gdbarch_push_dummy_call (gdbarch, csky_push_dummy_call);
2848
2849 /* Frame unwinders. Use DWARF debug info if available,
2850 otherwise use our own unwinder. */
2851 dwarf2_append_unwinders (gdbarch);
2852 frame_unwind_append_unwinder (gdbarch, &csky_stub_unwind);
2853 frame_unwind_append_unwinder (gdbarch, &csky_unwind_cache);
2854
2855 /* Hook in ABI-specific overrides, if they have been registered. */
2856 gdbarch_init_osabi (info, gdbarch);
2857
2858 /* Support simple overlay manager. */
2859 set_gdbarch_overlay_update (gdbarch, simple_overlay_update);
2860 set_gdbarch_char_signed (gdbarch, 0);
2861
2862 if (tdesc_data != nullptr)
2863 {
2864 set_gdbarch_num_regs (gdbarch, (num_regs + 1));
2865 tdesc_use_registers (gdbarch, info.target_desc, std::move (tdesc_data));
2866 set_gdbarch_register_type (gdbarch, csky_register_type);
2867 set_gdbarch_register_reggroup_p (gdbarch,
2868 csky_register_reggroup_p);
2869 }
2870
2871 if (tdep->fv_pseudo_registers_count)
2872 {
2873 set_gdbarch_num_pseudo_regs (gdbarch,
2874 tdep->fv_pseudo_registers_count);
2875 set_gdbarch_pseudo_register_read (gdbarch,
2876 csky_pseudo_register_read);
2877 set_gdbarch_deprecated_pseudo_register_write
2878 (gdbarch, csky_pseudo_register_write);
2879 set_tdesc_pseudo_register_name (gdbarch, csky_pseudo_register_name);
2880 }
2881
2882 return gdbarch;
2883 }
2884
2885 void _initialize_csky_tdep ();
2886 void
2887 _initialize_csky_tdep ()
2888 {
2889
2890 gdbarch_register (bfd_arch_csky, csky_gdbarch_init);
2891
2892 csky_init_reggroup ();
2893
2894 /* Allow debugging this file's internals. */
2895 add_setshow_boolean_cmd ("csky", class_maintenance, &csky_debug,
2896 _("Set C-Sky debugging."),
2897 _("Show C-Sky debugging."),
2898 _("When on, C-Sky specific debugging is enabled."),
2899 NULL,
2900 NULL,
2901 &setdebuglist, &showdebuglist);
2902 }
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