sim/m32r/cpu.h

   1 /* CPU family header for m32rbf.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifndef CPU_M32RBF_H
  26 #define CPU_M32RBF_H
  27
  28 /* Maximum number of instructions that are fetched at a time.
  29    This is for LIW type instructions sets (e.g. m32r).  */
  30 #define MAX_LIW_INSNS 2
  31
  32 /* Maximum number of instructions that can be executed in parallel.  */
  33 #define MAX_PARALLEL_INSNS 1
  34
  35 /* CPU state information.  */
  36 typedef struct {
  37   /* Hardware elements.  */
  38   struct {
  39   /* program counter */
  40   USI h_pc;
  41 #define GET_H_PC() CPU (h_pc)
  42 #define SET_H_PC(x) (CPU (h_pc) = (x))
  43   /* general registers */
  44   SI h_gr[16];
  45 #define GET_H_GR(a1) CPU (h_gr)[a1]
  46 #define SET_H_GR(a1, x) (CPU (h_gr)[a1] = (x))
  47   /* control registers */
  48   USI h_cr[16];
  49 /* GET_H_CR macro user-written */
  50 /* SET_H_CR macro user-written */
  51   /* accumulator */
  52   DI h_accum;
  53 /* GET_H_ACCUM macro user-written */
  54 /* SET_H_ACCUM macro user-written */
  55 /* start-sanitize-m32rx */
  56   /* accumulators */
  57   DI h_accums[2];
  58 /* end-sanitize-m32rx */
  59 /* start-sanitize-m32rx */
  60 /* GET_H_ACCUMS macro user-written */
  61 /* SET_H_ACCUMS macro user-written */
  62 /* end-sanitize-m32rx */
  63   /* condition bit */
  64   BI h_cond;
  65 #define GET_H_COND() CPU (h_cond)
  66 #define SET_H_COND(x) (CPU (h_cond) = (x))
  67   /* psw part of psw */
  68   UQI h_psw;
  69 /* GET_H_PSW macro user-written */
  70 /* SET_H_PSW macro user-written */
  71   /* backup psw */
  72   UQI h_bpsw;
  73 #define GET_H_BPSW() CPU (h_bpsw)
  74 #define SET_H_BPSW(x) (CPU (h_bpsw) = (x))
  75   /* backup bpsw */
  76   UQI h_bbpsw;
  77 #define GET_H_BBPSW() CPU (h_bbpsw)
  78 #define SET_H_BBPSW(x) (CPU (h_bbpsw) = (x))
  79   /* lock */
  80   BI h_lock;
  81 #define GET_H_LOCK() CPU (h_lock)
  82 #define SET_H_LOCK(x) (CPU (h_lock) = (x))
  83   } hardware;
  84 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
  85 } M32RBF_CPU_DATA;
  86
  87 /* Cover fns for register access.  */
  88 USI m32rbf_h_pc_get (SIM_CPU *);
  89 void m32rbf_h_pc_set (SIM_CPU *, USI);
  90 SI m32rbf_h_gr_get (SIM_CPU *, UINT);
  91 void m32rbf_h_gr_set (SIM_CPU *, UINT, SI);
  92 USI m32rbf_h_cr_get (SIM_CPU *, UINT);
  93 void m32rbf_h_cr_set (SIM_CPU *, UINT, USI);
  94 DI m32rbf_h_accum_get (SIM_CPU *);
  95 void m32rbf_h_accum_set (SIM_CPU *, DI);
  96 DI m32rbf_h_accums_get (SIM_CPU *, UINT);
  97 void m32rbf_h_accums_set (SIM_CPU *, UINT, DI);
  98 BI m32rbf_h_cond_get (SIM_CPU *);
  99 void m32rbf_h_cond_set (SIM_CPU *, BI);
 100 UQI m32rbf_h_psw_get (SIM_CPU *);
 101 void m32rbf_h_psw_set (SIM_CPU *, UQI);
 102 UQI m32rbf_h_bpsw_get (SIM_CPU *);
 103 void m32rbf_h_bpsw_set (SIM_CPU *, UQI);
 104 UQI m32rbf_h_bbpsw_get (SIM_CPU *);
 105 void m32rbf_h_bbpsw_set (SIM_CPU *, UQI);
 106 BI m32rbf_h_lock_get (SIM_CPU *);
 107 void m32rbf_h_lock_set (SIM_CPU *, BI);
 108
 109 /* These must be hand-written.  */
 110 extern CPUREG_FETCH_FN m32rbf_fetch_register;
 111 extern CPUREG_STORE_FN m32rbf_store_register;
 112
 113 typedef struct {
 114   UINT h_gr;
 115 } MODEL_M32R_D_DATA;
 116
 117 typedef struct {
 118   int empty;
 119 } MODEL_TEST_DATA;
 120
 121 union sem_fields {
 122     struct { /* empty sformat for unspecified field list */
 123       int empty;
 124     } fmt_empty;
 125     struct { /* e.g. add $dr,$sr */
 126       SI * i_dr;
 127       SI * i_sr;
 128       unsigned char in_dr;
 129       unsigned char in_sr;
 130       unsigned char out_dr;
 131     } fmt_add;
 132     struct { /* e.g. add3 $dr,$sr,$hash$slo16 */
 133       INT f_simm16;
 134       SI * i_sr;
 135       SI * i_dr;
 136       unsigned char in_sr;
 137       unsigned char out_dr;
 138     } fmt_add3;
 139     struct { /* e.g. and3 $dr,$sr,$uimm16 */
 140       UINT f_uimm16;
 141       SI * i_sr;
 142       SI * i_dr;
 143       unsigned char in_sr;
 144       unsigned char out_dr;
 145     } fmt_and3;
 146     struct { /* e.g. or3 $dr,$sr,$hash$ulo16 */
 147       UINT f_uimm16;
 148       SI * i_sr;
 149       SI * i_dr;
 150       unsigned char in_sr;
 151       unsigned char out_dr;
 152     } fmt_or3;
 153     struct { /* e.g. addi $dr,$simm8 */
 154       INT f_simm8;
 155       SI * i_dr;
 156       unsigned char in_dr;
 157       unsigned char out_dr;
 158     } fmt_addi;
 159     struct { /* e.g. addv $dr,$sr */
 160       SI * i_dr;
 161       SI * i_sr;
 162       unsigned char in_dr;
 163       unsigned char in_sr;
 164       unsigned char out_dr;
 165     } fmt_addv;
 166     struct { /* e.g. addv3 $dr,$sr,$simm16 */
 167       INT f_simm16;
 168       SI * i_sr;
 169       SI * i_dr;
 170       unsigned char in_sr;
 171       unsigned char out_dr;
 172     } fmt_addv3;
 173     struct { /* e.g. addx $dr,$sr */
 174       SI * i_dr;
 175       SI * i_sr;
 176       unsigned char in_dr;
 177       unsigned char in_sr;
 178       unsigned char out_dr;
 179     } fmt_addx;
 180     struct { /* e.g. cmp $src1,$src2 */
 181       SI * i_src1;
 182       SI * i_src2;
 183       unsigned char in_src1;
 184       unsigned char in_src2;
 185     } fmt_cmp;
 186     struct { /* e.g. cmpi $src2,$simm16 */
 187       INT f_simm16;
 188       SI * i_src2;
 189       unsigned char in_src2;
 190     } fmt_cmpi;
 191     struct { /* e.g. div $dr,$sr */
 192       SI * i_dr;
 193       SI * i_sr;
 194       unsigned char in_dr;
 195       unsigned char in_sr;
 196       unsigned char out_dr;
 197     } fmt_div;
 198     struct { /* e.g. ld $dr,@$sr */
 199       SI * i_sr;
 200       SI * i_dr;
 201       unsigned char in_sr;
 202       unsigned char out_dr;
 203     } fmt_ld;
 204     struct { /* e.g. ld $dr,@($slo16,$sr) */
 205       INT f_simm16;
 206       SI * i_sr;
 207       SI * i_dr;
 208       unsigned char in_sr;
 209       unsigned char out_dr;
 210     } fmt_ld_d;
 211     struct { /* e.g. ldb $dr,@$sr */
 212       SI * i_sr;
 213       SI * i_dr;
 214       unsigned char in_sr;
 215       unsigned char out_dr;
 216     } fmt_ldb;
 217     struct { /* e.g. ldb $dr,@($slo16,$sr) */
 218       INT f_simm16;
 219       SI * i_sr;
 220       SI * i_dr;
 221       unsigned char in_sr;
 222       unsigned char out_dr;
 223     } fmt_ldb_d;
 224     struct { /* e.g. ldh $dr,@$sr */
 225       SI * i_sr;
 226       SI * i_dr;
 227       unsigned char in_sr;
 228       unsigned char out_dr;
 229     } fmt_ldh;
 230     struct { /* e.g. ldh $dr,@($slo16,$sr) */
 231       INT f_simm16;
 232       SI * i_sr;
 233       SI * i_dr;
 234       unsigned char in_sr;
 235       unsigned char out_dr;
 236     } fmt_ldh_d;
 237     struct { /* e.g. ld $dr,@$sr+ */
 238       SI * i_sr;
 239       SI * i_dr;
 240       unsigned char in_sr;
 241       unsigned char out_dr;
 242       unsigned char out_sr;
 243     } fmt_ld_plus;
 244     struct { /* e.g. ld24 $dr,$uimm24 */
 245       ADDR i_uimm24;
 246       SI * i_dr;
 247       unsigned char out_dr;
 248     } fmt_ld24;
 249     struct { /* e.g. ldi8 $dr,$simm8 */
 250       INT f_simm8;
 251       SI * i_dr;
 252       unsigned char out_dr;
 253     } fmt_ldi8;
 254     struct { /* e.g. ldi16 $dr,$hash$slo16 */
 255       INT f_simm16;
 256       SI * i_dr;
 257       unsigned char out_dr;
 258     } fmt_ldi16;
 259     struct { /* e.g. lock $dr,@$sr */
 260       SI * i_sr;
 261       SI * i_dr;
 262       unsigned char in_sr;
 263       unsigned char out_dr;
 264     } fmt_lock;
 265     struct { /* e.g. machi $src1,$src2 */
 266       SI * i_src1;
 267       SI * i_src2;
 268       unsigned char in_src1;
 269       unsigned char in_src2;
 270     } fmt_machi;
 271     struct { /* e.g. mulhi $src1,$src2 */
 272       SI * i_src1;
 273       SI * i_src2;
 274       unsigned char in_src1;
 275       unsigned char in_src2;
 276     } fmt_mulhi;
 277     struct { /* e.g. mv $dr,$sr */
 278       SI * i_sr;
 279       SI * i_dr;
 280       unsigned char in_sr;
 281       unsigned char out_dr;
 282     } fmt_mv;
 283     struct { /* e.g. mvfachi $dr */
 284       SI * i_dr;
 285       unsigned char out_dr;
 286     } fmt_mvfachi;
 287     struct { /* e.g. mvfc $dr,$scr */
 288       UINT f_r2;
 289       SI * i_dr;
 290       unsigned char out_dr;
 291     } fmt_mvfc;
 292     struct { /* e.g. mvtachi $src1 */
 293       SI * i_src1;
 294       unsigned char in_src1;
 295     } fmt_mvtachi;
 296     struct { /* e.g. mvtc $sr,$dcr */
 297       UINT f_r1;
 298       SI * i_sr;
 299       unsigned char in_sr;
 300     } fmt_mvtc;
 301     struct { /* e.g. nop */
 302       int empty;
 303     } fmt_nop;
 304     struct { /* e.g. rac */
 305       int empty;
 306     } fmt_rac;
 307     struct { /* e.g. seth $dr,$hash$hi16 */
 308       UINT f_hi16;
 309       SI * i_dr;
 310       unsigned char out_dr;
 311     } fmt_seth;
 312     struct { /* e.g. sll3 $dr,$sr,$simm16 */
 313       INT f_simm16;
 314       SI * i_sr;
 315       SI * i_dr;
 316       unsigned char in_sr;
 317       unsigned char out_dr;
 318     } fmt_sll3;
 319     struct { /* e.g. slli $dr,$uimm5 */
 320       UINT f_uimm5;
 321       SI * i_dr;
 322       unsigned char in_dr;
 323       unsigned char out_dr;
 324     } fmt_slli;
 325     struct { /* e.g. st $src1,@$src2 */
 326       SI * i_src1;
 327       SI * i_src2;
 328       unsigned char in_src1;
 329       unsigned char in_src2;
 330     } fmt_st;
 331     struct { /* e.g. st $src1,@($slo16,$src2) */
 332       INT f_simm16;
 333       SI * i_src1;
 334       SI * i_src2;
 335       unsigned char in_src1;
 336       unsigned char in_src2;
 337     } fmt_st_d;
 338     struct { /* e.g. stb $src1,@$src2 */
 339       SI * i_src1;
 340       SI * i_src2;
 341       unsigned char in_src1;
 342       unsigned char in_src2;
 343     } fmt_stb;
 344     struct { /* e.g. stb $src1,@($slo16,$src2) */
 345       INT f_simm16;
 346       SI * i_src1;
 347       SI * i_src2;
 348       unsigned char in_src1;
 349       unsigned char in_src2;
 350     } fmt_stb_d;
 351     struct { /* e.g. sth $src1,@$src2 */
 352       SI * i_src1;
 353       SI * i_src2;
 354       unsigned char in_src1;
 355       unsigned char in_src2;
 356     } fmt_sth;
 357     struct { /* e.g. sth $src1,@($slo16,$src2) */
 358       INT f_simm16;
 359       SI * i_src1;
 360       SI * i_src2;
 361       unsigned char in_src1;
 362       unsigned char in_src2;
 363     } fmt_sth_d;
 364     struct { /* e.g. st $src1,@+$src2 */
 365       SI * i_src1;
 366       SI * i_src2;
 367       unsigned char in_src1;
 368       unsigned char in_src2;
 369       unsigned char out_src2;
 370     } fmt_st_plus;
 371     struct { /* e.g. unlock $src1,@$src2 */
 372       SI * i_src1;
 373       SI * i_src2;
 374       unsigned char in_src1;
 375       unsigned char in_src2;
 376     } fmt_unlock;
 377   /* cti insns, kept separately so addr_cache is in fixed place */
 378   struct {
 379     union {
 380     struct { /* e.g. bc.s $disp8 */
 381       IADDR i_disp8;
 382     } fmt_bc8;
 383     struct { /* e.g. bc.l $disp24 */
 384       IADDR i_disp24;
 385     } fmt_bc24;
 386     struct { /* e.g. beq $src1,$src2,$disp16 */
 387       IADDR i_disp16;
 388       SI * i_src1;
 389       SI * i_src2;
 390       unsigned char in_src1;
 391       unsigned char in_src2;
 392     } fmt_beq;
 393     struct { /* e.g. beqz $src2,$disp16 */
 394       IADDR i_disp16;
 395       SI * i_src2;
 396       unsigned char in_src2;
 397     } fmt_beqz;
 398     struct { /* e.g. bl.s $disp8 */
 399       IADDR i_disp8;
 400       unsigned char out_h_gr_14;
 401     } fmt_bl8;
 402     struct { /* e.g. bl.l $disp24 */
 403       IADDR i_disp24;
 404       unsigned char out_h_gr_14;
 405     } fmt_bl24;
 406     struct { /* e.g. bra.s $disp8 */
 407       IADDR i_disp8;
 408     } fmt_bra8;
 409     struct { /* e.g. bra.l $disp24 */
 410       IADDR i_disp24;
 411     } fmt_bra24;
 412     struct { /* e.g. jl $sr */
 413       SI * i_sr;
 414       unsigned char in_sr;
 415       unsigned char out_h_gr_14;
 416     } fmt_jl;
 417     struct { /* e.g. jmp $sr */
 418       SI * i_sr;
 419       unsigned char in_sr;
 420     } fmt_jmp;
 421     struct { /* e.g. rte */
 422       int empty;
 423     } fmt_rte;
 424     struct { /* e.g. trap $uimm4 */
 425       UINT f_uimm4;
 426     } fmt_trap;
 427     } fields;
 428 #if WITH_SCACHE_PBB
 429     SEM_PC addr_cache;
 430 #endif
 431   } cti;
 432 #if WITH_SCACHE_PBB
 433   /* Writeback handler.  */
 434   struct {
 435     /* Pointer to argbuf entry for insn whose results need writing back.  */
 436     const struct argbuf *abuf;
 437   } write;
 438   /* x-before handler */
 439   struct {
 440     /*const SCACHE *insns[MAX_PARALLEL_INSNS];*/
 441     int first_p;
 442   } before;
 443   /* x-after handler */
 444   struct {
 445     int empty;
 446   } after;
 447   /* This entry is used to terminate each pbb.  */
 448   struct {
 449     /* Number of insns in pbb.  */
 450     int insn_count;
 451     /* Next pbb to execute.  */
 452     SCACHE *next;
 453   } chain;
 454 #endif
 455 };
 456
 457 /* The ARGBUF struct.  */
 458 struct argbuf {
 459   /* These are the baseclass definitions.  */
 460   IADDR addr;
 461   const IDESC *idesc;
 462   char trace_p;
 463   char profile_p;
 464   /* cpu specific data follows */
 465   union sem semantic;
 466   int written;
 467   union sem_fields fields;
 468 };
 469
 470 /* A cached insn.
 471
 472    ??? SCACHE used to contain more than just argbuf.  We could delete the
 473    type entirely and always just use ARGBUF, but for future concerns and as
 474    a level of abstraction it is left in.  */
 475
 476 struct scache {
 477   struct argbuf argbuf;
 478 };
 479
 480 /* Macros to simplify extraction, reading and semantic code.
 481    These define and assign the local vars that contain the insn's fields.  */
 482
 483 #define EXTRACT_IFMT_EMPTY_VARS \
 484   /* Instruction fields.  */ \
 485   unsigned int length;
 486 #define EXTRACT_IFMT_EMPTY_CODE \
 487   length = 0; \
 488
 489 #define EXTRACT_IFMT_ADD_VARS \
 490   /* Instruction fields.  */ \
 491   UINT f_op1; \
 492   UINT f_r1; \
 493   UINT f_op2; \
 494   UINT f_r2; \
 495   unsigned int length;
 496 #define EXTRACT_IFMT_ADD_CODE \
 497   length = 2; \
 498   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 499   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 500   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 501   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 502
 503 #define EXTRACT_IFMT_ADD3_VARS \
 504   /* Instruction fields.  */ \
 505   UINT f_op1; \
 506   UINT f_r1; \
 507   UINT f_op2; \
 508   UINT f_r2; \
 509   INT f_simm16; \
 510   unsigned int length;
 511 #define EXTRACT_IFMT_ADD3_CODE \
 512   length = 4; \
 513   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 514   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 515   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 516   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 517   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 518
 519 #define EXTRACT_IFMT_AND3_VARS \
 520   /* Instruction fields.  */ \
 521   UINT f_op1; \
 522   UINT f_r1; \
 523   UINT f_op2; \
 524   UINT f_r2; \
 525   UINT f_uimm16; \
 526   unsigned int length;
 527 #define EXTRACT_IFMT_AND3_CODE \
 528   length = 4; \
 529   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 530   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 531   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 532   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 533   f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
 534
 535 #define EXTRACT_IFMT_OR3_VARS \
 536   /* Instruction fields.  */ \
 537   UINT f_op1; \
 538   UINT f_r1; \
 539   UINT f_op2; \
 540   UINT f_r2; \
 541   UINT f_uimm16; \
 542   unsigned int length;
 543 #define EXTRACT_IFMT_OR3_CODE \
 544   length = 4; \
 545   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 546   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 547   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 548   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 549   f_uimm16 = EXTRACT_UINT (insn, 32, 16, 16); \
 550
 551 #define EXTRACT_IFMT_ADDI_VARS \
 552   /* Instruction fields.  */ \
 553   UINT f_op1; \
 554   UINT f_r1; \
 555   INT f_simm8; \
 556   unsigned int length;
 557 #define EXTRACT_IFMT_ADDI_CODE \
 558   length = 2; \
 559   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 560   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 561   f_simm8 = EXTRACT_INT (insn, 16, 8, 8); \
 562
 563 #define EXTRACT_IFMT_ADDV3_VARS \
 564   /* Instruction fields.  */ \
 565   UINT f_op1; \
 566   UINT f_r1; \
 567   UINT f_op2; \
 568   UINT f_r2; \
 569   INT f_simm16; \
 570   unsigned int length;
 571 #define EXTRACT_IFMT_ADDV3_CODE \
 572   length = 4; \
 573   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 574   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 575   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 576   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 577   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 578
 579 #define EXTRACT_IFMT_BC8_VARS \
 580   /* Instruction fields.  */ \
 581   UINT f_op1; \
 582   UINT f_r1; \
 583   SI f_disp8; \
 584   unsigned int length;
 585 #define EXTRACT_IFMT_BC8_CODE \
 586   length = 2; \
 587   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 588   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 589   f_disp8 = ((((EXTRACT_INT (insn, 16, 8, 8)) << (2))) + (((pc) & (-4)))); \
 590
 591 #define EXTRACT_IFMT_BC24_VARS \
 592   /* Instruction fields.  */ \
 593   UINT f_op1; \
 594   UINT f_r1; \
 595   SI f_disp24; \
 596   unsigned int length;
 597 #define EXTRACT_IFMT_BC24_CODE \
 598   length = 4; \
 599   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 600   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 601   f_disp24 = ((((EXTRACT_INT (insn, 32, 8, 24)) << (2))) + (pc)); \
 602
 603 #define EXTRACT_IFMT_BEQ_VARS \
 604   /* Instruction fields.  */ \
 605   UINT f_op1; \
 606   UINT f_r1; \
 607   UINT f_op2; \
 608   UINT f_r2; \
 609   SI f_disp16; \
 610   unsigned int length;
 611 #define EXTRACT_IFMT_BEQ_CODE \
 612   length = 4; \
 613   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 614   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 615   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 616   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 617   f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
 618
 619 #define EXTRACT_IFMT_BEQZ_VARS \
 620   /* Instruction fields.  */ \
 621   UINT f_op1; \
 622   UINT f_r1; \
 623   UINT f_op2; \
 624   UINT f_r2; \
 625   SI f_disp16; \
 626   unsigned int length;
 627 #define EXTRACT_IFMT_BEQZ_CODE \
 628   length = 4; \
 629   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 630   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 631   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 632   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 633   f_disp16 = ((((EXTRACT_INT (insn, 32, 16, 16)) << (2))) + (pc)); \
 634
 635 #define EXTRACT_IFMT_CMP_VARS \
 636   /* Instruction fields.  */ \
 637   UINT f_op1; \
 638   UINT f_r1; \
 639   UINT f_op2; \
 640   UINT f_r2; \
 641   unsigned int length;
 642 #define EXTRACT_IFMT_CMP_CODE \
 643   length = 2; \
 644   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 645   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 646   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 647   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 648
 649 #define EXTRACT_IFMT_CMPI_VARS \
 650   /* Instruction fields.  */ \
 651   UINT f_op1; \
 652   UINT f_r1; \
 653   UINT f_op2; \
 654   UINT f_r2; \
 655   INT f_simm16; \
 656   unsigned int length;
 657 #define EXTRACT_IFMT_CMPI_CODE \
 658   length = 4; \
 659   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 660   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 661   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 662   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 663   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 664
 665 #define EXTRACT_IFMT_DIV_VARS \
 666   /* Instruction fields.  */ \
 667   UINT f_op1; \
 668   UINT f_r1; \
 669   UINT f_op2; \
 670   UINT f_r2; \
 671   INT f_simm16; \
 672   unsigned int length;
 673 #define EXTRACT_IFMT_DIV_CODE \
 674   length = 4; \
 675   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 676   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 677   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 678   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 679   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 680
 681 #define EXTRACT_IFMT_JL_VARS \
 682   /* Instruction fields.  */ \
 683   UINT f_op1; \
 684   UINT f_r1; \
 685   UINT f_op2; \
 686   UINT f_r2; \
 687   unsigned int length;
 688 #define EXTRACT_IFMT_JL_CODE \
 689   length = 2; \
 690   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 691   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 692   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 693   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 694
 695 #define EXTRACT_IFMT_LD24_VARS \
 696   /* Instruction fields.  */ \
 697   UINT f_op1; \
 698   UINT f_r1; \
 699   UINT f_uimm24; \
 700   unsigned int length;
 701 #define EXTRACT_IFMT_LD24_CODE \
 702   length = 4; \
 703   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 704   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 705   f_uimm24 = EXTRACT_UINT (insn, 32, 8, 24); \
 706
 707 #define EXTRACT_IFMT_LDI16_VARS \
 708   /* Instruction fields.  */ \
 709   UINT f_op1; \
 710   UINT f_r1; \
 711   UINT f_op2; \
 712   UINT f_r2; \
 713   INT f_simm16; \
 714   unsigned int length;
 715 #define EXTRACT_IFMT_LDI16_CODE \
 716   length = 4; \
 717   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 718   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 719   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 720   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 721   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 722
 723 #define EXTRACT_IFMT_MVFACHI_VARS \
 724   /* Instruction fields.  */ \
 725   UINT f_op1; \
 726   UINT f_r1; \
 727   UINT f_op2; \
 728   UINT f_r2; \
 729   unsigned int length;
 730 #define EXTRACT_IFMT_MVFACHI_CODE \
 731   length = 2; \
 732   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 733   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 734   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 735   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 736
 737 #define EXTRACT_IFMT_MVFC_VARS \
 738   /* Instruction fields.  */ \
 739   UINT f_op1; \
 740   UINT f_r1; \
 741   UINT f_op2; \
 742   UINT f_r2; \
 743   unsigned int length;
 744 #define EXTRACT_IFMT_MVFC_CODE \
 745   length = 2; \
 746   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 747   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 748   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 749   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 750
 751 #define EXTRACT_IFMT_MVTACHI_VARS \
 752   /* Instruction fields.  */ \
 753   UINT f_op1; \
 754   UINT f_r1; \
 755   UINT f_op2; \
 756   UINT f_r2; \
 757   unsigned int length;
 758 #define EXTRACT_IFMT_MVTACHI_CODE \
 759   length = 2; \
 760   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 761   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 762   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 763   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 764
 765 #define EXTRACT_IFMT_MVTC_VARS \
 766   /* Instruction fields.  */ \
 767   UINT f_op1; \
 768   UINT f_r1; \
 769   UINT f_op2; \
 770   UINT f_r2; \
 771   unsigned int length;
 772 #define EXTRACT_IFMT_MVTC_CODE \
 773   length = 2; \
 774   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 775   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 776   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 777   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 778
 779 #define EXTRACT_IFMT_NOP_VARS \
 780   /* Instruction fields.  */ \
 781   UINT f_op1; \
 782   UINT f_r1; \
 783   UINT f_op2; \
 784   UINT f_r2; \
 785   unsigned int length;
 786 #define EXTRACT_IFMT_NOP_CODE \
 787   length = 2; \
 788   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 789   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 790   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 791   f_r2 = EXTRACT_UINT (insn, 16, 12, 4); \
 792
 793 #define EXTRACT_IFMT_SETH_VARS \
 794   /* Instruction fields.  */ \
 795   UINT f_op1; \
 796   UINT f_r1; \
 797   UINT f_op2; \
 798   UINT f_r2; \
 799   UINT f_hi16; \
 800   unsigned int length;
 801 #define EXTRACT_IFMT_SETH_CODE \
 802   length = 4; \
 803   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 804   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 805   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 806   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 807   f_hi16 = EXTRACT_UINT (insn, 32, 16, 16); \
 808
 809 #define EXTRACT_IFMT_SLLI_VARS \
 810   /* Instruction fields.  */ \
 811   UINT f_op1; \
 812   UINT f_r1; \
 813   UINT f_shift_op2; \
 814   UINT f_uimm5; \
 815   unsigned int length;
 816 #define EXTRACT_IFMT_SLLI_CODE \
 817   length = 2; \
 818   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 819   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 820   f_shift_op2 = EXTRACT_UINT (insn, 16, 8, 3); \
 821   f_uimm5 = EXTRACT_UINT (insn, 16, 11, 5); \
 822
 823 #define EXTRACT_IFMT_ST_D_VARS \
 824   /* Instruction fields.  */ \
 825   UINT f_op1; \
 826   UINT f_r1; \
 827   UINT f_op2; \
 828   UINT f_r2; \
 829   INT f_simm16; \
 830   unsigned int length;
 831 #define EXTRACT_IFMT_ST_D_CODE \
 832   length = 4; \
 833   f_op1 = EXTRACT_UINT (insn, 32, 0, 4); \
 834   f_r1 = EXTRACT_UINT (insn, 32, 4, 4); \
 835   f_op2 = EXTRACT_UINT (insn, 32, 8, 4); \
 836   f_r2 = EXTRACT_UINT (insn, 32, 12, 4); \
 837   f_simm16 = EXTRACT_INT (insn, 32, 16, 16); \
 838
 839 #define EXTRACT_IFMT_TRAP_VARS \
 840   /* Instruction fields.  */ \
 841   UINT f_op1; \
 842   UINT f_r1; \
 843   UINT f_op2; \
 844   UINT f_uimm4; \
 845   unsigned int length;
 846 #define EXTRACT_IFMT_TRAP_CODE \
 847   length = 2; \
 848   f_op1 = EXTRACT_UINT (insn, 16, 0, 4); \
 849   f_r1 = EXTRACT_UINT (insn, 16, 4, 4); \
 850   f_op2 = EXTRACT_UINT (insn, 16, 8, 4); \
 851   f_uimm4 = EXTRACT_UINT (insn, 16, 12, 4); \
 852
 853 /* Collection of various things for the trace handler to use.  */
 854
 855 typedef struct trace_record {
 856   IADDR pc;
 857   /* FIXME:wip */
 858 } TRACE_RECORD;
 859
 860 #endif /* CPU_M32RBF_H */