sim/m32r/decode.h

   1 /* Decode header for m32rbf.
   2
   3 THIS FILE IS MACHINE GENERATED WITH CGEN.
   4
   5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
   6
   7 This file is part of the GNU Simulators.
   8
   9 This program is free software; you can redistribute it and/or modify
  10 it under the terms of the GNU General Public License as published by
  11 the Free Software Foundation; either version 2, or (at your option)
  12 any later version.
  13
  14 This program is distributed in the hope that it will be useful,
  15 but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17 GNU General Public License for more details.
  18
  19 You should have received a copy of the GNU General Public License along
  20 with this program; if not, write to the Free Software Foundation, Inc.,
  21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  22
  23 */
  24
  25 #ifndef M32RBF_DECODE_H
  26 #define M32RBF_DECODE_H
  27
  28 /* Run-time computed instruction descriptor.  */
  29
  30 struct idesc {
  31 #if WITH_SEM_SWITCH_FULL
  32 #ifdef __GNUC__
  33   void *sem_full_lab;
  34 #endif
  35 #else
  36   SEMANTIC_FN *sem_full;
  37 #endif
  38
  39 #if WITH_SEM_SWITCH_FAST
  40 #ifdef __GNUC__
  41   void *sem_fast_lab;
  42 #endif
  43 #else
  44   SEMANTIC_FN *sem_fast;
  45 #endif
  46
  47   /* Instruction number (index in IDESC table, profile table).
  48      Also used to switch on in non-gcc semantic switches.  */
  49   int num;
  50
  51   /* opcode table data */
  52   const CGEN_INSN *opcode;
  53
  54   /* profiling/modelling support */
  55   const INSN_TIMING *timing;
  56 };
  57
  58 extern const IDESC *m32rbf_decode (SIM_CPU *, IADDR,
  59                                   CGEN_INSN_INT, CGEN_INSN_INT,
  60                                   ARGBUF *);
  61
  62 /* Enum declaration for instructions in cpu family m32rbf.  */
  63 typedef enum m32rbf_insn_type {
  64   M32RBF_INSN_X_INVALID, M32RBF_INSN_X_AFTER, M32RBF_INSN_X_BEFORE, M32RBF_INSN_X_CTI_CHAIN
  65  , M32RBF_INSN_X_CHAIN, M32RBF_INSN_X_BEGIN, M32RBF_INSN_ADD, M32RBF_INSN_ADD3
  66  , M32RBF_INSN_AND, M32RBF_INSN_AND3, M32RBF_INSN_OR, M32RBF_INSN_OR3
  67  , M32RBF_INSN_XOR, M32RBF_INSN_XOR3, M32RBF_INSN_ADDI, M32RBF_INSN_ADDV
  68  , M32RBF_INSN_ADDV3, M32RBF_INSN_ADDX, M32RBF_INSN_BC8, M32RBF_INSN_BC24
  69  , M32RBF_INSN_BEQ, M32RBF_INSN_BEQZ, M32RBF_INSN_BGEZ, M32RBF_INSN_BGTZ
  70  , M32RBF_INSN_BLEZ, M32RBF_INSN_BLTZ, M32RBF_INSN_BNEZ, M32RBF_INSN_BL8
  71  , M32RBF_INSN_BL24, M32RBF_INSN_BNC8, M32RBF_INSN_BNC24, M32RBF_INSN_BNE
  72  , M32RBF_INSN_BRA8, M32RBF_INSN_BRA24, M32RBF_INSN_CMP, M32RBF_INSN_CMPI
  73  , M32RBF_INSN_CMPU, M32RBF_INSN_CMPUI, M32RBF_INSN_DIV, M32RBF_INSN_DIVU
  74  , M32RBF_INSN_REM, M32RBF_INSN_REMU, M32RBF_INSN_JL, M32RBF_INSN_JMP
  75  , M32RBF_INSN_LD, M32RBF_INSN_LD_D, M32RBF_INSN_LDB, M32RBF_INSN_LDB_D
  76  , M32RBF_INSN_LDH, M32RBF_INSN_LDH_D, M32RBF_INSN_LDUB, M32RBF_INSN_LDUB_D
  77  , M32RBF_INSN_LDUH, M32RBF_INSN_LDUH_D, M32RBF_INSN_LD_PLUS, M32RBF_INSN_LD24
  78  , M32RBF_INSN_LDI8, M32RBF_INSN_LDI16, M32RBF_INSN_LOCK, M32RBF_INSN_MACHI
  79  , M32RBF_INSN_MACLO, M32RBF_INSN_MACWHI, M32RBF_INSN_MACWLO, M32RBF_INSN_MUL
  80  , M32RBF_INSN_MULHI, M32RBF_INSN_MULLO, M32RBF_INSN_MULWHI, M32RBF_INSN_MULWLO
  81  , M32RBF_INSN_MV, M32RBF_INSN_MVFACHI, M32RBF_INSN_MVFACLO, M32RBF_INSN_MVFACMI
  82  , M32RBF_INSN_MVFC, M32RBF_INSN_MVTACHI, M32RBF_INSN_MVTACLO, M32RBF_INSN_MVTC
  83  , M32RBF_INSN_NEG, M32RBF_INSN_NOP, M32RBF_INSN_NOT, M32RBF_INSN_RAC
  84  , M32RBF_INSN_RACH, M32RBF_INSN_RTE, M32RBF_INSN_SETH, M32RBF_INSN_SLL
  85  , M32RBF_INSN_SLL3, M32RBF_INSN_SLLI, M32RBF_INSN_SRA, M32RBF_INSN_SRA3
  86  , M32RBF_INSN_SRAI, M32RBF_INSN_SRL, M32RBF_INSN_SRL3, M32RBF_INSN_SRLI
  87  , M32RBF_INSN_ST, M32RBF_INSN_ST_D, M32RBF_INSN_STB, M32RBF_INSN_STB_D
  88  , M32RBF_INSN_STH, M32RBF_INSN_STH_D, M32RBF_INSN_ST_PLUS, M32RBF_INSN_ST_MINUS
  89  , M32RBF_INSN_SUB, M32RBF_INSN_SUBV, M32RBF_INSN_SUBX, M32RBF_INSN_TRAP
  90  , M32RBF_INSN_UNLOCK, M32RBF_INSN_MAX
  91 } M32RBF_INSN_TYPE;
  92
  93 #if ! WITH_SEM_SWITCH_FULL
  94 #define SEMFULL(fn) extern SEMANTIC_FN CONCAT3 (m32rbf,_sem_,fn);
  95 #else
  96 #define SEMFULL(fn)
  97 #endif
  98
  99 #if ! WITH_SEM_SWITCH_FAST
 100 #define SEMFAST(fn) extern SEMANTIC_FN CONCAT3 (m32rbf,_semf_,fn);
 101 #else
 102 #define SEMFAST(fn)
 103 #endif
 104
 105 #define SEM(fn) SEMFULL (fn) SEMFAST (fn)
 106
 107 /* The function version of the before/after handlers is always needed,
 108    so we always want the SEMFULL declaration of them.  */
 109 extern SEMANTIC_FN CONCAT3 (m32rbf,_sem_,x_before);
 110 extern SEMANTIC_FN CONCAT3 (m32rbf,_sem_,x_after);
 111
 112 SEM (x_invalid)
 113 SEM (x_after)
 114 SEM (x_before)
 115 SEM (x_cti_chain)
 116 SEM (x_chain)
 117 SEM (x_begin)
 118 SEM (add)
 119 SEM (add3)
 120 SEM (and)
 121 SEM (and3)
 122 SEM (or)
 123 SEM (or3)
 124 SEM (xor)
 125 SEM (xor3)
 126 SEM (addi)
 127 SEM (addv)
 128 SEM (addv3)
 129 SEM (addx)
 130 SEM (bc8)
 131 SEM (bc24)
 132 SEM (beq)
 133 SEM (beqz)
 134 SEM (bgez)
 135 SEM (bgtz)
 136 SEM (blez)
 137 SEM (bltz)
 138 SEM (bnez)
 139 SEM (bl8)
 140 SEM (bl24)
 141 SEM (bnc8)
 142 SEM (bnc24)
 143 SEM (bne)
 144 SEM (bra8)
 145 SEM (bra24)
 146 SEM (cmp)
 147 SEM (cmpi)
 148 SEM (cmpu)
 149 SEM (cmpui)
 150 SEM (div)
 151 SEM (divu)
 152 SEM (rem)
 153 SEM (remu)
 154 SEM (jl)
 155 SEM (jmp)
 156 SEM (ld)
 157 SEM (ld_d)
 158 SEM (ldb)
 159 SEM (ldb_d)
 160 SEM (ldh)
 161 SEM (ldh_d)
 162 SEM (ldub)
 163 SEM (ldub_d)
 164 SEM (lduh)
 165 SEM (lduh_d)
 166 SEM (ld_plus)
 167 SEM (ld24)
 168 SEM (ldi8)
 169 SEM (ldi16)
 170 SEM (lock)
 171 SEM (machi)
 172 SEM (maclo)
 173 SEM (macwhi)
 174 SEM (macwlo)
 175 SEM (mul)
 176 SEM (mulhi)
 177 SEM (mullo)
 178 SEM (mulwhi)
 179 SEM (mulwlo)
 180 SEM (mv)
 181 SEM (mvfachi)
 182 SEM (mvfaclo)
 183 SEM (mvfacmi)
 184 SEM (mvfc)
 185 SEM (mvtachi)
 186 SEM (mvtaclo)
 187 SEM (mvtc)
 188 SEM (neg)
 189 SEM (nop)
 190 SEM (not)
 191 SEM (rac)
 192 SEM (rach)
 193 SEM (rte)
 194 SEM (seth)
 195 SEM (sll)
 196 SEM (sll3)
 197 SEM (slli)
 198 SEM (sra)
 199 SEM (sra3)
 200 SEM (srai)
 201 SEM (srl)
 202 SEM (srl3)
 203 SEM (srli)
 204 SEM (st)
 205 SEM (st_d)
 206 SEM (stb)
 207 SEM (stb_d)
 208 SEM (sth)
 209 SEM (sth_d)
 210 SEM (st_plus)
 211 SEM (st_minus)
 212 SEM (sub)
 213 SEM (subv)
 214 SEM (subx)
 215 SEM (trap)
 216 SEM (unlock)
 217
 218 #undef SEMFULL
 219 #undef SEMFAST
 220 #undef SEM
 221
 222 /* Function unit handlers (user written).  */
 223
 224 extern int m32rbf_model_m32r_d_u_store (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
 225 extern int m32rbf_model_m32r_d_u_load (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/, INT /*dr*/);
 226 extern int m32rbf_model_m32r_d_u_cti (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/);
 227 extern int m32rbf_model_m32r_d_u_mac (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
 228 extern int m32rbf_model_m32r_d_u_cmp (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*src1*/, INT /*src2*/);
 229 extern int m32rbf_model_m32r_d_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/, INT /*sr*/, INT /*sr2*/, INT /*dr*/);
 230 extern int m32rbf_model_test_u_exec (SIM_CPU *, const IDESC *, int /*unit_num*/, int /*referenced*/);
 231
 232 /* Profiling before/after handlers (user written) */
 233
 234 extern void m32rbf_model_insn_before (SIM_CPU *, int /*first_p*/);
 235 extern void m32rbf_model_insn_after (SIM_CPU *, int /*last_p*/, int /*cycles*/);
 236
 237 #endif /* M32RBF_DECODE_H */