?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
* "objcopy -O binary" warning tweak, suggested by dmoseley
[binutils-gdb.git] / sim / m32r / decodex.c
blobbc61f5d3a484c14c20add96d76274f7fe6b0cb91
1 /* Simulator instruction decoder for m32rxf.
2
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
4
5 Copyright (C) 1996, 1997, 1998, 1999 Free Software Foundation, Inc.
6
7 This file is part of the GNU Simulators.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
12 any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License along
20 with this program; if not, write to the Free Software Foundation, Inc.,
21 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22
23 */
24
25 #define WANT_CPU m32rxf
26 #define WANT_CPU_M32RXF
27
28 #include "sim-main.h"
29 #include "sim-assert.h"
30
31 #ifdef __GNUC__
32 #define FMT(n)
33 #else
34 #define FMT(n) CONCAT2 (M32RXF_,n) ,
35 #endif
36
37 /* FIXME: Need to review choices for the following. */
38
39 #if WITH_SEM_SWITCH_FULL
40 #define FULL(fn)
41 #else
42 #define FULL(fn) CONCAT3 (m32rxf,_sem_,fn) ,
43 #endif
44
45 #if WITH_FAST
46 #if WITH_SEM_SWITCH_FAST
47 #define FAST(fn)
48 #else
49 #define FAST(fn) CONCAT3 (m32rxf,_semf_,fn) , /* f for fast */
50 #endif
51 #else
52 #define FAST(fn)
53 #endif
54
55 /* The instruction descriptor array.
56 This is computed at runtime. Space for it is not malloc'd to save a
57 teensy bit of cpu in the decoder. Moving it to malloc space is trivial
58 but won't be done until necessary (we don't currently support the runtime
59 addition of instructions nor an SMP machine with different cpus). */
60 static IDESC m32rxf_insn_data[M32RXF_INSN_MAX];
61
62 /* Instruction semantic handlers and support.
63 This struct defines the part of an IDESC that can be computed at
64 compile time. */
65
66 struct insn_sem {
67 /* The instruction type (a number that identifies each insn over the
68 entire architecture). */
69 CGEN_INSN_TYPE type;
70
71 /* Index in IDESC table. */
72 int index;
73
74 /* Index in IDESC table of parallel handler. */
75 int par_index;
76
77 /* Index in IDESC table of writeback handler. */
78 int write_index;
79
80 /* Routines to execute the insn.
81 The full version has all features (profiling,tracing) compiled in.
82 The fast version has none of that. */
83 #if ! WITH_SEM_SWITCH_FULL
84 SEMANTIC_FN *sem_full;
85 #endif
86 #if WITH_FAST && ! WITH_SEM_SWITCH_FAST
87 SEMANTIC_FN *sem_fast;
88 #endif
89
90 };
91 /* The INSN_ prefix is not here and is instead part of the `insn' argument
92 to avoid collisions with header files (e.g. `AND' in ansidecl.h). */
93 #define IDX(insn) CONCAT2 (M32RXF_,insn)
94 #define TYPE(insn) CONCAT2 (M32R_,insn)
95
96 /* Insn can't be executed in parallel.
97 Or is that "do NOt Pass to Air defense Radar"? :-) */
98 #define NOPAR (-1)
99
100 /* Commas between elements are contained in the macros.
101 Some of these are conditionally compiled out. */
102
103 static const struct insn_sem m32rxf_insn_sem[] =
104 {
105 { VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), NOPAR, NOPAR, FULL (x_invalid) FAST (x_invalid) },
106 { VIRTUAL_INSN_X_AFTER, IDX (INSN_X_AFTER), NOPAR, NOPAR, FULL (x_after) FAST (x_after) },
107 { VIRTUAL_INSN_X_BEFORE, IDX (INSN_X_BEFORE), NOPAR, NOPAR, FULL (x_before) FAST (x_before) },
108 { VIRTUAL_INSN_X_CTI_CHAIN, IDX (INSN_X_CTI_CHAIN), NOPAR, NOPAR, FULL (x_cti_chain) FAST (x_cti_chain) },
109 { VIRTUAL_INSN_X_CHAIN, IDX (INSN_X_CHAIN), NOPAR, NOPAR, FULL (x_chain) FAST (x_chain) },
110 { VIRTUAL_INSN_X_BEGIN, IDX (INSN_X_BEGIN), NOPAR, NOPAR, FULL (x_begin) FAST (x_begin) },
111 { TYPE (INSN_ADD), IDX (INSN_ADD), IDX (INSN_PAR_ADD), IDX (INSN_WRITE_ADD), FULL (add) FAST (add) },
112 { TYPE (INSN_ADD3), IDX (INSN_ADD3), NOPAR, NOPAR, FULL (add3) FAST (add3) },
113 { TYPE (INSN_AND), IDX (INSN_AND), IDX (INSN_PAR_AND), IDX (INSN_WRITE_AND), FULL (and) FAST (and) },
114 { TYPE (INSN_AND3), IDX (INSN_AND3), NOPAR, NOPAR, FULL (and3) FAST (and3) },
115 { TYPE (INSN_OR), IDX (INSN_OR), IDX (INSN_PAR_OR), IDX (INSN_WRITE_OR), FULL (or) FAST (or) },
116 { TYPE (INSN_OR3), IDX (INSN_OR3), NOPAR, NOPAR, FULL (or3) FAST (or3) },
117 { TYPE (INSN_XOR), IDX (INSN_XOR), IDX (INSN_PAR_XOR), IDX (INSN_WRITE_XOR), FULL (xor) FAST (xor) },
118 { TYPE (INSN_XOR3), IDX (INSN_XOR3), NOPAR, NOPAR, FULL (xor3) FAST (xor3) },
119 { TYPE (INSN_ADDI), IDX (INSN_ADDI), IDX (INSN_PAR_ADDI), IDX (INSN_WRITE_ADDI), FULL (addi) FAST (addi) },
120 { TYPE (INSN_ADDV), IDX (INSN_ADDV), IDX (INSN_PAR_ADDV), IDX (INSN_WRITE_ADDV), FULL (addv) FAST (addv) },
121 { TYPE (INSN_ADDV3), IDX (INSN_ADDV3), NOPAR, NOPAR, FULL (addv3) FAST (addv3) },
122 { TYPE (INSN_ADDX), IDX (INSN_ADDX), IDX (INSN_PAR_ADDX), IDX (INSN_WRITE_ADDX), FULL (addx) FAST (addx) },
123 { TYPE (INSN_BC8), IDX (INSN_BC8), IDX (INSN_PAR_BC8), IDX (INSN_WRITE_BC8), FULL (bc8) FAST (bc8) },
124 { TYPE (INSN_BC24), IDX (INSN_BC24), NOPAR, NOPAR, FULL (bc24) FAST (bc24) },
125 { TYPE (INSN_BEQ), IDX (INSN_BEQ), NOPAR, NOPAR, FULL (beq) FAST (beq) },
126 { TYPE (INSN_BEQZ), IDX (INSN_BEQZ), NOPAR, NOPAR, FULL (beqz) FAST (beqz) },
127 { TYPE (INSN_BGEZ), IDX (INSN_BGEZ), NOPAR, NOPAR, FULL (bgez) FAST (bgez) },
128 { TYPE (INSN_BGTZ), IDX (INSN_BGTZ), NOPAR, NOPAR, FULL (bgtz) FAST (bgtz) },
129 { TYPE (INSN_BLEZ), IDX (INSN_BLEZ), NOPAR, NOPAR, FULL (blez) FAST (blez) },
130 { TYPE (INSN_BLTZ), IDX (INSN_BLTZ), NOPAR, NOPAR, FULL (bltz) FAST (bltz) },
131 { TYPE (INSN_BNEZ), IDX (INSN_BNEZ), NOPAR, NOPAR, FULL (bnez) FAST (bnez) },
132 { TYPE (INSN_BL8), IDX (INSN_BL8), IDX (INSN_PAR_BL8), IDX (INSN_WRITE_BL8), FULL (bl8) FAST (bl8) },
133 { TYPE (INSN_BL24), IDX (INSN_BL24), NOPAR, NOPAR, FULL (bl24) FAST (bl24) },
134 { TYPE (INSN_BCL8), IDX (INSN_BCL8), IDX (INSN_PAR_BCL8), IDX (INSN_WRITE_BCL8), FULL (bcl8) FAST (bcl8) },
135 { TYPE (INSN_BCL24), IDX (INSN_BCL24), NOPAR, NOPAR, FULL (bcl24) FAST (bcl24) },
136 { TYPE (INSN_BNC8), IDX (INSN_BNC8), IDX (INSN_PAR_BNC8), IDX (INSN_WRITE_BNC8), FULL (bnc8) FAST (bnc8) },
137 { TYPE (INSN_BNC24), IDX (INSN_BNC24), NOPAR, NOPAR, FULL (bnc24) FAST (bnc24) },
138 { TYPE (INSN_BNE), IDX (INSN_BNE), NOPAR, NOPAR, FULL (bne) FAST (bne) },
139 { TYPE (INSN_BRA8), IDX (INSN_BRA8), IDX (INSN_PAR_BRA8), IDX (INSN_WRITE_BRA8), FULL (bra8) FAST (bra8) },
140 { TYPE (INSN_BRA24), IDX (INSN_BRA24), NOPAR, NOPAR, FULL (bra24) FAST (bra24) },
141 { TYPE (INSN_BNCL8), IDX (INSN_BNCL8), IDX (INSN_PAR_BNCL8), IDX (INSN_WRITE_BNCL8), FULL (bncl8) FAST (bncl8) },
142 { TYPE (INSN_BNCL24), IDX (INSN_BNCL24), NOPAR, NOPAR, FULL (bncl24) FAST (bncl24) },
143 { TYPE (INSN_CMP), IDX (INSN_CMP), IDX (INSN_PAR_CMP), IDX (INSN_WRITE_CMP), FULL (cmp) FAST (cmp) },
144 { TYPE (INSN_CMPI), IDX (INSN_CMPI), NOPAR, NOPAR, FULL (cmpi) FAST (cmpi) },
145 { TYPE (INSN_CMPU), IDX (INSN_CMPU), IDX (INSN_PAR_CMPU), IDX (INSN_WRITE_CMPU), FULL (cmpu) FAST (cmpu) },
146 { TYPE (INSN_CMPUI), IDX (INSN_CMPUI), NOPAR, NOPAR, FULL (cmpui) FAST (cmpui) },
147 { TYPE (INSN_CMPEQ), IDX (INSN_CMPEQ), IDX (INSN_PAR_CMPEQ), IDX (INSN_WRITE_CMPEQ), FULL (cmpeq) FAST (cmpeq) },
148 { TYPE (INSN_CMPZ), IDX (INSN_CMPZ), IDX (INSN_PAR_CMPZ), IDX (INSN_WRITE_CMPZ), FULL (cmpz) FAST (cmpz) },
149 { TYPE (INSN_DIV), IDX (INSN_DIV), NOPAR, NOPAR, FULL (div) FAST (div) },
150 { TYPE (INSN_DIVU), IDX (INSN_DIVU), NOPAR, NOPAR, FULL (divu) FAST (divu) },
151 { TYPE (INSN_REM), IDX (INSN_REM), NOPAR, NOPAR, FULL (rem) FAST (rem) },
152 { TYPE (INSN_REMU), IDX (INSN_REMU), NOPAR, NOPAR, FULL (remu) FAST (remu) },
153 { TYPE (INSN_DIVH), IDX (INSN_DIVH), NOPAR, NOPAR, FULL (divh) FAST (divh) },
154 { TYPE (INSN_JC), IDX (INSN_JC), IDX (INSN_PAR_JC), IDX (INSN_WRITE_JC), FULL (jc) FAST (jc) },
155 { TYPE (INSN_JNC), IDX (INSN_JNC), IDX (INSN_PAR_JNC), IDX (INSN_WRITE_JNC), FULL (jnc) FAST (jnc) },
156 { TYPE (INSN_JL), IDX (INSN_JL), IDX (INSN_PAR_JL), IDX (INSN_WRITE_JL), FULL (jl) FAST (jl) },
157 { TYPE (INSN_JMP), IDX (INSN_JMP), IDX (INSN_PAR_JMP), IDX (INSN_WRITE_JMP), FULL (jmp) FAST (jmp) },
158 { TYPE (INSN_LD), IDX (INSN_LD), IDX (INSN_PAR_LD), IDX (INSN_WRITE_LD), FULL (ld) FAST (ld) },
159 { TYPE (INSN_LD_D), IDX (INSN_LD_D), NOPAR, NOPAR, FULL (ld_d) FAST (ld_d) },
160 { TYPE (INSN_LDB), IDX (INSN_LDB), IDX (INSN_PAR_LDB), IDX (INSN_WRITE_LDB), FULL (ldb) FAST (ldb) },
161 { TYPE (INSN_LDB_D), IDX (INSN_LDB_D), NOPAR, NOPAR, FULL (ldb_d) FAST (ldb_d) },
162 { TYPE (INSN_LDH), IDX (INSN_LDH), IDX (INSN_PAR_LDH), IDX (INSN_WRITE_LDH), FULL (ldh) FAST (ldh) },
163 { TYPE (INSN_LDH_D), IDX (INSN_LDH_D), NOPAR, NOPAR, FULL (ldh_d) FAST (ldh_d) },
164 { TYPE (INSN_LDUB), IDX (INSN_LDUB), IDX (INSN_PAR_LDUB), IDX (INSN_WRITE_LDUB), FULL (ldub) FAST (ldub) },
165 { TYPE (INSN_LDUB_D), IDX (INSN_LDUB_D), NOPAR, NOPAR, FULL (ldub_d) FAST (ldub_d) },
166 { TYPE (INSN_LDUH), IDX (INSN_LDUH), IDX (INSN_PAR_LDUH), IDX (INSN_WRITE_LDUH), FULL (lduh) FAST (lduh) },
167 { TYPE (INSN_LDUH_D), IDX (INSN_LDUH_D), NOPAR, NOPAR, FULL (lduh_d) FAST (lduh_d) },
168 { TYPE (INSN_LD_PLUS), IDX (INSN_LD_PLUS), IDX (INSN_PAR_LD_PLUS), IDX (INSN_WRITE_LD_PLUS), FULL (ld_plus) FAST (ld_plus) },
169 { TYPE (INSN_LD24), IDX (INSN_LD24), NOPAR, NOPAR, FULL (ld24) FAST (ld24) },
170 { TYPE (INSN_LDI8), IDX (INSN_LDI8), IDX (INSN_PAR_LDI8), IDX (INSN_WRITE_LDI8), FULL (ldi8) FAST (ldi8) },
171 { TYPE (INSN_LDI16), IDX (INSN_LDI16), NOPAR, NOPAR, FULL (ldi16) FAST (ldi16) },
172 { TYPE (INSN_LOCK), IDX (INSN_LOCK), IDX (INSN_PAR_LOCK), IDX (INSN_WRITE_LOCK), FULL (lock) FAST (lock) },
173 { TYPE (INSN_MACHI_A), IDX (INSN_MACHI_A), IDX (INSN_PAR_MACHI_A), IDX (INSN_WRITE_MACHI_A), FULL (machi_a) FAST (machi_a) },
174 { TYPE (INSN_MACLO_A), IDX (INSN_MACLO_A), IDX (INSN_PAR_MACLO_A), IDX (INSN_WRITE_MACLO_A), FULL (maclo_a) FAST (maclo_a) },
175 { TYPE (INSN_MACWHI_A), IDX (INSN_MACWHI_A), IDX (INSN_PAR_MACWHI_A), IDX (INSN_WRITE_MACWHI_A), FULL (macwhi_a) FAST (macwhi_a) },
176 { TYPE (INSN_MACWLO_A), IDX (INSN_MACWLO_A), IDX (INSN_PAR_MACWLO_A), IDX (INSN_WRITE_MACWLO_A), FULL (macwlo_a) FAST (macwlo_a) },
177 { TYPE (INSN_MUL), IDX (INSN_MUL), IDX (INSN_PAR_MUL), IDX (INSN_WRITE_MUL), FULL (mul) FAST (mul) },
178 { TYPE (INSN_MULHI_A), IDX (INSN_MULHI_A), IDX (INSN_PAR_MULHI_A), IDX (INSN_WRITE_MULHI_A), FULL (mulhi_a) FAST (mulhi_a) },
179 { TYPE (INSN_MULLO_A), IDX (INSN_MULLO_A), IDX (INSN_PAR_MULLO_A), IDX (INSN_WRITE_MULLO_A), FULL (mullo_a) FAST (mullo_a) },
180 { TYPE (INSN_MULWHI_A), IDX (INSN_MULWHI_A), IDX (INSN_PAR_MULWHI_A), IDX (INSN_WRITE_MULWHI_A), FULL (mulwhi_a) FAST (mulwhi_a) },
181 { TYPE (INSN_MULWLO_A), IDX (INSN_MULWLO_A), IDX (INSN_PAR_MULWLO_A), IDX (INSN_WRITE_MULWLO_A), FULL (mulwlo_a) FAST (mulwlo_a) },
182 { TYPE (INSN_MV), IDX (INSN_MV), IDX (INSN_PAR_MV), IDX (INSN_WRITE_MV), FULL (mv) FAST (mv) },
183 { TYPE (INSN_MVFACHI_A), IDX (INSN_MVFACHI_A), IDX (INSN_PAR_MVFACHI_A), IDX (INSN_WRITE_MVFACHI_A), FULL (mvfachi_a) FAST (mvfachi_a) },
184 { TYPE (INSN_MVFACLO_A), IDX (INSN_MVFACLO_A), IDX (INSN_PAR_MVFACLO_A), IDX (INSN_WRITE_MVFACLO_A), FULL (mvfaclo_a) FAST (mvfaclo_a) },
185 { TYPE (INSN_MVFACMI_A), IDX (INSN_MVFACMI_A), IDX (INSN_PAR_MVFACMI_A), IDX (INSN_WRITE_MVFACMI_A), FULL (mvfacmi_a) FAST (mvfacmi_a) },
186 { TYPE (INSN_MVFC), IDX (INSN_MVFC), IDX (INSN_PAR_MVFC), IDX (INSN_WRITE_MVFC), FULL (mvfc) FAST (mvfc) },
187 { TYPE (INSN_MVTACHI_A), IDX (INSN_MVTACHI_A), IDX (INSN_PAR_MVTACHI_A), IDX (INSN_WRITE_MVTACHI_A), FULL (mvtachi_a) FAST (mvtachi_a) },
188 { TYPE (INSN_MVTACLO_A), IDX (INSN_MVTACLO_A), IDX (INSN_PAR_MVTACLO_A), IDX (INSN_WRITE_MVTACLO_A), FULL (mvtaclo_a) FAST (mvtaclo_a) },
189 { TYPE (INSN_MVTC), IDX (INSN_MVTC), IDX (INSN_PAR_MVTC), IDX (INSN_WRITE_MVTC), FULL (mvtc) FAST (mvtc) },
190 { TYPE (INSN_NEG), IDX (INSN_NEG), IDX (INSN_PAR_NEG), IDX (INSN_WRITE_NEG), FULL (neg) FAST (neg) },
191 { TYPE (INSN_NOP), IDX (INSN_NOP), IDX (INSN_PAR_NOP), IDX (INSN_WRITE_NOP), FULL (nop) FAST (nop) },
192 { TYPE (INSN_NOT), IDX (INSN_NOT), IDX (INSN_PAR_NOT), IDX (INSN_WRITE_NOT), FULL (not) FAST (not) },
193 { TYPE (INSN_RAC_DSI), IDX (INSN_RAC_DSI), IDX (INSN_PAR_RAC_DSI), IDX (INSN_WRITE_RAC_DSI), FULL (rac_dsi) FAST (rac_dsi) },
194 { TYPE (INSN_RACH_DSI), IDX (INSN_RACH_DSI), IDX (INSN_PAR_RACH_DSI), IDX (INSN_WRITE_RACH_DSI), FULL (rach_dsi) FAST (rach_dsi) },
195 { TYPE (INSN_RTE), IDX (INSN_RTE), IDX (INSN_PAR_RTE), IDX (INSN_WRITE_RTE), FULL (rte) FAST (rte) },
196 { TYPE (INSN_SETH), IDX (INSN_SETH), NOPAR, NOPAR, FULL (seth) FAST (seth) },
197 { TYPE (INSN_SLL), IDX (INSN_SLL), IDX (INSN_PAR_SLL), IDX (INSN_WRITE_SLL), FULL (sll) FAST (sll) },
198 { TYPE (INSN_SLL3), IDX (INSN_SLL3), NOPAR, NOPAR, FULL (sll3) FAST (sll3) },
199 { TYPE (INSN_SLLI), IDX (INSN_SLLI), IDX (INSN_PAR_SLLI), IDX (INSN_WRITE_SLLI), FULL (slli) FAST (slli) },
200 { TYPE (INSN_SRA), IDX (INSN_SRA), IDX (INSN_PAR_SRA), IDX (INSN_WRITE_SRA), FULL (sra) FAST (sra) },
201 { TYPE (INSN_SRA3), IDX (INSN_SRA3), NOPAR, NOPAR, FULL (sra3) FAST (sra3) },
202 { TYPE (INSN_SRAI), IDX (INSN_SRAI), IDX (INSN_PAR_SRAI), IDX (INSN_WRITE_SRAI), FULL (srai) FAST (srai) },
203 { TYPE (INSN_SRL), IDX (INSN_SRL), IDX (INSN_PAR_SRL), IDX (INSN_WRITE_SRL), FULL (srl) FAST (srl) },
204 { TYPE (INSN_SRL3), IDX (INSN_SRL3), NOPAR, NOPAR, FULL (srl3) FAST (srl3) },
205 { TYPE (INSN_SRLI), IDX (INSN_SRLI), IDX (INSN_PAR_SRLI), IDX (INSN_WRITE_SRLI), FULL (srli) FAST (srli) },
206 { TYPE (INSN_ST), IDX (INSN_ST), IDX (INSN_PAR_ST), IDX (INSN_WRITE_ST), FULL (st) FAST (st) },
207 { TYPE (INSN_ST_D), IDX (INSN_ST_D), NOPAR, NOPAR, FULL (st_d) FAST (st_d) },
208 { TYPE (INSN_STB), IDX (INSN_STB), IDX (INSN_PAR_STB), IDX (INSN_WRITE_STB), FULL (stb) FAST (stb) },
209 { TYPE (INSN_STB_D), IDX (INSN_STB_D), NOPAR, NOPAR, FULL (stb_d) FAST (stb_d) },
210 { TYPE (INSN_STH), IDX (INSN_STH), IDX (INSN_PAR_STH), IDX (INSN_WRITE_STH), FULL (sth) FAST (sth) },
211 { TYPE (INSN_STH_D), IDX (INSN_STH_D), NOPAR, NOPAR, FULL (sth_d) FAST (sth_d) },
212 { TYPE (INSN_ST_PLUS), IDX (INSN_ST_PLUS), IDX (INSN_PAR_ST_PLUS), IDX (INSN_WRITE_ST_PLUS), FULL (st_plus) FAST (st_plus) },
213 { TYPE (INSN_ST_MINUS), IDX (INSN_ST_MINUS), IDX (INSN_PAR_ST_MINUS), IDX (INSN_WRITE_ST_MINUS), FULL (st_minus) FAST (st_minus) },
214 { TYPE (INSN_SUB), IDX (INSN_SUB), IDX (INSN_PAR_SUB), IDX (INSN_WRITE_SUB), FULL (sub) FAST (sub) },
215 { TYPE (INSN_SUBV), IDX (INSN_SUBV), IDX (INSN_PAR_SUBV), IDX (INSN_WRITE_SUBV), FULL (subv) FAST (subv) },
216 { TYPE (INSN_SUBX), IDX (INSN_SUBX), IDX (INSN_PAR_SUBX), IDX (INSN_WRITE_SUBX), FULL (subx) FAST (subx) },
217 { TYPE (INSN_TRAP), IDX (INSN_TRAP), IDX (INSN_PAR_TRAP), IDX (INSN_WRITE_TRAP), FULL (trap) FAST (trap) },
218 { TYPE (INSN_UNLOCK), IDX (INSN_UNLOCK), IDX (INSN_PAR_UNLOCK), IDX (INSN_WRITE_UNLOCK), FULL (unlock) FAST (unlock) },
219 { TYPE (INSN_SATB), IDX (INSN_SATB), NOPAR, NOPAR, FULL (satb) FAST (satb) },
220 { TYPE (INSN_SATH), IDX (INSN_SATH), NOPAR, NOPAR, FULL (sath) FAST (sath) },
221 { TYPE (INSN_SAT), IDX (INSN_SAT), NOPAR, NOPAR, FULL (sat) FAST (sat) },
222 { TYPE (INSN_PCMPBZ), IDX (INSN_PCMPBZ), IDX (INSN_PAR_PCMPBZ), IDX (INSN_WRITE_PCMPBZ), FULL (pcmpbz) FAST (pcmpbz) },
223 { TYPE (INSN_SADD), IDX (INSN_SADD), IDX (INSN_PAR_SADD), IDX (INSN_WRITE_SADD), FULL (sadd) FAST (sadd) },
224 { TYPE (INSN_MACWU1), IDX (INSN_MACWU1), IDX (INSN_PAR_MACWU1), IDX (INSN_WRITE_MACWU1), FULL (macwu1) FAST (macwu1) },
225 { TYPE (INSN_MSBLO), IDX (INSN_MSBLO), IDX (INSN_PAR_MSBLO), IDX (INSN_WRITE_MSBLO), FULL (msblo) FAST (msblo) },
226 { TYPE (INSN_MULWU1), IDX (INSN_MULWU1), IDX (INSN_PAR_MULWU1), IDX (INSN_WRITE_MULWU1), FULL (mulwu1) FAST (mulwu1) },
227 { TYPE (INSN_MACLH1), IDX (INSN_MACLH1), IDX (INSN_PAR_MACLH1), IDX (INSN_WRITE_MACLH1), FULL (maclh1) FAST (maclh1) },
228 { TYPE (INSN_SC), IDX (INSN_SC), IDX (INSN_PAR_SC), IDX (INSN_WRITE_SC), FULL (sc) FAST (sc) },
229 { TYPE (INSN_SNC), IDX (INSN_SNC), IDX (INSN_PAR_SNC), IDX (INSN_WRITE_SNC), FULL (snc) FAST (snc) },
230 };
231
232 static const struct insn_sem m32rxf_insn_sem_invalid =
233 {
234 VIRTUAL_INSN_X_INVALID, IDX (INSN_X_INVALID), IDX (INSN_X_INVALID), 0 /*unused*/, FULL (x_invalid) FAST (x_invalid)
235 };
236
237 #undef IDX
238 #undef TYPE
239
240 /* Initialize an IDESC from the compile-time computable parts. */
241
242 static INLINE void
243 init_idesc (SIM_CPU *cpu, IDESC *id, const struct insn_sem *t)
244 {
245 const CGEN_INSN *opcode_table = m32r_cgen_insn_table_entries;
246
247 id->num = t->index;
248 if ((int) t->type <= 0)
249 id->opcode = & cgen_virtual_opcode_table[- t->type];
250 else
251 id->opcode = & opcode_table[t->type];
252 #if ! WITH_SEM_SWITCH_FULL
253 id->sem_full = t->sem_full;
254 #endif
255 #if WITH_FAST && ! WITH_SEM_SWITCH_FAST
256 id->sem_fast = t->sem_fast;
257 #endif
258 #if WITH_PROFILE_MODEL_P
259 id->timing = & MODEL_TIMING (CPU_MODEL (cpu)) [t->index];
260 {
261 SIM_DESC sd = CPU_STATE (cpu);
262 SIM_ASSERT (t->index == id->timing->num);
263 }
264 #endif
265 }
266
267 /* Initialize the instruction descriptor table. */
268
269 void
270 m32rxf_init_idesc_table (SIM_CPU *cpu)
271 {
272 IDESC *id,*tabend;
273 const struct insn_sem *t,*tend;
274 int tabsize = M32RXF_INSN_MAX;
275 IDESC *table = m32rxf_insn_data;
276
277 memset (table, 0, tabsize * sizeof (IDESC));
278
279 /* First set all entries to the `invalid insn'. */
280 t = & m32rxf_insn_sem_invalid;
281 for (id = table, tabend = table + tabsize; id < tabend; ++id)
282 init_idesc (cpu, id, t);
283
284 /* Now fill in the values for the chosen cpu. */
285 for (t = m32rxf_insn_sem, tend = t + sizeof (m32rxf_insn_sem) / sizeof (*t);
286 t != tend; ++t)
287 {
288 init_idesc (cpu, & table[t->index], t);
289 if (t->par_index != NOPAR)
290 {
291 init_idesc (cpu, &table[t->par_index], t);
292 table[t->index].par_idesc = &table[t->par_index];
293 }
294 if (t->par_index != NOPAR)
295 {
296 init_idesc (cpu, &table[t->write_index], t);
297 table[t->par_index].par_idesc = &table[t->write_index];
298 }
299 }
300
301 /* Link the IDESC table into the cpu. */
302 CPU_IDESC (cpu) = table;
303 }
304
305 /* Enum declaration for all instruction semantic formats. */
306 typedef enum sfmt {
307 FMT_EMPTY, FMT_ADD, FMT_ADD3, FMT_AND3
308 , FMT_OR3, FMT_ADDI, FMT_ADDV, FMT_ADDV3
309 , FMT_ADDX, FMT_BC8, FMT_BC24, FMT_BEQ
310 , FMT_BEQZ, FMT_BL8, FMT_BL24, FMT_BCL8
311 , FMT_BCL24, FMT_BRA8, FMT_BRA24, FMT_CMP
312 , FMT_CMPI, FMT_CMPZ, FMT_DIV, FMT_JC
313 , FMT_JL, FMT_JMP, FMT_LD, FMT_LD_D
314 , FMT_LDB, FMT_LDB_D, FMT_LDH, FMT_LDH_D
315 , FMT_LD_PLUS, FMT_LD24, FMT_LDI8, FMT_LDI16
316 , FMT_LOCK, FMT_MACHI_A, FMT_MULHI_A, FMT_MV
317 , FMT_MVFACHI_A, FMT_MVFC, FMT_MVTACHI_A, FMT_MVTC
318 , FMT_NOP, FMT_RAC_DSI, FMT_RTE, FMT_SETH
319 , FMT_SLL3, FMT_SLLI, FMT_ST, FMT_ST_D
320 , FMT_STB, FMT_STB_D, FMT_STH, FMT_STH_D
321 , FMT_ST_PLUS, FMT_TRAP, FMT_UNLOCK, FMT_SATB
322 , FMT_SAT, FMT_SADD, FMT_MACWU1, FMT_MSBLO
323 , FMT_MULWU1, FMT_SC
324 } SFMT;
325
326 /* The decoder uses this to record insns and direct extraction handling. */
327
328 typedef struct {
329 const IDESC *idesc;
330 #ifdef __GNUC__
331 void *sfmt;
332 #else
333 enum sfmt sfmt;
334 #endif
335 } DECODE_DESC;
336
337 /* Macro to go from decode phase to extraction phase. */
338
339 #ifdef __GNUC__
340 #define GOTO_EXTRACT(id) goto *(id)->sfmt
341 #else
342 #define GOTO_EXTRACT(id) goto extract
343 #endif
344
345 /* The decoder needs a slightly different computed goto switch control. */
346 #ifdef __GNUC__
347 #define DECODE_SWITCH(N, X) goto *labels_##N[X];
348 #else
349 #define DECODE_SWITCH(N, X) switch (X)
350 #endif
351
352 /* Given an instruction, return a pointer to its IDESC entry. */
353
354 const IDESC *
355 m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
356 CGEN_INSN_INT base_insn, CGEN_INSN_INT entire_insn,
357 ARGBUF *abuf)
358 {
359 /* Result of decoder, used by extractor. */
360 const DECODE_DESC *idecode;
361
362 /* First decode the instruction. */
363
364 {
365 #define I(insn) & m32rxf_insn_data[CONCAT2 (M32RXF_,insn)]
366 #ifdef __GNUC__
367 #define E(fmt) && case_ex_##fmt
368 #else
369 #define E(fmt) fmt
370 #endif
371 CGEN_INSN_INT insn = base_insn;
372 static const DECODE_DESC idecode_invalid = { I (INSN_X_INVALID), E (FMT_EMPTY) };
373
374 {
375 #ifdef __GNUC__
376 static const void *labels_0[256] = {
377 && default_0, && default_0, && default_0, && default_0,
378 && default_0, && default_0, && default_0, && case_0_7,
379 && default_0, && default_0, && default_0, && default_0,
380 && default_0, && default_0, && default_0, && default_0,
381 && default_0, && default_0, && default_0, && default_0,
382 && default_0, && default_0, && default_0, && default_0,
383 && default_0, && default_0, && default_0, && default_0,
384 && case_0_28, && default_0, && default_0, && default_0,
385 && default_0, && default_0, && default_0, && default_0,
386 && default_0, && default_0, && default_0, && default_0,
387 && default_0, && default_0, && default_0, && default_0,
388 && default_0, && default_0, && default_0, && default_0,
389 && default_0, && default_0, && default_0, && default_0,
390 && default_0, && default_0, && default_0, && default_0,
391 && default_0, && default_0, && default_0, && default_0,
392 && default_0, && default_0, && default_0, && default_0,
393 && default_0, && default_0, && default_0, && default_0,
394 && default_0, && default_0, && default_0, && default_0,
395 && default_0, && default_0, && default_0, && default_0,
396 && default_0, && default_0, && default_0, && default_0,
397 && default_0, && default_0, && default_0, && default_0,
398 && default_0, && default_0, && default_0, && case_0_87,
399 && default_0, && default_0, && default_0, && default_0,
400 && default_0, && default_0, && default_0, && case_0_95,
401 && default_0, && default_0, && default_0, && default_0,
402 && default_0, && default_0, && default_0, && default_0,
403 && default_0, && default_0, && default_0, && default_0,
404 && default_0, && default_0, && default_0, && default_0,
405 && case_0_112, && case_0_113, && case_0_114, && case_0_115,
406 && case_0_116, && case_0_117, && case_0_118, && case_0_119,
407 && case_0_120, && case_0_121, && case_0_122, && case_0_123,
408 && case_0_124, && case_0_125, && case_0_126, && case_0_127,
409 && default_0, && default_0, && default_0, && default_0,
410 && default_0, && default_0, && case_0_134, && default_0,
411 && default_0, && default_0, && default_0, && default_0,
412 && default_0, && default_0, && default_0, && default_0,
413 && case_0_144, && default_0, && default_0, && default_0,
414 && default_0, && default_0, && default_0, && default_0,
415 && default_0, && default_0, && default_0, && default_0,
416 && default_0, && default_0, && default_0, && default_0,
417 && default_0, && default_0, && default_0, && default_0,
418 && default_0, && default_0, && default_0, && default_0,
419 && default_0, && default_0, && default_0, && default_0,
420 && default_0, && default_0, && default_0, && default_0,
421 && default_0, && default_0, && default_0, && default_0,
422 && default_0, && default_0, && default_0, && default_0,
423 && default_0, && default_0, && default_0, && default_0,
424 && default_0, && default_0, && default_0, && default_0,
425 && default_0, && default_0, && default_0, && default_0,
426 && default_0, && default_0, && default_0, && default_0,
427 && default_0, && default_0, && default_0, && default_0,
428 && default_0, && default_0, && default_0, && default_0,
429 && default_0, && default_0, && default_0, && default_0,
430 && default_0, && default_0, && default_0, && default_0,
431 && default_0, && default_0, && default_0, && default_0,
432 && default_0, && default_0, && default_0, && default_0,
433 && default_0, && default_0, && default_0, && default_0,
434 && default_0, && default_0, && default_0, && default_0,
435 && default_0, && default_0, && default_0, && default_0,
436 && default_0, && default_0, && default_0, && default_0,
437 && case_0_240, && case_0_241, && case_0_242, && case_0_243,
438 && case_0_244, && case_0_245, && case_0_246, && case_0_247,
439 && case_0_248, && case_0_249, && case_0_250, && case_0_251,
440 && case_0_252, && case_0_253, && case_0_254, && case_0_255,
441 };
442 #endif
443 static const DECODE_DESC insns[256] = {
444 { I (INSN_SUBV), E (FMT_ADDV) }, { I (INSN_SUBX), E (FMT_ADDX) },
445 { I (INSN_SUB), E (FMT_ADD) }, { I (INSN_NEG), E (FMT_MV) },
446 { I (INSN_CMP), E (FMT_CMP) }, { I (INSN_CMPU), E (FMT_CMP) },
447 { I (INSN_CMPEQ), E (FMT_CMP) }, { 0 },
448 { I (INSN_ADDV), E (FMT_ADDV) }, { I (INSN_ADDX), E (FMT_ADDX) },
449 { I (INSN_ADD), E (FMT_ADD) }, { I (INSN_NOT), E (FMT_MV) },
450 { I (INSN_AND), E (FMT_ADD) }, { I (INSN_XOR), E (FMT_ADD) },
451 { I (INSN_OR), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
452 { I (INSN_SRL), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
453 { I (INSN_SRA), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
454 { I (INSN_SLL), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
455 { I (INSN_MUL), E (FMT_ADD) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
456 { I (INSN_MV), E (FMT_MV) }, { I (INSN_MVFC), E (FMT_MVFC) },
457 { I (INSN_MVTC), E (FMT_MVTC) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
458 { 0 }, { I (INSN_RTE), E (FMT_RTE) },
459 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_TRAP), E (FMT_TRAP) },
460 { I (INSN_STB), E (FMT_STB) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
461 { I (INSN_STH), E (FMT_STH) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
462 { I (INSN_ST), E (FMT_ST) }, { I (INSN_UNLOCK), E (FMT_UNLOCK) },
463 { I (INSN_ST_PLUS), E (FMT_ST_PLUS) }, { I (INSN_ST_MINUS), E (FMT_ST_PLUS) },
464 { I (INSN_LDB), E (FMT_LDB) }, { I (INSN_LDUB), E (FMT_LDB) },
465 { I (INSN_LDH), E (FMT_LDH) }, { I (INSN_LDUH), E (FMT_LDH) },
466 { I (INSN_LD), E (FMT_LD) }, { I (INSN_LOCK), E (FMT_LOCK) },
467 { I (INSN_LD_PLUS), E (FMT_LD_PLUS) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
468 { I (INSN_MULHI_A), E (FMT_MULHI_A) }, { I (INSN_MULLO_A), E (FMT_MULHI_A) },
469 { I (INSN_MULWHI_A), E (FMT_MULHI_A) }, { I (INSN_MULWLO_A), E (FMT_MULHI_A) },
470 { I (INSN_MACHI_A), E (FMT_MACHI_A) }, { I (INSN_MACLO_A), E (FMT_MACHI_A) },
471 { I (INSN_MACWHI_A), E (FMT_MACHI_A) }, { I (INSN_MACWLO_A), E (FMT_MACHI_A) },
472 { I (INSN_MULHI_A), E (FMT_MULHI_A) }, { I (INSN_MULLO_A), E (FMT_MULHI_A) },
473 { I (INSN_MULWHI_A), E (FMT_MULHI_A) }, { I (INSN_MULWLO_A), E (FMT_MULHI_A) },
474 { I (INSN_MACHI_A), E (FMT_MACHI_A) }, { I (INSN_MACLO_A), E (FMT_MACHI_A) },
475 { I (INSN_MACWHI_A), E (FMT_MACHI_A) }, { I (INSN_MACWLO_A), E (FMT_MACHI_A) },
476 { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) },
477 { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) },
478 { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) },
479 { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) },
480 { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) },
481 { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) },
482 { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) },
483 { I (INSN_ADDI), E (FMT_ADDI) }, { I (INSN_ADDI), E (FMT_ADDI) },
484 { I (INSN_SRLI), E (FMT_SLLI) }, { I (INSN_SRLI), E (FMT_SLLI) },
485 { I (INSN_SRAI), E (FMT_SLLI) }, { I (INSN_SRAI), E (FMT_SLLI) },
486 { I (INSN_SLLI), E (FMT_SLLI) }, { I (INSN_SLLI), E (FMT_SLLI) },
487 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { 0 },
488 { I (INSN_RACH_DSI), E (FMT_RAC_DSI) }, { I (INSN_RAC_DSI), E (FMT_RAC_DSI) },
489 { I (INSN_MULWU1), E (FMT_MULWU1) }, { I (INSN_MACWU1), E (FMT_MACWU1) },
490 { I (INSN_MACLH1), E (FMT_MACWU1) }, { I (INSN_MSBLO), E (FMT_MSBLO) },
491 { I (INSN_SADD), E (FMT_SADD) }, { 0 },
492 { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) },
493 { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) },
494 { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) },
495 { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) },
496 { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) },
497 { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) },
498 { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) },
499 { I (INSN_LDI8), E (FMT_LDI8) }, { I (INSN_LDI8), E (FMT_LDI8) },
500 { 0 }, { 0 },
501 { 0 }, { 0 },
502 { 0 }, { 0 },
503 { 0 }, { 0 },
504 { 0 }, { 0 },
505 { 0 }, { 0 },
506 { 0 }, { 0 },
507 { 0 }, { 0 },
508 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
509 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
510 { I (INSN_CMPI), E (FMT_CMPI) }, { I (INSN_CMPUI), E (FMT_CMPI) },
511 { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
512 { I (INSN_ADDV3), E (FMT_ADDV3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
513 { I (INSN_ADD3), E (FMT_ADD3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
514 { I (INSN_AND3), E (FMT_AND3) }, { I (INSN_XOR3), E (FMT_AND3) },
515 { I (INSN_OR3), E (FMT_OR3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
516 { 0 }, { I (INSN_DIVU), E (FMT_DIV) },
517 { I (INSN_REM), E (FMT_DIV) }, { I (INSN_REMU), E (FMT_DIV) },
518 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
519 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
520 { I (INSN_SRL3), E (FMT_SLL3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
521 { I (INSN_SRA3), E (FMT_SLL3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
522 { I (INSN_SLL3), E (FMT_SLL3) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
523 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_LDI16), E (FMT_LDI16) },
524 { I (INSN_STB_D), E (FMT_STB_D) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
525 { I (INSN_STH_D), E (FMT_STH_D) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
526 { I (INSN_ST_D), E (FMT_ST_D) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
527 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
528 { I (INSN_LDB_D), E (FMT_LDB_D) }, { I (INSN_LDUB_D), E (FMT_LDB_D) },
529 { I (INSN_LDH_D), E (FMT_LDH_D) }, { I (INSN_LDUH_D), E (FMT_LDH_D) },
530 { I (INSN_LD_D), E (FMT_LD_D) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
531 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
532 { I (INSN_BEQ), E (FMT_BEQ) }, { I (INSN_BNE), E (FMT_BEQ) },
533 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
534 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
535 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
536 { I (INSN_BEQZ), E (FMT_BEQZ) }, { I (INSN_BNEZ), E (FMT_BEQZ) },
537 { I (INSN_BLTZ), E (FMT_BEQZ) }, { I (INSN_BGEZ), E (FMT_BEQZ) },
538 { I (INSN_BLEZ), E (FMT_BEQZ) }, { I (INSN_BGTZ), E (FMT_BEQZ) },
539 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
540 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
541 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
542 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
543 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
544 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
545 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
546 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
547 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
548 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
549 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
550 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
551 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
552 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
553 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
554 { I (INSN_SETH), E (FMT_SETH) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
555 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
556 { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) },
557 { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) },
558 { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) },
559 { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) },
560 { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) },
561 { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) },
562 { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) },
563 { I (INSN_LD24), E (FMT_LD24) }, { I (INSN_LD24), E (FMT_LD24) },
564 { 0 }, { 0 },
565 { 0 }, { 0 },
566 { 0 }, { 0 },
567 { 0 }, { 0 },
568 { 0 }, { 0 },
569 { 0 }, { 0 },
570 { 0 }, { 0 },
571 { 0 }, { 0 },
572 };
573 unsigned int val;
574 val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
575 DECODE_SWITCH (0, val)
576 {
577 CASE (0, 7) :
578 {
579 static const DECODE_DESC insns[16] = {
580 { I (INSN_CMPZ), E (FMT_CMPZ) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
581 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_PCMPBZ), E (FMT_CMPZ) },
582 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
583 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
584 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
585 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
586 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
587 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
588 };
589 unsigned int val = (((insn >> 8) & (15 << 0)));
590 idecode = &insns[val];
591 GOTO_EXTRACT (idecode);
592 }
593 CASE (0, 28) :
594 {
595 static const DECODE_DESC insns[16] = {
596 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
597 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
598 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
599 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
600 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
601 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
602 { I (INSN_JC), E (FMT_JC) }, { I (INSN_JNC), E (FMT_JC) },
603 { I (INSN_JL), E (FMT_JL) }, { I (INSN_JMP), E (FMT_JMP) },
604 };
605 unsigned int val = (((insn >> 8) & (15 << 0)));
606 idecode = &insns[val];
607 GOTO_EXTRACT (idecode);
608 }
609 CASE (0, 87) :
610 {
611 static const DECODE_DESC insns[4] = {
612 { I (INSN_MVTACHI_A), E (FMT_MVTACHI_A) }, { I (INSN_MVTACLO_A), E (FMT_MVTACHI_A) },
613 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
614 };
615 unsigned int val = (((insn >> 0) & (3 << 0)));
616 idecode = &insns[val];
617 GOTO_EXTRACT (idecode);
618 }
619 CASE (0, 95) :
620 {
621 static const DECODE_DESC insns[4] = {
622 { I (INSN_MVFACHI_A), E (FMT_MVFACHI_A) }, { I (INSN_MVFACLO_A), E (FMT_MVFACHI_A) },
623 { I (INSN_MVFACMI_A), E (FMT_MVFACHI_A) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
624 };
625 unsigned int val = (((insn >> 0) & (3 << 0)));
626 idecode = &insns[val];
627 GOTO_EXTRACT (idecode);
628 }
629 CASE (0, 112) :
630 {
631 static const DECODE_DESC insns[16] = {
632 { I (INSN_NOP), E (FMT_NOP) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
633 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
634 { I (INSN_SC), E (FMT_SC) }, { I (INSN_SNC), E (FMT_SC) },
635 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
636 { I (INSN_BCL8), E (FMT_BCL8) }, { I (INSN_BNCL8), E (FMT_BCL8) },
637 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
638 { I (INSN_BC8), E (FMT_BC8) }, { I (INSN_BNC8), E (FMT_BC8) },
639 { I (INSN_BL8), E (FMT_BL8) }, { I (INSN_BRA8), E (FMT_BRA8) },
640 };
641 unsigned int val = (((insn >> 8) & (15 << 0)));
642 idecode = &insns[val];
643 GOTO_EXTRACT (idecode);
644 }
645 CASE (0, 113) : /* fall through */
646 CASE (0, 114) : /* fall through */
647 CASE (0, 115) : /* fall through */
648 CASE (0, 116) : /* fall through */
649 CASE (0, 117) : /* fall through */
650 CASE (0, 118) : /* fall through */
651 CASE (0, 119) : /* fall through */
652 CASE (0, 120) : /* fall through */
653 CASE (0, 121) : /* fall through */
654 CASE (0, 122) : /* fall through */
655 CASE (0, 123) : /* fall through */
656 CASE (0, 124) : /* fall through */
657 CASE (0, 125) : /* fall through */
658 CASE (0, 126) : /* fall through */
659 CASE (0, 127) :
660 {
661 static const DECODE_DESC insns[16] = {
662 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
663 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
664 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
665 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
666 { I (INSN_BCL8), E (FMT_BCL8) }, { I (INSN_BNCL8), E (FMT_BCL8) },
667 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
668 { I (INSN_BC8), E (FMT_BC8) }, { I (INSN_BNC8), E (FMT_BC8) },
669 { I (INSN_BL8), E (FMT_BL8) }, { I (INSN_BRA8), E (FMT_BRA8) },
670 };
671 unsigned int val = (((insn >> 8) & (15 << 0)));
672 idecode = &insns[val];
673 GOTO_EXTRACT (idecode);
674 }
675 CASE (0, 134) :
676 {
677 #ifdef __GNUC__
678 static const void *labels_0_134[16] = {
679 && case_0_134_0, && default_0_134, && default_0_134, && default_0_134,
680 && default_0_134, && default_0_134, && default_0_134, && default_0_134,
681 && default_0_134, && default_0_134, && default_0_134, && default_0_134,
682 && default_0_134, && default_0_134, && default_0_134, && default_0_134,
683 };
684 #endif
685 static const DECODE_DESC insns[16] = {
686 { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
687 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
688 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
689 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
690 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
691 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
692 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
693 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
694 };
695 unsigned int val;
696 /* Must fetch more bits. */
697 insn = GETIMEMUHI (current_cpu, pc + 2);
698 val = (((insn >> 12) & (15 << 0)));
699 DECODE_SWITCH (0_134, val)
700 {
701 CASE (0_134, 0) :
702 {
703 static const DECODE_DESC insns[16] = {
704 { I (INSN_SAT), E (FMT_SAT) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
705 { I (INSN_SATH), E (FMT_SATB) }, { I (INSN_SATB), E (FMT_SATB) },
706 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
707 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
708 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
709 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
710 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
711 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
712 };
713 unsigned int val = (((insn >> 8) & (15 << 0)));
714 idecode = &insns[val];
715 GOTO_EXTRACT (idecode);
716 }
717 DEFAULT (0_134) :
718 idecode = &insns[val];
719 GOTO_EXTRACT (idecode);
720 }
721 ENDSWITCH (0_134)
722 }
723 CASE (0, 144) :
724 {
725 #ifdef __GNUC__
726 static const void *labels_0_144[16] = {
727 && case_0_144_0, && default_0_144, && default_0_144, && default_0_144,
728 && default_0_144, && default_0_144, && default_0_144, && default_0_144,
729 && default_0_144, && default_0_144, && default_0_144, && default_0_144,
730 && default_0_144, && default_0_144, && default_0_144, && default_0_144,
731 };
732 #endif
733 static const DECODE_DESC insns[16] = {
734 { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
735 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
736 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
737 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
738 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
739 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
740 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
741 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
742 };
743 unsigned int val;
744 /* Must fetch more bits. */
745 insn = GETIMEMUHI (current_cpu, pc + 2);
746 val = (((insn >> 12) & (15 << 0)));
747 DECODE_SWITCH (0_144, val)
748 {
749 CASE (0_144, 0) :
750 {
751 #ifdef __GNUC__
752 static const void *labels_0_144_0[16] = {
753 && case_0_144_0_0, && default_0_144_0, && default_0_144_0, && default_0_144_0,
754 && default_0_144_0, && default_0_144_0, && default_0_144_0, && default_0_144_0,
755 && default_0_144_0, && default_0_144_0, && default_0_144_0, && default_0_144_0,
756 && default_0_144_0, && default_0_144_0, && default_0_144_0, && default_0_144_0,
757 };
758 #endif
759 static const DECODE_DESC insns[16] = {
760 { 0 }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
761 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
762 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
763 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
764 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
765 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
766 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
767 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
768 };
769 unsigned int val;
770 val = (((insn >> 8) & (15 << 0)));
771 DECODE_SWITCH (0_144_0, val)
772 {
773 CASE (0_144_0, 0) :
774 {
775 static const DECODE_DESC insns[16] = {
776 { I (INSN_DIV), E (FMT_DIV) }, { I (INSN_DIVH), E (FMT_DIV) },
777 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
778 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
779 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
780 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
781 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
782 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
783 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
784 };
785 unsigned int val = (((insn >> 4) & (15 << 0)));
786 idecode = &insns[val];
787 GOTO_EXTRACT (idecode);
788 }
789 DEFAULT (0_144_0) :
790 idecode = &insns[val];
791 GOTO_EXTRACT (idecode);
792 }
793 ENDSWITCH (0_144_0)
794 }
795 DEFAULT (0_144) :
796 idecode = &insns[val];
797 GOTO_EXTRACT (idecode);
798 }
799 ENDSWITCH (0_144)
800 }
801 CASE (0, 240) : /* fall through */
802 CASE (0, 241) : /* fall through */
803 CASE (0, 242) : /* fall through */
804 CASE (0, 243) : /* fall through */
805 CASE (0, 244) : /* fall through */
806 CASE (0, 245) : /* fall through */
807 CASE (0, 246) : /* fall through */
808 CASE (0, 247) : /* fall through */
809 CASE (0, 248) : /* fall through */
810 CASE (0, 249) : /* fall through */
811 CASE (0, 250) : /* fall through */
812 CASE (0, 251) : /* fall through */
813 CASE (0, 252) : /* fall through */
814 CASE (0, 253) : /* fall through */
815 CASE (0, 254) : /* fall through */
816 CASE (0, 255) :
817 {
818 static const DECODE_DESC insns[16] = {
819 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
820 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
821 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
822 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
823 { I (INSN_BCL24), E (FMT_BCL24) }, { I (INSN_BNCL24), E (FMT_BCL24) },
824 { I (INSN_X_INVALID), E (FMT_EMPTY) }, { I (INSN_X_INVALID), E (FMT_EMPTY) },
825 { I (INSN_BC24), E (FMT_BC24) }, { I (INSN_BNC24), E (FMT_BC24) },
826 { I (INSN_BL24), E (FMT_BL24) }, { I (INSN_BRA24), E (FMT_BRA24) },
827 };
828 unsigned int val = (((insn >> 8) & (15 << 0)));
829 idecode = &insns[val];
830 GOTO_EXTRACT (idecode);
831 }
832 DEFAULT (0) :
833 idecode = &insns[val];
834 GOTO_EXTRACT (idecode);
835 }
836 ENDSWITCH (0)
837 }
838 #undef I
839 #undef E
840 }
841
842 /* The instruction has been decoded, now extract the fields. */
843
844 extract:
845 {
846 #ifndef __GNUC__
847 switch (idecode->sfmt)
848 #endif
849 {
850
851 CASE (ex, FMT_EMPTY) :
852 {
853 CGEN_INSN_INT insn = entire_insn;
854 #define FLD(f) abuf->fields.fmt_empty.f
855 EXTRACT_IFMT_EMPTY_VARS /* */
856
857 EXTRACT_IFMT_EMPTY_CODE
858
859 /* Record the fields for the semantic handler. */
860 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_empty", (char *) 0));
861
862 #undef FLD
863 BREAK (ex);
864 }
865
866 CASE (ex, FMT_ADD) :
867 {
868 CGEN_INSN_INT insn = entire_insn;
869 #define FLD(f) abuf->fields.fmt_add.f
870 EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
871
872 EXTRACT_IFMT_ADD_CODE
873
874 /* Record the fields for the semantic handler. */
875 FLD (i_dr) = & CPU (h_gr)[f_r1];
876 FLD (i_sr) = & CPU (h_gr)[f_r2];
877 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_add", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
878
879 #if WITH_PROFILE_MODEL_P
880 /* Record the fields for profiling. */
881 if (PROFILE_MODEL_P (current_cpu))
882 {
883 FLD (in_dr) = f_r1;
884 FLD (in_sr) = f_r2;
885 FLD (out_dr) = f_r1;
886 }
887 #endif
888 #undef FLD
889 BREAK (ex);
890 }
891
892 CASE (ex, FMT_ADD3) :
893 {
894 CGEN_INSN_INT insn = entire_insn;
895 #define FLD(f) abuf->fields.fmt_add3.f
896 EXTRACT_IFMT_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
897
898 EXTRACT_IFMT_ADD3_CODE
899
900 /* Record the fields for the semantic handler. */
901 FLD (f_simm16) = f_simm16;
902 FLD (i_sr) = & CPU (h_gr)[f_r2];
903 FLD (i_dr) = & CPU (h_gr)[f_r1];
904 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_add3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
905
906 #if WITH_PROFILE_MODEL_P
907 /* Record the fields for profiling. */
908 if (PROFILE_MODEL_P (current_cpu))
909 {
910 FLD (in_sr) = f_r2;
911 FLD (out_dr) = f_r1;
912 }
913 #endif
914 #undef FLD
915 BREAK (ex);
916 }
917
918 CASE (ex, FMT_AND3) :
919 {
920 CGEN_INSN_INT insn = entire_insn;
921 #define FLD(f) abuf->fields.fmt_and3.f
922 EXTRACT_IFMT_AND3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
923
924 EXTRACT_IFMT_AND3_CODE
925
926 /* Record the fields for the semantic handler. */
927 FLD (f_uimm16) = f_uimm16;
928 FLD (i_sr) = & CPU (h_gr)[f_r2];
929 FLD (i_dr) = & CPU (h_gr)[f_r1];
930 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_and3", "f_uimm16 0x%x", 'x', f_uimm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
931
932 #if WITH_PROFILE_MODEL_P
933 /* Record the fields for profiling. */
934 if (PROFILE_MODEL_P (current_cpu))
935 {
936 FLD (in_sr) = f_r2;
937 FLD (out_dr) = f_r1;
938 }
939 #endif
940 #undef FLD
941 BREAK (ex);
942 }
943
944 CASE (ex, FMT_OR3) :
945 {
946 CGEN_INSN_INT insn = entire_insn;
947 #define FLD(f) abuf->fields.fmt_or3.f
948 EXTRACT_IFMT_OR3_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
949
950 EXTRACT_IFMT_OR3_CODE
951
952 /* Record the fields for the semantic handler. */
953 FLD (f_uimm16) = f_uimm16;
954 FLD (i_sr) = & CPU (h_gr)[f_r2];
955 FLD (i_dr) = & CPU (h_gr)[f_r1];
956 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_or3", "f_uimm16 0x%x", 'x', f_uimm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
957
958 #if WITH_PROFILE_MODEL_P
959 /* Record the fields for profiling. */
960 if (PROFILE_MODEL_P (current_cpu))
961 {
962 FLD (in_sr) = f_r2;
963 FLD (out_dr) = f_r1;
964 }
965 #endif
966 #undef FLD
967 BREAK (ex);
968 }
969
970 CASE (ex, FMT_ADDI) :
971 {
972 CGEN_INSN_INT insn = entire_insn;
973 #define FLD(f) abuf->fields.fmt_addi.f
974 EXTRACT_IFMT_ADDI_VARS /* f-op1 f-r1 f-simm8 */
975
976 EXTRACT_IFMT_ADDI_CODE
977
978 /* Record the fields for the semantic handler. */
979 FLD (f_simm8) = f_simm8;
980 FLD (i_dr) = & CPU (h_gr)[f_r1];
981 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addi", "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0));
982
983 #if WITH_PROFILE_MODEL_P
984 /* Record the fields for profiling. */
985 if (PROFILE_MODEL_P (current_cpu))
986 {
987 FLD (in_dr) = f_r1;
988 FLD (out_dr) = f_r1;
989 }
990 #endif
991 #undef FLD
992 BREAK (ex);
993 }
994
995 CASE (ex, FMT_ADDV) :
996 {
997 CGEN_INSN_INT insn = entire_insn;
998 #define FLD(f) abuf->fields.fmt_addv.f
999 EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
1000
1001 EXTRACT_IFMT_ADD_CODE
1002
1003 /* Record the fields for the semantic handler. */
1004 FLD (i_dr) = & CPU (h_gr)[f_r1];
1005 FLD (i_sr) = & CPU (h_gr)[f_r2];
1006 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addv", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
1007
1008 #if WITH_PROFILE_MODEL_P
1009 /* Record the fields for profiling. */
1010 if (PROFILE_MODEL_P (current_cpu))
1011 {
1012 FLD (in_dr) = f_r1;
1013 FLD (in_sr) = f_r2;
1014 FLD (out_dr) = f_r1;
1015 }
1016 #endif
1017 #undef FLD
1018 BREAK (ex);
1019 }
1020
1021 CASE (ex, FMT_ADDV3) :
1022 {
1023 CGEN_INSN_INT insn = entire_insn;
1024 #define FLD(f) abuf->fields.fmt_addv3.f
1025 EXTRACT_IFMT_ADDV3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1026
1027 EXTRACT_IFMT_ADDV3_CODE
1028
1029 /* Record the fields for the semantic handler. */
1030 FLD (f_simm16) = f_simm16;
1031 FLD (i_sr) = & CPU (h_gr)[f_r2];
1032 FLD (i_dr) = & CPU (h_gr)[f_r1];
1033 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addv3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1034
1035 #if WITH_PROFILE_MODEL_P
1036 /* Record the fields for profiling. */
1037 if (PROFILE_MODEL_P (current_cpu))
1038 {
1039 FLD (in_sr) = f_r2;
1040 FLD (out_dr) = f_r1;
1041 }
1042 #endif
1043 #undef FLD
1044 BREAK (ex);
1045 }
1046
1047 CASE (ex, FMT_ADDX) :
1048 {
1049 CGEN_INSN_INT insn = entire_insn;
1050 #define FLD(f) abuf->fields.fmt_addx.f
1051 EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
1052
1053 EXTRACT_IFMT_ADD_CODE
1054
1055 /* Record the fields for the semantic handler. */
1056 FLD (i_dr) = & CPU (h_gr)[f_r1];
1057 FLD (i_sr) = & CPU (h_gr)[f_r2];
1058 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_addx", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
1059
1060 #if WITH_PROFILE_MODEL_P
1061 /* Record the fields for profiling. */
1062 if (PROFILE_MODEL_P (current_cpu))
1063 {
1064 FLD (in_dr) = f_r1;
1065 FLD (in_sr) = f_r2;
1066 FLD (out_dr) = f_r1;
1067 }
1068 #endif
1069 #undef FLD
1070 BREAK (ex);
1071 }
1072
1073 CASE (ex, FMT_BC8) :
1074 {
1075 CGEN_INSN_INT insn = entire_insn;
1076 #define FLD(f) abuf->fields.cti.fields.fmt_bc8.f
1077 EXTRACT_IFMT_BC8_VARS /* f-op1 f-r1 f-disp8 */
1078
1079 EXTRACT_IFMT_BC8_CODE
1080
1081 /* Record the fields for the semantic handler. */
1082 FLD (i_disp8) = f_disp8;
1083 SEM_BRANCH_INIT_EXTRACT (abuf);
1084 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bc8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
1085
1086 #if WITH_PROFILE_MODEL_P
1087 /* Record the fields for profiling. */
1088 if (PROFILE_MODEL_P (current_cpu))
1089 {
1090 }
1091 #endif
1092 #undef FLD
1093 BREAK (ex);
1094 }
1095
1096 CASE (ex, FMT_BC24) :
1097 {
1098 CGEN_INSN_INT insn = entire_insn;
1099 #define FLD(f) abuf->fields.cti.fields.fmt_bc24.f
1100 EXTRACT_IFMT_BC24_VARS /* f-op1 f-r1 f-disp24 */
1101
1102 EXTRACT_IFMT_BC24_CODE
1103
1104 /* Record the fields for the semantic handler. */
1105 FLD (i_disp24) = f_disp24;
1106 SEM_BRANCH_INIT_EXTRACT (abuf);
1107 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bc24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
1108
1109 #if WITH_PROFILE_MODEL_P
1110 /* Record the fields for profiling. */
1111 if (PROFILE_MODEL_P (current_cpu))
1112 {
1113 }
1114 #endif
1115 #undef FLD
1116 BREAK (ex);
1117 }
1118
1119 CASE (ex, FMT_BEQ) :
1120 {
1121 CGEN_INSN_INT insn = entire_insn;
1122 #define FLD(f) abuf->fields.cti.fields.fmt_beq.f
1123 EXTRACT_IFMT_BEQ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
1124
1125 EXTRACT_IFMT_BEQ_CODE
1126
1127 /* Record the fields for the semantic handler. */
1128 FLD (i_disp16) = f_disp16;
1129 FLD (i_src1) = & CPU (h_gr)[f_r1];
1130 FLD (i_src2) = & CPU (h_gr)[f_r2];
1131 SEM_BRANCH_INIT_EXTRACT (abuf);
1132 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_beq", "disp16 0x%x", 'x', f_disp16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1133
1134 #if WITH_PROFILE_MODEL_P
1135 /* Record the fields for profiling. */
1136 if (PROFILE_MODEL_P (current_cpu))
1137 {
1138 FLD (in_src1) = f_r1;
1139 FLD (in_src2) = f_r2;
1140 }
1141 #endif
1142 #undef FLD
1143 BREAK (ex);
1144 }
1145
1146 CASE (ex, FMT_BEQZ) :
1147 {
1148 CGEN_INSN_INT insn = entire_insn;
1149 #define FLD(f) abuf->fields.cti.fields.fmt_beqz.f
1150 EXTRACT_IFMT_BEQZ_VARS /* f-op1 f-r1 f-op2 f-r2 f-disp16 */
1151
1152 EXTRACT_IFMT_BEQZ_CODE
1153
1154 /* Record the fields for the semantic handler. */
1155 FLD (i_disp16) = f_disp16;
1156 FLD (i_src2) = & CPU (h_gr)[f_r2];
1157 SEM_BRANCH_INIT_EXTRACT (abuf);
1158 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_beqz", "disp16 0x%x", 'x', f_disp16, "src2 0x%x", 'x', f_r2, (char *) 0));
1159
1160 #if WITH_PROFILE_MODEL_P
1161 /* Record the fields for profiling. */
1162 if (PROFILE_MODEL_P (current_cpu))
1163 {
1164 FLD (in_src2) = f_r2;
1165 }
1166 #endif
1167 #undef FLD
1168 BREAK (ex);
1169 }
1170
1171 CASE (ex, FMT_BL8) :
1172 {
1173 CGEN_INSN_INT insn = entire_insn;
1174 #define FLD(f) abuf->fields.cti.fields.fmt_bl8.f
1175 EXTRACT_IFMT_BC8_VARS /* f-op1 f-r1 f-disp8 */
1176
1177 EXTRACT_IFMT_BC8_CODE
1178
1179 /* Record the fields for the semantic handler. */
1180 FLD (i_disp8) = f_disp8;
1181 SEM_BRANCH_INIT_EXTRACT (abuf);
1182 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
1183
1184 #if WITH_PROFILE_MODEL_P
1185 /* Record the fields for profiling. */
1186 if (PROFILE_MODEL_P (current_cpu))
1187 {
1188 FLD (out_h_gr_14) = 14;
1189 }
1190 #endif
1191 #undef FLD
1192 BREAK (ex);
1193 }
1194
1195 CASE (ex, FMT_BL24) :
1196 {
1197 CGEN_INSN_INT insn = entire_insn;
1198 #define FLD(f) abuf->fields.cti.fields.fmt_bl24.f
1199 EXTRACT_IFMT_BC24_VARS /* f-op1 f-r1 f-disp24 */
1200
1201 EXTRACT_IFMT_BC24_CODE
1202
1203 /* Record the fields for the semantic handler. */
1204 FLD (i_disp24) = f_disp24;
1205 SEM_BRANCH_INIT_EXTRACT (abuf);
1206 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
1207
1208 #if WITH_PROFILE_MODEL_P
1209 /* Record the fields for profiling. */
1210 if (PROFILE_MODEL_P (current_cpu))
1211 {
1212 FLD (out_h_gr_14) = 14;
1213 }
1214 #endif
1215 #undef FLD
1216 BREAK (ex);
1217 }
1218
1219 CASE (ex, FMT_BCL8) :
1220 {
1221 CGEN_INSN_INT insn = entire_insn;
1222 #define FLD(f) abuf->fields.cti.fields.fmt_bcl8.f
1223 EXTRACT_IFMT_BC8_VARS /* f-op1 f-r1 f-disp8 */
1224
1225 EXTRACT_IFMT_BC8_CODE
1226
1227 /* Record the fields for the semantic handler. */
1228 FLD (i_disp8) = f_disp8;
1229 SEM_BRANCH_INIT_EXTRACT (abuf);
1230 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bcl8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
1231
1232 #if WITH_PROFILE_MODEL_P
1233 /* Record the fields for profiling. */
1234 if (PROFILE_MODEL_P (current_cpu))
1235 {
1236 FLD (out_h_gr_14) = 14;
1237 }
1238 #endif
1239 #undef FLD
1240 BREAK (ex);
1241 }
1242
1243 CASE (ex, FMT_BCL24) :
1244 {
1245 CGEN_INSN_INT insn = entire_insn;
1246 #define FLD(f) abuf->fields.cti.fields.fmt_bcl24.f
1247 EXTRACT_IFMT_BC24_VARS /* f-op1 f-r1 f-disp24 */
1248
1249 EXTRACT_IFMT_BC24_CODE
1250
1251 /* Record the fields for the semantic handler. */
1252 FLD (i_disp24) = f_disp24;
1253 SEM_BRANCH_INIT_EXTRACT (abuf);
1254 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bcl24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
1255
1256 #if WITH_PROFILE_MODEL_P
1257 /* Record the fields for profiling. */
1258 if (PROFILE_MODEL_P (current_cpu))
1259 {
1260 FLD (out_h_gr_14) = 14;
1261 }
1262 #endif
1263 #undef FLD
1264 BREAK (ex);
1265 }
1266
1267 CASE (ex, FMT_BRA8) :
1268 {
1269 CGEN_INSN_INT insn = entire_insn;
1270 #define FLD(f) abuf->fields.cti.fields.fmt_bra8.f
1271 EXTRACT_IFMT_BC8_VARS /* f-op1 f-r1 f-disp8 */
1272
1273 EXTRACT_IFMT_BC8_CODE
1274
1275 /* Record the fields for the semantic handler. */
1276 FLD (i_disp8) = f_disp8;
1277 SEM_BRANCH_INIT_EXTRACT (abuf);
1278 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bra8", "disp8 0x%x", 'x', f_disp8, (char *) 0));
1279
1280 #if WITH_PROFILE_MODEL_P
1281 /* Record the fields for profiling. */
1282 if (PROFILE_MODEL_P (current_cpu))
1283 {
1284 }
1285 #endif
1286 #undef FLD
1287 BREAK (ex);
1288 }
1289
1290 CASE (ex, FMT_BRA24) :
1291 {
1292 CGEN_INSN_INT insn = entire_insn;
1293 #define FLD(f) abuf->fields.cti.fields.fmt_bra24.f
1294 EXTRACT_IFMT_BC24_VARS /* f-op1 f-r1 f-disp24 */
1295
1296 EXTRACT_IFMT_BC24_CODE
1297
1298 /* Record the fields for the semantic handler. */
1299 FLD (i_disp24) = f_disp24;
1300 SEM_BRANCH_INIT_EXTRACT (abuf);
1301 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_bra24", "disp24 0x%x", 'x', f_disp24, (char *) 0));
1302
1303 #if WITH_PROFILE_MODEL_P
1304 /* Record the fields for profiling. */
1305 if (PROFILE_MODEL_P (current_cpu))
1306 {
1307 }
1308 #endif
1309 #undef FLD
1310 BREAK (ex);
1311 }
1312
1313 CASE (ex, FMT_CMP) :
1314 {
1315 CGEN_INSN_INT insn = entire_insn;
1316 #define FLD(f) abuf->fields.fmt_cmp.f
1317 EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
1318
1319 EXTRACT_IFMT_CMP_CODE
1320
1321 /* Record the fields for the semantic handler. */
1322 FLD (i_src1) = & CPU (h_gr)[f_r1];
1323 FLD (i_src2) = & CPU (h_gr)[f_r2];
1324 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmp", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1325
1326 #if WITH_PROFILE_MODEL_P
1327 /* Record the fields for profiling. */
1328 if (PROFILE_MODEL_P (current_cpu))
1329 {
1330 FLD (in_src1) = f_r1;
1331 FLD (in_src2) = f_r2;
1332 }
1333 #endif
1334 #undef FLD
1335 BREAK (ex);
1336 }
1337
1338 CASE (ex, FMT_CMPI) :
1339 {
1340 CGEN_INSN_INT insn = entire_insn;
1341 #define FLD(f) abuf->fields.fmt_cmpi.f
1342 EXTRACT_IFMT_CMPI_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1343
1344 EXTRACT_IFMT_CMPI_CODE
1345
1346 /* Record the fields for the semantic handler. */
1347 FLD (f_simm16) = f_simm16;
1348 FLD (i_src2) = & CPU (h_gr)[f_r2];
1349 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpi", "f_simm16 0x%x", 'x', f_simm16, "src2 0x%x", 'x', f_r2, (char *) 0));
1350
1351 #if WITH_PROFILE_MODEL_P
1352 /* Record the fields for profiling. */
1353 if (PROFILE_MODEL_P (current_cpu))
1354 {
1355 FLD (in_src2) = f_r2;
1356 }
1357 #endif
1358 #undef FLD
1359 BREAK (ex);
1360 }
1361
1362 CASE (ex, FMT_CMPZ) :
1363 {
1364 CGEN_INSN_INT insn = entire_insn;
1365 #define FLD(f) abuf->fields.fmt_cmpz.f
1366 EXTRACT_IFMT_CMPZ_VARS /* f-op1 f-r1 f-op2 f-r2 */
1367
1368 EXTRACT_IFMT_CMPZ_CODE
1369
1370 /* Record the fields for the semantic handler. */
1371 FLD (i_src2) = & CPU (h_gr)[f_r2];
1372 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_cmpz", "src2 0x%x", 'x', f_r2, (char *) 0));
1373
1374 #if WITH_PROFILE_MODEL_P
1375 /* Record the fields for profiling. */
1376 if (PROFILE_MODEL_P (current_cpu))
1377 {
1378 FLD (in_src2) = f_r2;
1379 }
1380 #endif
1381 #undef FLD
1382 BREAK (ex);
1383 }
1384
1385 CASE (ex, FMT_DIV) :
1386 {
1387 CGEN_INSN_INT insn = entire_insn;
1388 #define FLD(f) abuf->fields.fmt_div.f
1389 EXTRACT_IFMT_DIV_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1390
1391 EXTRACT_IFMT_DIV_CODE
1392
1393 /* Record the fields for the semantic handler. */
1394 FLD (i_dr) = & CPU (h_gr)[f_r1];
1395 FLD (i_sr) = & CPU (h_gr)[f_r2];
1396 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_div", "dr 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
1397
1398 #if WITH_PROFILE_MODEL_P
1399 /* Record the fields for profiling. */
1400 if (PROFILE_MODEL_P (current_cpu))
1401 {
1402 FLD (in_dr) = f_r1;
1403 FLD (in_sr) = f_r2;
1404 FLD (out_dr) = f_r1;
1405 }
1406 #endif
1407 #undef FLD
1408 BREAK (ex);
1409 }
1410
1411 CASE (ex, FMT_JC) :
1412 {
1413 CGEN_INSN_INT insn = entire_insn;
1414 #define FLD(f) abuf->fields.cti.fields.fmt_jc.f
1415 EXTRACT_IFMT_JC_VARS /* f-op1 f-r1 f-op2 f-r2 */
1416
1417 EXTRACT_IFMT_JC_CODE
1418
1419 /* Record the fields for the semantic handler. */
1420 FLD (i_sr) = & CPU (h_gr)[f_r2];
1421 SEM_BRANCH_INIT_EXTRACT (abuf);
1422 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_jc", "sr 0x%x", 'x', f_r2, (char *) 0));
1423
1424 #if WITH_PROFILE_MODEL_P
1425 /* Record the fields for profiling. */
1426 if (PROFILE_MODEL_P (current_cpu))
1427 {
1428 FLD (in_sr) = f_r2;
1429 }
1430 #endif
1431 #undef FLD
1432 BREAK (ex);
1433 }
1434
1435 CASE (ex, FMT_JL) :
1436 {
1437 CGEN_INSN_INT insn = entire_insn;
1438 #define FLD(f) abuf->fields.cti.fields.fmt_jl.f
1439 EXTRACT_IFMT_JC_VARS /* f-op1 f-r1 f-op2 f-r2 */
1440
1441 EXTRACT_IFMT_JC_CODE
1442
1443 /* Record the fields for the semantic handler. */
1444 FLD (i_sr) = & CPU (h_gr)[f_r2];
1445 SEM_BRANCH_INIT_EXTRACT (abuf);
1446 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_jl", "sr 0x%x", 'x', f_r2, (char *) 0));
1447
1448 #if WITH_PROFILE_MODEL_P
1449 /* Record the fields for profiling. */
1450 if (PROFILE_MODEL_P (current_cpu))
1451 {
1452 FLD (in_sr) = f_r2;
1453 FLD (out_h_gr_14) = 14;
1454 }
1455 #endif
1456 #undef FLD
1457 BREAK (ex);
1458 }
1459
1460 CASE (ex, FMT_JMP) :
1461 {
1462 CGEN_INSN_INT insn = entire_insn;
1463 #define FLD(f) abuf->fields.cti.fields.fmt_jmp.f
1464 EXTRACT_IFMT_JC_VARS /* f-op1 f-r1 f-op2 f-r2 */
1465
1466 EXTRACT_IFMT_JC_CODE
1467
1468 /* Record the fields for the semantic handler. */
1469 FLD (i_sr) = & CPU (h_gr)[f_r2];
1470 SEM_BRANCH_INIT_EXTRACT (abuf);
1471 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_jmp", "sr 0x%x", 'x', f_r2, (char *) 0));
1472
1473 #if WITH_PROFILE_MODEL_P
1474 /* Record the fields for profiling. */
1475 if (PROFILE_MODEL_P (current_cpu))
1476 {
1477 FLD (in_sr) = f_r2;
1478 }
1479 #endif
1480 #undef FLD
1481 BREAK (ex);
1482 }
1483
1484 CASE (ex, FMT_LD) :
1485 {
1486 CGEN_INSN_INT insn = entire_insn;
1487 #define FLD(f) abuf->fields.fmt_ld.f
1488 EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
1489
1490 EXTRACT_IFMT_ADD_CODE
1491
1492 /* Record the fields for the semantic handler. */
1493 FLD (i_sr) = & CPU (h_gr)[f_r2];
1494 FLD (i_dr) = & CPU (h_gr)[f_r1];
1495 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1496
1497 #if WITH_PROFILE_MODEL_P
1498 /* Record the fields for profiling. */
1499 if (PROFILE_MODEL_P (current_cpu))
1500 {
1501 FLD (in_sr) = f_r2;
1502 FLD (out_dr) = f_r1;
1503 }
1504 #endif
1505 #undef FLD
1506 BREAK (ex);
1507 }
1508
1509 CASE (ex, FMT_LD_D) :
1510 {
1511 CGEN_INSN_INT insn = entire_insn;
1512 #define FLD(f) abuf->fields.fmt_ld_d.f
1513 EXTRACT_IFMT_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1514
1515 EXTRACT_IFMT_ADD3_CODE
1516
1517 /* Record the fields for the semantic handler. */
1518 FLD (f_simm16) = f_simm16;
1519 FLD (i_sr) = & CPU (h_gr)[f_r2];
1520 FLD (i_dr) = & CPU (h_gr)[f_r1];
1521 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_d", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1522
1523 #if WITH_PROFILE_MODEL_P
1524 /* Record the fields for profiling. */
1525 if (PROFILE_MODEL_P (current_cpu))
1526 {
1527 FLD (in_sr) = f_r2;
1528 FLD (out_dr) = f_r1;
1529 }
1530 #endif
1531 #undef FLD
1532 BREAK (ex);
1533 }
1534
1535 CASE (ex, FMT_LDB) :
1536 {
1537 CGEN_INSN_INT insn = entire_insn;
1538 #define FLD(f) abuf->fields.fmt_ldb.f
1539 EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
1540
1541 EXTRACT_IFMT_ADD_CODE
1542
1543 /* Record the fields for the semantic handler. */
1544 FLD (i_sr) = & CPU (h_gr)[f_r2];
1545 FLD (i_dr) = & CPU (h_gr)[f_r1];
1546 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldb", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1547
1548 #if WITH_PROFILE_MODEL_P
1549 /* Record the fields for profiling. */
1550 if (PROFILE_MODEL_P (current_cpu))
1551 {
1552 FLD (in_sr) = f_r2;
1553 FLD (out_dr) = f_r1;
1554 }
1555 #endif
1556 #undef FLD
1557 BREAK (ex);
1558 }
1559
1560 CASE (ex, FMT_LDB_D) :
1561 {
1562 CGEN_INSN_INT insn = entire_insn;
1563 #define FLD(f) abuf->fields.fmt_ldb_d.f
1564 EXTRACT_IFMT_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1565
1566 EXTRACT_IFMT_ADD3_CODE
1567
1568 /* Record the fields for the semantic handler. */
1569 FLD (f_simm16) = f_simm16;
1570 FLD (i_sr) = & CPU (h_gr)[f_r2];
1571 FLD (i_dr) = & CPU (h_gr)[f_r1];
1572 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldb_d", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1573
1574 #if WITH_PROFILE_MODEL_P
1575 /* Record the fields for profiling. */
1576 if (PROFILE_MODEL_P (current_cpu))
1577 {
1578 FLD (in_sr) = f_r2;
1579 FLD (out_dr) = f_r1;
1580 }
1581 #endif
1582 #undef FLD
1583 BREAK (ex);
1584 }
1585
1586 CASE (ex, FMT_LDH) :
1587 {
1588 CGEN_INSN_INT insn = entire_insn;
1589 #define FLD(f) abuf->fields.fmt_ldh.f
1590 EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
1591
1592 EXTRACT_IFMT_ADD_CODE
1593
1594 /* Record the fields for the semantic handler. */
1595 FLD (i_sr) = & CPU (h_gr)[f_r2];
1596 FLD (i_dr) = & CPU (h_gr)[f_r1];
1597 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldh", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1598
1599 #if WITH_PROFILE_MODEL_P
1600 /* Record the fields for profiling. */
1601 if (PROFILE_MODEL_P (current_cpu))
1602 {
1603 FLD (in_sr) = f_r2;
1604 FLD (out_dr) = f_r1;
1605 }
1606 #endif
1607 #undef FLD
1608 BREAK (ex);
1609 }
1610
1611 CASE (ex, FMT_LDH_D) :
1612 {
1613 CGEN_INSN_INT insn = entire_insn;
1614 #define FLD(f) abuf->fields.fmt_ldh_d.f
1615 EXTRACT_IFMT_ADD3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1616
1617 EXTRACT_IFMT_ADD3_CODE
1618
1619 /* Record the fields for the semantic handler. */
1620 FLD (f_simm16) = f_simm16;
1621 FLD (i_sr) = & CPU (h_gr)[f_r2];
1622 FLD (i_dr) = & CPU (h_gr)[f_r1];
1623 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldh_d", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1624
1625 #if WITH_PROFILE_MODEL_P
1626 /* Record the fields for profiling. */
1627 if (PROFILE_MODEL_P (current_cpu))
1628 {
1629 FLD (in_sr) = f_r2;
1630 FLD (out_dr) = f_r1;
1631 }
1632 #endif
1633 #undef FLD
1634 BREAK (ex);
1635 }
1636
1637 CASE (ex, FMT_LD_PLUS) :
1638 {
1639 CGEN_INSN_INT insn = entire_insn;
1640 #define FLD(f) abuf->fields.fmt_ld_plus.f
1641 EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
1642
1643 EXTRACT_IFMT_ADD_CODE
1644
1645 /* Record the fields for the semantic handler. */
1646 FLD (i_sr) = & CPU (h_gr)[f_r2];
1647 FLD (i_dr) = & CPU (h_gr)[f_r1];
1648 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld_plus", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1649
1650 #if WITH_PROFILE_MODEL_P
1651 /* Record the fields for profiling. */
1652 if (PROFILE_MODEL_P (current_cpu))
1653 {
1654 FLD (in_sr) = f_r2;
1655 FLD (out_dr) = f_r1;
1656 FLD (out_sr) = f_r2;
1657 }
1658 #endif
1659 #undef FLD
1660 BREAK (ex);
1661 }
1662
1663 CASE (ex, FMT_LD24) :
1664 {
1665 CGEN_INSN_INT insn = entire_insn;
1666 #define FLD(f) abuf->fields.fmt_ld24.f
1667 EXTRACT_IFMT_LD24_VARS /* f-op1 f-r1 f-uimm24 */
1668
1669 EXTRACT_IFMT_LD24_CODE
1670
1671 /* Record the fields for the semantic handler. */
1672 FLD (i_uimm24) = f_uimm24;
1673 FLD (i_dr) = & CPU (h_gr)[f_r1];
1674 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ld24", "uimm24 0x%x", 'x', f_uimm24, "dr 0x%x", 'x', f_r1, (char *) 0));
1675
1676 #if WITH_PROFILE_MODEL_P
1677 /* Record the fields for profiling. */
1678 if (PROFILE_MODEL_P (current_cpu))
1679 {
1680 FLD (out_dr) = f_r1;
1681 }
1682 #endif
1683 #undef FLD
1684 BREAK (ex);
1685 }
1686
1687 CASE (ex, FMT_LDI8) :
1688 {
1689 CGEN_INSN_INT insn = entire_insn;
1690 #define FLD(f) abuf->fields.fmt_ldi8.f
1691 EXTRACT_IFMT_ADDI_VARS /* f-op1 f-r1 f-simm8 */
1692
1693 EXTRACT_IFMT_ADDI_CODE
1694
1695 /* Record the fields for the semantic handler. */
1696 FLD (f_simm8) = f_simm8;
1697 FLD (i_dr) = & CPU (h_gr)[f_r1];
1698 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldi8", "f_simm8 0x%x", 'x', f_simm8, "dr 0x%x", 'x', f_r1, (char *) 0));
1699
1700 #if WITH_PROFILE_MODEL_P
1701 /* Record the fields for profiling. */
1702 if (PROFILE_MODEL_P (current_cpu))
1703 {
1704 FLD (out_dr) = f_r1;
1705 }
1706 #endif
1707 #undef FLD
1708 BREAK (ex);
1709 }
1710
1711 CASE (ex, FMT_LDI16) :
1712 {
1713 CGEN_INSN_INT insn = entire_insn;
1714 #define FLD(f) abuf->fields.fmt_ldi16.f
1715 EXTRACT_IFMT_LDI16_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
1716
1717 EXTRACT_IFMT_LDI16_CODE
1718
1719 /* Record the fields for the semantic handler. */
1720 FLD (f_simm16) = f_simm16;
1721 FLD (i_dr) = & CPU (h_gr)[f_r1];
1722 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_ldi16", "f_simm16 0x%x", 'x', f_simm16, "dr 0x%x", 'x', f_r1, (char *) 0));
1723
1724 #if WITH_PROFILE_MODEL_P
1725 /* Record the fields for profiling. */
1726 if (PROFILE_MODEL_P (current_cpu))
1727 {
1728 FLD (out_dr) = f_r1;
1729 }
1730 #endif
1731 #undef FLD
1732 BREAK (ex);
1733 }
1734
1735 CASE (ex, FMT_LOCK) :
1736 {
1737 CGEN_INSN_INT insn = entire_insn;
1738 #define FLD(f) abuf->fields.fmt_lock.f
1739 EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
1740
1741 EXTRACT_IFMT_ADD_CODE
1742
1743 /* Record the fields for the semantic handler. */
1744 FLD (i_sr) = & CPU (h_gr)[f_r2];
1745 FLD (i_dr) = & CPU (h_gr)[f_r1];
1746 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_lock", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1747
1748 #if WITH_PROFILE_MODEL_P
1749 /* Record the fields for profiling. */
1750 if (PROFILE_MODEL_P (current_cpu))
1751 {
1752 FLD (in_sr) = f_r2;
1753 FLD (out_dr) = f_r1;
1754 }
1755 #endif
1756 #undef FLD
1757 BREAK (ex);
1758 }
1759
1760 CASE (ex, FMT_MACHI_A) :
1761 {
1762 CGEN_INSN_INT insn = entire_insn;
1763 #define FLD(f) abuf->fields.fmt_machi_a.f
1764 EXTRACT_IFMT_MACHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */
1765
1766 EXTRACT_IFMT_MACHI_A_CODE
1767
1768 /* Record the fields for the semantic handler. */
1769 FLD (f_acc) = f_acc;
1770 FLD (i_src1) = & CPU (h_gr)[f_r1];
1771 FLD (i_src2) = & CPU (h_gr)[f_r2];
1772 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_machi_a", "f_acc 0x%x", 'x', f_acc, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1773
1774 #if WITH_PROFILE_MODEL_P
1775 /* Record the fields for profiling. */
1776 if (PROFILE_MODEL_P (current_cpu))
1777 {
1778 FLD (in_src1) = f_r1;
1779 FLD (in_src2) = f_r2;
1780 }
1781 #endif
1782 #undef FLD
1783 BREAK (ex);
1784 }
1785
1786 CASE (ex, FMT_MULHI_A) :
1787 {
1788 CGEN_INSN_INT insn = entire_insn;
1789 #define FLD(f) abuf->fields.fmt_mulhi_a.f
1790 EXTRACT_IFMT_MACHI_A_VARS /* f-op1 f-r1 f-acc f-op23 f-r2 */
1791
1792 EXTRACT_IFMT_MACHI_A_CODE
1793
1794 /* Record the fields for the semantic handler. */
1795 FLD (f_acc) = f_acc;
1796 FLD (i_src1) = & CPU (h_gr)[f_r1];
1797 FLD (i_src2) = & CPU (h_gr)[f_r2];
1798 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mulhi_a", "f_acc 0x%x", 'x', f_acc, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
1799
1800 #if WITH_PROFILE_MODEL_P
1801 /* Record the fields for profiling. */
1802 if (PROFILE_MODEL_P (current_cpu))
1803 {
1804 FLD (in_src1) = f_r1;
1805 FLD (in_src2) = f_r2;
1806 }
1807 #endif
1808 #undef FLD
1809 BREAK (ex);
1810 }
1811
1812 CASE (ex, FMT_MV) :
1813 {
1814 CGEN_INSN_INT insn = entire_insn;
1815 #define FLD(f) abuf->fields.fmt_mv.f
1816 EXTRACT_IFMT_ADD_VARS /* f-op1 f-r1 f-op2 f-r2 */
1817
1818 EXTRACT_IFMT_ADD_CODE
1819
1820 /* Record the fields for the semantic handler. */
1821 FLD (i_sr) = & CPU (h_gr)[f_r2];
1822 FLD (i_dr) = & CPU (h_gr)[f_r1];
1823 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mv", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1824
1825 #if WITH_PROFILE_MODEL_P
1826 /* Record the fields for profiling. */
1827 if (PROFILE_MODEL_P (current_cpu))
1828 {
1829 FLD (in_sr) = f_r2;
1830 FLD (out_dr) = f_r1;
1831 }
1832 #endif
1833 #undef FLD
1834 BREAK (ex);
1835 }
1836
1837 CASE (ex, FMT_MVFACHI_A) :
1838 {
1839 CGEN_INSN_INT insn = entire_insn;
1840 #define FLD(f) abuf->fields.fmt_mvfachi_a.f
1841 EXTRACT_IFMT_MVFACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
1842
1843 EXTRACT_IFMT_MVFACHI_A_CODE
1844
1845 /* Record the fields for the semantic handler. */
1846 FLD (f_accs) = f_accs;
1847 FLD (i_dr) = & CPU (h_gr)[f_r1];
1848 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvfachi_a", "f_accs 0x%x", 'x', f_accs, "dr 0x%x", 'x', f_r1, (char *) 0));
1849
1850 #if WITH_PROFILE_MODEL_P
1851 /* Record the fields for profiling. */
1852 if (PROFILE_MODEL_P (current_cpu))
1853 {
1854 FLD (out_dr) = f_r1;
1855 }
1856 #endif
1857 #undef FLD
1858 BREAK (ex);
1859 }
1860
1861 CASE (ex, FMT_MVFC) :
1862 {
1863 CGEN_INSN_INT insn = entire_insn;
1864 #define FLD(f) abuf->fields.fmt_mvfc.f
1865 EXTRACT_IFMT_MVFC_VARS /* f-op1 f-r1 f-op2 f-r2 */
1866
1867 EXTRACT_IFMT_MVFC_CODE
1868
1869 /* Record the fields for the semantic handler. */
1870 FLD (f_r2) = f_r2;
1871 FLD (i_dr) = & CPU (h_gr)[f_r1];
1872 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvfc", "f_r2 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
1873
1874 #if WITH_PROFILE_MODEL_P
1875 /* Record the fields for profiling. */
1876 if (PROFILE_MODEL_P (current_cpu))
1877 {
1878 FLD (out_dr) = f_r1;
1879 }
1880 #endif
1881 #undef FLD
1882 BREAK (ex);
1883 }
1884
1885 CASE (ex, FMT_MVTACHI_A) :
1886 {
1887 CGEN_INSN_INT insn = entire_insn;
1888 #define FLD(f) abuf->fields.fmt_mvtachi_a.f
1889 EXTRACT_IFMT_MVTACHI_A_VARS /* f-op1 f-r1 f-op2 f-accs f-op3 */
1890
1891 EXTRACT_IFMT_MVTACHI_A_CODE
1892
1893 /* Record the fields for the semantic handler. */
1894 FLD (f_accs) = f_accs;
1895 FLD (i_src1) = & CPU (h_gr)[f_r1];
1896 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvtachi_a", "f_accs 0x%x", 'x', f_accs, "src1 0x%x", 'x', f_r1, (char *) 0));
1897
1898 #if WITH_PROFILE_MODEL_P
1899 /* Record the fields for profiling. */
1900 if (PROFILE_MODEL_P (current_cpu))
1901 {
1902 FLD (in_src1) = f_r1;
1903 }
1904 #endif
1905 #undef FLD
1906 BREAK (ex);
1907 }
1908
1909 CASE (ex, FMT_MVTC) :
1910 {
1911 CGEN_INSN_INT insn = entire_insn;
1912 #define FLD(f) abuf->fields.fmt_mvtc.f
1913 EXTRACT_IFMT_MVTC_VARS /* f-op1 f-r1 f-op2 f-r2 */
1914
1915 EXTRACT_IFMT_MVTC_CODE
1916
1917 /* Record the fields for the semantic handler. */
1918 FLD (f_r1) = f_r1;
1919 FLD (i_sr) = & CPU (h_gr)[f_r2];
1920 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mvtc", "f_r1 0x%x", 'x', f_r1, "sr 0x%x", 'x', f_r2, (char *) 0));
1921
1922 #if WITH_PROFILE_MODEL_P
1923 /* Record the fields for profiling. */
1924 if (PROFILE_MODEL_P (current_cpu))
1925 {
1926 FLD (in_sr) = f_r2;
1927 }
1928 #endif
1929 #undef FLD
1930 BREAK (ex);
1931 }
1932
1933 CASE (ex, FMT_NOP) :
1934 {
1935 CGEN_INSN_INT insn = entire_insn;
1936 #define FLD(f) abuf->fields.fmt_nop.f
1937 EXTRACT_IFMT_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */
1938
1939 EXTRACT_IFMT_NOP_CODE
1940
1941 /* Record the fields for the semantic handler. */
1942 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_nop", (char *) 0));
1943
1944 #undef FLD
1945 BREAK (ex);
1946 }
1947
1948 CASE (ex, FMT_RAC_DSI) :
1949 {
1950 CGEN_INSN_INT insn = entire_insn;
1951 #define FLD(f) abuf->fields.fmt_rac_dsi.f
1952 EXTRACT_IFMT_RAC_DSI_VARS /* f-op1 f-accd f-bits67 f-op2 f-accs f-bit14 f-imm1 */
1953
1954 EXTRACT_IFMT_RAC_DSI_CODE
1955
1956 /* Record the fields for the semantic handler. */
1957 FLD (f_accs) = f_accs;
1958 FLD (f_imm1) = f_imm1;
1959 FLD (f_accd) = f_accd;
1960 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_rac_dsi", "f_accs 0x%x", 'x', f_accs, "f_imm1 0x%x", 'x', f_imm1, "f_accd 0x%x", 'x', f_accd, (char *) 0));
1961
1962 #undef FLD
1963 BREAK (ex);
1964 }
1965
1966 CASE (ex, FMT_RTE) :
1967 {
1968 CGEN_INSN_INT insn = entire_insn;
1969 #define FLD(f) abuf->fields.cti.fields.fmt_rte.f
1970 EXTRACT_IFMT_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */
1971
1972 EXTRACT_IFMT_NOP_CODE
1973
1974 /* Record the fields for the semantic handler. */
1975 SEM_BRANCH_INIT_EXTRACT (abuf);
1976 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_rte", (char *) 0));
1977
1978 #if WITH_PROFILE_MODEL_P
1979 /* Record the fields for profiling. */
1980 if (PROFILE_MODEL_P (current_cpu))
1981 {
1982 }
1983 #endif
1984 #undef FLD
1985 BREAK (ex);
1986 }
1987
1988 CASE (ex, FMT_SETH) :
1989 {
1990 CGEN_INSN_INT insn = entire_insn;
1991 #define FLD(f) abuf->fields.fmt_seth.f
1992 EXTRACT_IFMT_SETH_VARS /* f-op1 f-r1 f-op2 f-r2 f-hi16 */
1993
1994 EXTRACT_IFMT_SETH_CODE
1995
1996 /* Record the fields for the semantic handler. */
1997 FLD (f_hi16) = f_hi16;
1998 FLD (i_dr) = & CPU (h_gr)[f_r1];
1999 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_seth", "f_hi16 0x%x", 'x', f_hi16, "dr 0x%x", 'x', f_r1, (char *) 0));
2000
2001 #if WITH_PROFILE_MODEL_P
2002 /* Record the fields for profiling. */
2003 if (PROFILE_MODEL_P (current_cpu))
2004 {
2005 FLD (out_dr) = f_r1;
2006 }
2007 #endif
2008 #undef FLD
2009 BREAK (ex);
2010 }
2011
2012 CASE (ex, FMT_SLL3) :
2013 {
2014 CGEN_INSN_INT insn = entire_insn;
2015 #define FLD(f) abuf->fields.fmt_sll3.f
2016 EXTRACT_IFMT_ADDV3_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
2017
2018 EXTRACT_IFMT_ADDV3_CODE
2019
2020 /* Record the fields for the semantic handler. */
2021 FLD (f_simm16) = f_simm16;
2022 FLD (i_sr) = & CPU (h_gr)[f_r2];
2023 FLD (i_dr) = & CPU (h_gr)[f_r1];
2024 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sll3", "f_simm16 0x%x", 'x', f_simm16, "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
2025
2026 #if WITH_PROFILE_MODEL_P
2027 /* Record the fields for profiling. */
2028 if (PROFILE_MODEL_P (current_cpu))
2029 {
2030 FLD (in_sr) = f_r2;
2031 FLD (out_dr) = f_r1;
2032 }
2033 #endif
2034 #undef FLD
2035 BREAK (ex);
2036 }
2037
2038 CASE (ex, FMT_SLLI) :
2039 {
2040 CGEN_INSN_INT insn = entire_insn;
2041 #define FLD(f) abuf->fields.fmt_slli.f
2042 EXTRACT_IFMT_SLLI_VARS /* f-op1 f-r1 f-shift-op2 f-uimm5 */
2043
2044 EXTRACT_IFMT_SLLI_CODE
2045
2046 /* Record the fields for the semantic handler. */
2047 FLD (f_uimm5) = f_uimm5;
2048 FLD (i_dr) = & CPU (h_gr)[f_r1];
2049 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_slli", "f_uimm5 0x%x", 'x', f_uimm5, "dr 0x%x", 'x', f_r1, (char *) 0));
2050
2051 #if WITH_PROFILE_MODEL_P
2052 /* Record the fields for profiling. */
2053 if (PROFILE_MODEL_P (current_cpu))
2054 {
2055 FLD (in_dr) = f_r1;
2056 FLD (out_dr) = f_r1;
2057 }
2058 #endif
2059 #undef FLD
2060 BREAK (ex);
2061 }
2062
2063 CASE (ex, FMT_ST) :
2064 {
2065 CGEN_INSN_INT insn = entire_insn;
2066 #define FLD(f) abuf->fields.fmt_st.f
2067 EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
2068
2069 EXTRACT_IFMT_CMP_CODE
2070
2071 /* Record the fields for the semantic handler. */
2072 FLD (i_src1) = & CPU (h_gr)[f_r1];
2073 FLD (i_src2) = & CPU (h_gr)[f_r2];
2074 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2075
2076 #if WITH_PROFILE_MODEL_P
2077 /* Record the fields for profiling. */
2078 if (PROFILE_MODEL_P (current_cpu))
2079 {
2080 FLD (in_src1) = f_r1;
2081 FLD (in_src2) = f_r2;
2082 }
2083 #endif
2084 #undef FLD
2085 BREAK (ex);
2086 }
2087
2088 CASE (ex, FMT_ST_D) :
2089 {
2090 CGEN_INSN_INT insn = entire_insn;
2091 #define FLD(f) abuf->fields.fmt_st_d.f
2092 EXTRACT_IFMT_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
2093
2094 EXTRACT_IFMT_ST_D_CODE
2095
2096 /* Record the fields for the semantic handler. */
2097 FLD (f_simm16) = f_simm16;
2098 FLD (i_src1) = & CPU (h_gr)[f_r1];
2099 FLD (i_src2) = & CPU (h_gr)[f_r2];
2100 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_d", "f_simm16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2101
2102 #if WITH_PROFILE_MODEL_P
2103 /* Record the fields for profiling. */
2104 if (PROFILE_MODEL_P (current_cpu))
2105 {
2106 FLD (in_src1) = f_r1;
2107 FLD (in_src2) = f_r2;
2108 }
2109 #endif
2110 #undef FLD
2111 BREAK (ex);
2112 }
2113
2114 CASE (ex, FMT_STB) :
2115 {
2116 CGEN_INSN_INT insn = entire_insn;
2117 #define FLD(f) abuf->fields.fmt_stb.f
2118 EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
2119
2120 EXTRACT_IFMT_CMP_CODE
2121
2122 /* Record the fields for the semantic handler. */
2123 FLD (i_src1) = & CPU (h_gr)[f_r1];
2124 FLD (i_src2) = & CPU (h_gr)[f_r2];
2125 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stb", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2126
2127 #if WITH_PROFILE_MODEL_P
2128 /* Record the fields for profiling. */
2129 if (PROFILE_MODEL_P (current_cpu))
2130 {
2131 FLD (in_src1) = f_r1;
2132 FLD (in_src2) = f_r2;
2133 }
2134 #endif
2135 #undef FLD
2136 BREAK (ex);
2137 }
2138
2139 CASE (ex, FMT_STB_D) :
2140 {
2141 CGEN_INSN_INT insn = entire_insn;
2142 #define FLD(f) abuf->fields.fmt_stb_d.f
2143 EXTRACT_IFMT_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
2144
2145 EXTRACT_IFMT_ST_D_CODE
2146
2147 /* Record the fields for the semantic handler. */
2148 FLD (f_simm16) = f_simm16;
2149 FLD (i_src1) = & CPU (h_gr)[f_r1];
2150 FLD (i_src2) = & CPU (h_gr)[f_r2];
2151 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_stb_d", "f_simm16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2152
2153 #if WITH_PROFILE_MODEL_P
2154 /* Record the fields for profiling. */
2155 if (PROFILE_MODEL_P (current_cpu))
2156 {
2157 FLD (in_src1) = f_r1;
2158 FLD (in_src2) = f_r2;
2159 }
2160 #endif
2161 #undef FLD
2162 BREAK (ex);
2163 }
2164
2165 CASE (ex, FMT_STH) :
2166 {
2167 CGEN_INSN_INT insn = entire_insn;
2168 #define FLD(f) abuf->fields.fmt_sth.f
2169 EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
2170
2171 EXTRACT_IFMT_CMP_CODE
2172
2173 /* Record the fields for the semantic handler. */
2174 FLD (i_src1) = & CPU (h_gr)[f_r1];
2175 FLD (i_src2) = & CPU (h_gr)[f_r2];
2176 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sth", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2177
2178 #if WITH_PROFILE_MODEL_P
2179 /* Record the fields for profiling. */
2180 if (PROFILE_MODEL_P (current_cpu))
2181 {
2182 FLD (in_src1) = f_r1;
2183 FLD (in_src2) = f_r2;
2184 }
2185 #endif
2186 #undef FLD
2187 BREAK (ex);
2188 }
2189
2190 CASE (ex, FMT_STH_D) :
2191 {
2192 CGEN_INSN_INT insn = entire_insn;
2193 #define FLD(f) abuf->fields.fmt_sth_d.f
2194 EXTRACT_IFMT_ST_D_VARS /* f-op1 f-r1 f-op2 f-r2 f-simm16 */
2195
2196 EXTRACT_IFMT_ST_D_CODE
2197
2198 /* Record the fields for the semantic handler. */
2199 FLD (f_simm16) = f_simm16;
2200 FLD (i_src1) = & CPU (h_gr)[f_r1];
2201 FLD (i_src2) = & CPU (h_gr)[f_r2];
2202 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sth_d", "f_simm16 0x%x", 'x', f_simm16, "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2203
2204 #if WITH_PROFILE_MODEL_P
2205 /* Record the fields for profiling. */
2206 if (PROFILE_MODEL_P (current_cpu))
2207 {
2208 FLD (in_src1) = f_r1;
2209 FLD (in_src2) = f_r2;
2210 }
2211 #endif
2212 #undef FLD
2213 BREAK (ex);
2214 }
2215
2216 CASE (ex, FMT_ST_PLUS) :
2217 {
2218 CGEN_INSN_INT insn = entire_insn;
2219 #define FLD(f) abuf->fields.fmt_st_plus.f
2220 EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
2221
2222 EXTRACT_IFMT_CMP_CODE
2223
2224 /* Record the fields for the semantic handler. */
2225 FLD (i_src1) = & CPU (h_gr)[f_r1];
2226 FLD (i_src2) = & CPU (h_gr)[f_r2];
2227 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_st_plus", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2228
2229 #if WITH_PROFILE_MODEL_P
2230 /* Record the fields for profiling. */
2231 if (PROFILE_MODEL_P (current_cpu))
2232 {
2233 FLD (in_src1) = f_r1;
2234 FLD (in_src2) = f_r2;
2235 FLD (out_src2) = f_r2;
2236 }
2237 #endif
2238 #undef FLD
2239 BREAK (ex);
2240 }
2241
2242 CASE (ex, FMT_TRAP) :
2243 {
2244 CGEN_INSN_INT insn = entire_insn;
2245 #define FLD(f) abuf->fields.cti.fields.fmt_trap.f
2246 EXTRACT_IFMT_TRAP_VARS /* f-op1 f-r1 f-op2 f-uimm4 */
2247
2248 EXTRACT_IFMT_TRAP_CODE
2249
2250 /* Record the fields for the semantic handler. */
2251 FLD (f_uimm4) = f_uimm4;
2252 SEM_BRANCH_INIT_EXTRACT (abuf);
2253 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_trap", "f_uimm4 0x%x", 'x', f_uimm4, (char *) 0));
2254
2255 #if WITH_PROFILE_MODEL_P
2256 /* Record the fields for profiling. */
2257 if (PROFILE_MODEL_P (current_cpu))
2258 {
2259 }
2260 #endif
2261 #undef FLD
2262 BREAK (ex);
2263 }
2264
2265 CASE (ex, FMT_UNLOCK) :
2266 {
2267 CGEN_INSN_INT insn = entire_insn;
2268 #define FLD(f) abuf->fields.fmt_unlock.f
2269 EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
2270
2271 EXTRACT_IFMT_CMP_CODE
2272
2273 /* Record the fields for the semantic handler. */
2274 FLD (i_src1) = & CPU (h_gr)[f_r1];
2275 FLD (i_src2) = & CPU (h_gr)[f_r2];
2276 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_unlock", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2277
2278 #if WITH_PROFILE_MODEL_P
2279 /* Record the fields for profiling. */
2280 if (PROFILE_MODEL_P (current_cpu))
2281 {
2282 FLD (in_src1) = f_r1;
2283 FLD (in_src2) = f_r2;
2284 }
2285 #endif
2286 #undef FLD
2287 BREAK (ex);
2288 }
2289
2290 CASE (ex, FMT_SATB) :
2291 {
2292 CGEN_INSN_INT insn = entire_insn;
2293 #define FLD(f) abuf->fields.fmt_satb.f
2294 EXTRACT_IFMT_SATB_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
2295
2296 EXTRACT_IFMT_SATB_CODE
2297
2298 /* Record the fields for the semantic handler. */
2299 FLD (i_sr) = & CPU (h_gr)[f_r2];
2300 FLD (i_dr) = & CPU (h_gr)[f_r1];
2301 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_satb", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
2302
2303 #if WITH_PROFILE_MODEL_P
2304 /* Record the fields for profiling. */
2305 if (PROFILE_MODEL_P (current_cpu))
2306 {
2307 FLD (in_sr) = f_r2;
2308 FLD (out_dr) = f_r1;
2309 }
2310 #endif
2311 #undef FLD
2312 BREAK (ex);
2313 }
2314
2315 CASE (ex, FMT_SAT) :
2316 {
2317 CGEN_INSN_INT insn = entire_insn;
2318 #define FLD(f) abuf->fields.fmt_sat.f
2319 EXTRACT_IFMT_SATB_VARS /* f-op1 f-r1 f-op2 f-r2 f-uimm16 */
2320
2321 EXTRACT_IFMT_SATB_CODE
2322
2323 /* Record the fields for the semantic handler. */
2324 FLD (i_sr) = & CPU (h_gr)[f_r2];
2325 FLD (i_dr) = & CPU (h_gr)[f_r1];
2326 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sat", "sr 0x%x", 'x', f_r2, "dr 0x%x", 'x', f_r1, (char *) 0));
2327
2328 #if WITH_PROFILE_MODEL_P
2329 /* Record the fields for profiling. */
2330 if (PROFILE_MODEL_P (current_cpu))
2331 {
2332 FLD (in_sr) = f_r2;
2333 FLD (out_dr) = f_r1;
2334 }
2335 #endif
2336 #undef FLD
2337 BREAK (ex);
2338 }
2339
2340 CASE (ex, FMT_SADD) :
2341 {
2342 CGEN_INSN_INT insn = entire_insn;
2343 #define FLD(f) abuf->fields.fmt_sadd.f
2344 EXTRACT_IFMT_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */
2345
2346 EXTRACT_IFMT_NOP_CODE
2347
2348 /* Record the fields for the semantic handler. */
2349 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sadd", (char *) 0));
2350
2351 #undef FLD
2352 BREAK (ex);
2353 }
2354
2355 CASE (ex, FMT_MACWU1) :
2356 {
2357 CGEN_INSN_INT insn = entire_insn;
2358 #define FLD(f) abuf->fields.fmt_macwu1.f
2359 EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
2360
2361 EXTRACT_IFMT_CMP_CODE
2362
2363 /* Record the fields for the semantic handler. */
2364 FLD (i_src1) = & CPU (h_gr)[f_r1];
2365 FLD (i_src2) = & CPU (h_gr)[f_r2];
2366 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_macwu1", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2367
2368 #if WITH_PROFILE_MODEL_P
2369 /* Record the fields for profiling. */
2370 if (PROFILE_MODEL_P (current_cpu))
2371 {
2372 FLD (in_src1) = f_r1;
2373 FLD (in_src2) = f_r2;
2374 }
2375 #endif
2376 #undef FLD
2377 BREAK (ex);
2378 }
2379
2380 CASE (ex, FMT_MSBLO) :
2381 {
2382 CGEN_INSN_INT insn = entire_insn;
2383 #define FLD(f) abuf->fields.fmt_msblo.f
2384 EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
2385
2386 EXTRACT_IFMT_CMP_CODE
2387
2388 /* Record the fields for the semantic handler. */
2389 FLD (i_src1) = & CPU (h_gr)[f_r1];
2390 FLD (i_src2) = & CPU (h_gr)[f_r2];
2391 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_msblo", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2392
2393 #if WITH_PROFILE_MODEL_P
2394 /* Record the fields for profiling. */
2395 if (PROFILE_MODEL_P (current_cpu))
2396 {
2397 FLD (in_src1) = f_r1;
2398 FLD (in_src2) = f_r2;
2399 }
2400 #endif
2401 #undef FLD
2402 BREAK (ex);
2403 }
2404
2405 CASE (ex, FMT_MULWU1) :
2406 {
2407 CGEN_INSN_INT insn = entire_insn;
2408 #define FLD(f) abuf->fields.fmt_mulwu1.f
2409 EXTRACT_IFMT_CMP_VARS /* f-op1 f-r1 f-op2 f-r2 */
2410
2411 EXTRACT_IFMT_CMP_CODE
2412
2413 /* Record the fields for the semantic handler. */
2414 FLD (i_src1) = & CPU (h_gr)[f_r1];
2415 FLD (i_src2) = & CPU (h_gr)[f_r2];
2416 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_mulwu1", "src1 0x%x", 'x', f_r1, "src2 0x%x", 'x', f_r2, (char *) 0));
2417
2418 #if WITH_PROFILE_MODEL_P
2419 /* Record the fields for profiling. */
2420 if (PROFILE_MODEL_P (current_cpu))
2421 {
2422 FLD (in_src1) = f_r1;
2423 FLD (in_src2) = f_r2;
2424 }
2425 #endif
2426 #undef FLD
2427 BREAK (ex);
2428 }
2429
2430 CASE (ex, FMT_SC) :
2431 {
2432 CGEN_INSN_INT insn = entire_insn;
2433 #define FLD(f) abuf->fields.cti.fields.fmt_sc.f
2434 EXTRACT_IFMT_NOP_VARS /* f-op1 f-r1 f-op2 f-r2 */
2435
2436 EXTRACT_IFMT_NOP_CODE
2437
2438 /* Record the fields for the semantic handler. */
2439 SEM_BRANCH_INIT_EXTRACT (abuf);
2440 TRACE_EXTRACT (current_cpu, abuf, (current_cpu, pc, "fmt_sc", (char *) 0));
2441
2442 #undef FLD
2443 BREAK (ex);
2444 }
2445
2446
2447 }
2448 ENDSWITCH (ex)
2449
2450 }
2451
2452 return idecode->idesc;
2453 }
The GNU Binutils are a collection of binary tools.