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* "objcopy -O binary" warning tweak, suggested by dmoseley
[binutils-gdb.git] / sim / mn10300 / simops.c
blob7a190566bcb68b167e027053eb8946351e4286f3
1 #include "config.h"
2
3 #include <signal.h>
4 #ifdef HAVE_UNISTD_H
5 #include <unistd.h>
6 #endif
7 #include "mn10300_sim.h"
8 #include "simops.h"
9 #include "sim-types.h"
10 #include "targ-vals.h"
11 #include "bfd.h"
12 #include <errno.h>
13 #include <sys/stat.h>
14 #include <sys/times.h>
15 #include <sys/time.h>
16
17 #define REG0(X) ((X) & 0x3)
18 #define REG1(X) (((X) & 0xc) >> 2)
19 #define REG0_4(X) (((X) & 0x30) >> 4)
20 #define REG0_8(X) (((X) & 0x300) >> 8)
21 #define REG1_8(X) (((X) & 0xc00) >> 10)
22 #define REG0_16(X) (((X) & 0x30000) >> 16)
23 #define REG1_16(X) (((X) & 0xc0000) >> 18)
24 \f
25 /* mov imm8, dn */
26 void OP_8000 (insn, extension)
27 unsigned long insn, extension;
28 {
29 State.regs[REG_D0 + REG0_8 (insn)] = SEXT8 (insn & 0xff);
30 }
31
32 /* mov dm, dn */
33 void OP_80 (insn, extension)
34 unsigned long insn, extension;
35 {
36 State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_D0 + REG1 (insn)];
37 }
38
39 /* mov dm, an */
40 void OP_F1E0 (insn, extension)
41 unsigned long insn, extension;
42 {
43 State.regs[REG_A0 + REG0 (insn)] = State.regs[REG_D0 + REG1 (insn)];
44 }
45
46 /* mov am, dn */
47 void OP_F1D0 (insn, extension)
48 unsigned long insn, extension;
49 {
50 State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_A0 + REG1 (insn)];
51 }
52
53 /* mov imm8, an */
54 void OP_9000 (insn, extension)
55 unsigned long insn, extension;
56 {
57 State.regs[REG_A0 + REG0_8 (insn)] = insn & 0xff;
58 }
59
60 /* mov am, an */
61 void OP_90 (insn, extension)
62 unsigned long insn, extension;
63 {
64 State.regs[REG_A0 + REG0 (insn)] = State.regs[REG_A0 + REG1 (insn)];
65 }
66
67 /* mov sp, an */
68 void OP_3C (insn, extension)
69 unsigned long insn, extension;
70 {
71 State.regs[REG_A0 + REG0 (insn)] = State.regs[REG_SP];
72 }
73
74 /* mov am, sp */
75 void OP_F2F0 (insn, extension)
76 unsigned long insn, extension;
77 {
78 State.regs[REG_SP] = State.regs[REG_A0 + REG1 (insn)];
79 }
80
81 /* mov psw, dn */
82 void OP_F2E4 (insn, extension)
83 unsigned long insn, extension;
84 {
85 State.regs[REG_D0 + REG0 (insn)] = PSW;
86 }
87
88 /* mov dm, psw */
89 void OP_F2F3 (insn, extension)
90 unsigned long insn, extension;
91 {
92 PSW = State.regs[REG_D0 + REG1 (insn)];
93 }
94
95 /* mov mdr, dn */
96 void OP_F2E0 (insn, extension)
97 unsigned long insn, extension;
98 {
99 State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_MDR];
100 }
101
102 /* mov dm, mdr */
103 void OP_F2F2 (insn, extension)
104 unsigned long insn, extension;
105 {
106 State.regs[REG_MDR] = State.regs[REG_D0 + REG1 (insn)];
107 }
108
109 /* mov (am), dn */
110 void OP_70 (insn, extension)
111 unsigned long insn, extension;
112 {
113 State.regs[REG_D0 + REG1 (insn)]
114 = load_word (State.regs[REG_A0 + REG0 (insn)]);
115 }
116
117 /* mov (d8,am), dn */
118 void OP_F80000 (insn, extension)
119 unsigned long insn, extension;
120 {
121 State.regs[REG_D0 + REG1_8 (insn)]
122 = load_word ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff)));
123 }
124
125 /* mov (d16,am), dn */
126 void OP_FA000000 (insn, extension)
127 unsigned long insn, extension;
128 {
129 State.regs[REG_D0 + REG1_16 (insn)]
130 = load_word ((State.regs[REG_A0 + REG0_16 (insn)]
131 + SEXT16 (insn & 0xffff)));
132 }
133
134 /* mov (d32,am), dn */
135 void OP_FC000000 (insn, extension)
136 unsigned long insn, extension;
137 {
138 State.regs[REG_D0 + REG1_16 (insn)]
139 = load_word ((State.regs[REG_A0 + REG0_16 (insn)]
140 + ((insn & 0xffff) << 16) + extension));
141 }
142
143 /* mov (d8,sp), dn */
144 void OP_5800 (insn, extension)
145 unsigned long insn, extension;
146 {
147 State.regs[REG_D0 + REG0_8 (insn)]
148 = load_word (State.regs[REG_SP] + (insn & 0xff));
149 }
150
151 /* mov (d16,sp), dn */
152 void OP_FAB40000 (insn, extension)
153 unsigned long insn, extension;
154 {
155 State.regs[REG_D0 + REG0_16 (insn)]
156 = load_word (State.regs[REG_SP] + (insn & 0xffff));
157 }
158
159 /* mov (d32,sp), dn */
160 void OP_FCB40000 (insn, extension)
161 unsigned long insn, extension;
162 {
163 State.regs[REG_D0 + REG0_16 (insn)]
164 = load_word (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension));
165 }
166
167 /* mov (di,am), dn */
168 void OP_F300 (insn, extension)
169 unsigned long insn, extension;
170 {
171 State.regs[REG_D0 + REG0_4 (insn)]
172 = load_word ((State.regs[REG_A0 + REG0 (insn)]
173 + State.regs[REG_D0 + REG1 (insn)]));
174 }
175
176 /* mov (abs16), dn */
177 void OP_300000 (insn, extension)
178 unsigned long insn, extension;
179 {
180 State.regs[REG_D0 + REG0_16 (insn)] = load_word ((insn & 0xffff));
181 }
182
183 /* mov (abs32), dn */
184 void OP_FCA40000 (insn, extension)
185 unsigned long insn, extension;
186 {
187 State.regs[REG_D0 + REG0_16 (insn)]
188 = load_word ((((insn & 0xffff) << 16) + extension));
189 }
190
191 /* mov (am), an */
192 void OP_F000 (insn, extension)
193 unsigned long insn, extension;
194 {
195 State.regs[REG_A0 + REG1 (insn)]
196 = load_word (State.regs[REG_A0 + REG0 (insn)]);
197 }
198
199 /* mov (d8,am), an */
200 void OP_F82000 (insn, extension)
201 unsigned long insn, extension;
202 {
203 State.regs[REG_A0 + REG1_8 (insn)]
204 = load_word ((State.regs[REG_A0 + REG0_8 (insn)]
205 + SEXT8 (insn & 0xff)));
206 }
207
208 /* mov (d16,am), an */
209 void OP_FA200000 (insn, extension)
210 unsigned long insn, extension;
211 {
212 State.regs[REG_A0 + REG1_16 (insn)]
213 = load_word ((State.regs[REG_A0 + REG0_16 (insn)]
214 + SEXT16 (insn & 0xffff)));
215 }
216
217 /* mov (d32,am), an */
218 void OP_FC200000 (insn, extension)
219 unsigned long insn, extension;
220 {
221 State.regs[REG_A0 + REG1_16 (insn)]
222 = load_word ((State.regs[REG_A0 + REG0_16 (insn)]
223 + ((insn & 0xffff) << 16) + extension));
224 }
225
226 /* mov (d8,sp), an */
227 void OP_5C00 (insn, extension)
228 unsigned long insn, extension;
229 {
230 State.regs[REG_A0 + REG0_8 (insn)]
231 = load_word (State.regs[REG_SP] + (insn & 0xff));
232 }
233
234 /* mov (d16,sp), an */
235 void OP_FAB00000 (insn, extension)
236 unsigned long insn, extension;
237 {
238 State.regs[REG_A0 + REG0_16 (insn)]
239 = load_word (State.regs[REG_SP] + (insn & 0xffff));
240 }
241
242 /* mov (d32,sp), an */
243 void OP_FCB00000 (insn, extension)
244 unsigned long insn, extension;
245 {
246 State.regs[REG_A0 + REG0_16 (insn)]
247 = load_word (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension));
248 }
249
250 /* mov (di,am), an */
251 void OP_F380 (insn, extension)
252 unsigned long insn, extension;
253 {
254 State.regs[REG_A0 + REG0_4 (insn)]
255 = load_word ((State.regs[REG_A0 + REG0 (insn)]
256 + State.regs[REG_D0 + REG1 (insn)]));
257 }
258
259 /* mov (abs16), an */
260 void OP_FAA00000 (insn, extension)
261 unsigned long insn, extension;
262 {
263 State.regs[REG_A0 + REG0_16 (insn)] = load_word ((insn & 0xffff));
264 }
265
266 /* mov (abs32), an */
267 void OP_FCA00000 (insn, extension)
268 unsigned long insn, extension;
269 {
270 State.regs[REG_A0 + REG0_16 (insn)]
271 = load_word ((((insn & 0xffff) << 16) + extension));
272 }
273
274 /* mov (d8,am), sp */
275 void OP_F8F000 (insn, extension)
276 unsigned long insn, extension;
277 {
278 State.regs[REG_SP]
279 = load_word ((State.regs[REG_A0 + REG0_8 (insn)]
280 + SEXT8 (insn & 0xff)));
281 }
282
283 /* mov dm, (an) */
284 void OP_60 (insn, extension)
285 unsigned long insn, extension;
286 {
287 store_word (State.regs[REG_A0 + REG0 (insn)],
288 State.regs[REG_D0 + REG1 (insn)]);
289 }
290
291 /* mov dm, (d8,an) */
292 void OP_F81000 (insn, extension)
293 unsigned long insn, extension;
294 {
295 store_word ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff)),
296 State.regs[REG_D0 + REG1_8 (insn)]);
297 }
298
299 /* mov dm (d16,an) */
300 void OP_FA100000 (insn, extension)
301 unsigned long insn, extension;
302 {
303 store_word ((State.regs[REG_A0 + REG0_16 (insn)] + SEXT16 (insn & 0xffff)),
304 State.regs[REG_D0 + REG1_16 (insn)]);
305 }
306
307 /* mov dm (d32,an) */
308 void OP_FC100000 (insn, extension)
309 unsigned long insn, extension;
310 {
311 store_word ((State.regs[REG_A0 + REG0_16 (insn)]
312 + ((insn & 0xffff) << 16) + extension),
313 State.regs[REG_D0 + REG1_16 (insn)]);
314 }
315
316 /* mov dm, (d8,sp) */
317 void OP_4200 (insn, extension)
318 unsigned long insn, extension;
319 {
320 store_word (State.regs[REG_SP] + (insn & 0xff),
321 State.regs[REG_D0 + REG1_8 (insn)]);
322 }
323
324 /* mov dm, (d16,sp) */
325 void OP_FA910000 (insn, extension)
326 unsigned long insn, extension;
327 {
328 store_word (State.regs[REG_SP] + (insn & 0xffff),
329 State.regs[REG_D0 + REG1_16 (insn)]);
330 }
331
332 /* mov dm, (d32,sp) */
333 void OP_FC910000 (insn, extension)
334 unsigned long insn, extension;
335 {
336 store_word (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension),
337 State.regs[REG_D0 + REG1_16 (insn)]);
338 }
339
340 /* mov dm, (di,an) */
341 void OP_F340 (insn, extension)
342 unsigned long insn, extension;
343 {
344 store_word ((State.regs[REG_A0 + REG0 (insn)]
345 + State.regs[REG_D0 + REG1 (insn)]),
346 State.regs[REG_D0 + REG0_4 (insn)]);
347 }
348
349 /* mov dm, (abs16) */
350 void OP_10000 (insn, extension)
351 unsigned long insn, extension;
352 {
353 store_word ((insn & 0xffff), State.regs[REG_D0 + REG1_16 (insn)]);
354 }
355
356 /* mov dm, (abs32) */
357 void OP_FC810000 (insn, extension)
358 unsigned long insn, extension;
359 {
360 store_word ((((insn & 0xffff) << 16) + extension),
361 State.regs[REG_D0 + REG1_16 (insn)]);
362 }
363
364 /* mov am, (an) */
365 void OP_F010 (insn, extension)
366 unsigned long insn, extension;
367 {
368 store_word (State.regs[REG_A0 + REG0 (insn)],
369 State.regs[REG_A0 + REG1 (insn)]);
370 }
371
372 /* mov am, (d8,an) */
373 void OP_F83000 (insn, extension)
374 unsigned long insn, extension;
375 {
376 store_word ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff)),
377 State.regs[REG_A0 + REG1_8 (insn)]);
378 }
379
380 /* mov am, (d16,an) */
381 void OP_FA300000 (insn, extension)
382 unsigned long insn, extension;
383 {
384 store_word ((State.regs[REG_A0 + REG0_16 (insn)] + SEXT16 (insn & 0xffff)),
385 State.regs[REG_A0 + REG1_16 (insn)]);
386 }
387
388 /* mov am, (d32,an) */
389 void OP_FC300000 (insn, extension)
390 unsigned long insn, extension;
391 {
392 store_word ((State.regs[REG_A0 + REG0_16 (insn)]
393 + ((insn & 0xffff) << 16) + extension),
394 State.regs[REG_A0 + REG1_16 (insn)]);
395 }
396
397 /* mov am, (d8,sp) */
398 void OP_4300 (insn, extension)
399 unsigned long insn, extension;
400 {
401 store_word (State.regs[REG_SP] + (insn & 0xff),
402 State.regs[REG_A0 + REG1_8 (insn)]);
403 }
404
405 /* mov am, (d16,sp) */
406 void OP_FA900000 (insn, extension)
407 unsigned long insn, extension;
408 {
409 store_word (State.regs[REG_SP] + (insn & 0xffff),
410 State.regs[REG_A0 + REG1_16 (insn)]);
411 }
412
413 /* mov am, (d32,sp) */
414 void OP_FC900000 (insn, extension)
415 unsigned long insn, extension;
416 {
417 store_word (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension),
418 State.regs[REG_A0 + REG1_16 (insn)]);
419 }
420
421 /* mov am, (di,an) */
422 void OP_F3C0 (insn, extension)
423 unsigned long insn, extension;
424 {
425 store_word ((State.regs[REG_A0 + REG0 (insn)]
426 + State.regs[REG_D0 + REG1 (insn)]),
427 State.regs[REG_A0 + REG0_4 (insn)]);
428 }
429
430 /* mov am, (abs16) */
431 void OP_FA800000 (insn, extension)
432 unsigned long insn, extension;
433 {
434 store_word ((insn & 0xffff), State.regs[REG_A0 + REG1_16 (insn)]);
435 }
436
437 /* mov am, (abs32) */
438 void OP_FC800000 (insn, extension)
439 unsigned long insn, extension;
440 {
441 store_word ((((insn & 0xffff) << 16) + extension), State.regs[REG_A0 + REG1_16 (insn)]);
442 }
443
444 /* mov sp, (d8,an) */
445 void OP_F8F400 (insn, extension)
446 unsigned long insn, extension;
447 {
448 store_word (State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff),
449 State.regs[REG_SP]);
450 }
451
452 /* mov imm16, dn */
453 void OP_2C0000 (insn, extension)
454 unsigned long insn, extension;
455 {
456 unsigned long value;
457
458 value = SEXT16 (insn & 0xffff);
459 State.regs[REG_D0 + REG0_16 (insn)] = value;
460 }
461
462 /* mov imm32,dn */
463 void OP_FCCC0000 (insn, extension)
464 unsigned long insn, extension;
465 {
466 unsigned long value;
467
468 value = ((insn & 0xffff) << 16) + extension;
469 State.regs[REG_D0 + REG0_16 (insn)] = value;
470 }
471
472 /* mov imm16, an */
473 void OP_240000 (insn, extension)
474 unsigned long insn, extension;
475 {
476 unsigned long value;
477
478 value = insn & 0xffff;
479 State.regs[REG_A0 + REG0_16 (insn)] = value;
480 }
481
482 /* mov imm32, an */
483 void OP_FCDC0000 (insn, extension)
484 unsigned long insn, extension;
485 {
486 unsigned long value;
487
488 value = ((insn & 0xffff) << 16) + extension;
489 State.regs[REG_A0 + REG0_16 (insn)] = value;
490 }
491
492 /* movbu (am), dn */
493 void OP_F040 (insn, extension)
494 unsigned long insn, extension;
495 {
496 State.regs[REG_D0 + REG1 (insn)]
497 = load_byte (State.regs[REG_A0 + REG0 (insn)]);
498 }
499
500 /* movbu (d8,am), dn */
501 void OP_F84000 (insn, extension)
502 unsigned long insn, extension;
503 {
504 State.regs[REG_D0 + REG1_8 (insn)]
505 = load_byte ((State.regs[REG_A0 + REG0_8 (insn)]
506 + SEXT8 (insn & 0xff)));
507 }
508
509 /* movbu (d16,am), dn */
510 void OP_FA400000 (insn, extension)
511 unsigned long insn, extension;
512 {
513 State.regs[REG_D0 + REG1_16 (insn)]
514 = load_byte ((State.regs[REG_A0 + REG0_16 (insn)]
515 + SEXT16 (insn & 0xffff)));
516 }
517
518 /* movbu (d32,am), dn */
519 void OP_FC400000 (insn, extension)
520 unsigned long insn, extension;
521 {
522 State.regs[REG_D0 + REG1_16 (insn)]
523 = load_byte ((State.regs[REG_A0 + REG0_16 (insn)]
524 + ((insn & 0xffff) << 16) + extension));
525 }
526
527 /* movbu (d8,sp), dn */
528 void OP_F8B800 (insn, extension)
529 unsigned long insn, extension;
530 {
531 State.regs[REG_D0 + REG0_8 (insn)]
532 = load_byte ((State.regs[REG_SP] + (insn & 0xff)));
533 }
534
535 /* movbu (d16,sp), dn */
536 void OP_FAB80000 (insn, extension)
537 unsigned long insn, extension;
538 {
539 State.regs[REG_D0 + REG0_16 (insn)]
540 = load_byte ((State.regs[REG_SP] + (insn & 0xffff)));
541 }
542
543 /* movbu (d32,sp), dn */
544 void OP_FCB80000 (insn, extension)
545 unsigned long insn, extension;
546 {
547 State.regs[REG_D0 + REG0_16 (insn)]
548 = load_byte (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension));
549 }
550
551 /* movbu (di,am), dn */
552 void OP_F400 (insn, extension)
553 unsigned long insn, extension;
554 {
555 State.regs[REG_D0 + REG0_4 (insn)]
556 = load_byte ((State.regs[REG_A0 + REG0 (insn)]
557 + State.regs[REG_D0 + REG1 (insn)]));
558 }
559
560 /* movbu (abs16), dn */
561 void OP_340000 (insn, extension)
562 unsigned long insn, extension;
563 {
564 State.regs[REG_D0 + REG0_16 (insn)] = load_byte ((insn & 0xffff));
565 }
566
567 /* movbu (abs32), dn */
568 void OP_FCA80000 (insn, extension)
569 unsigned long insn, extension;
570 {
571 State.regs[REG_D0 + REG0_16 (insn)]
572 = load_byte ((((insn & 0xffff) << 16) + extension));
573 }
574
575 /* movbu dm, (an) */
576 void OP_F050 (insn, extension)
577 unsigned long insn, extension;
578 {
579 store_byte (State.regs[REG_A0 + REG0 (insn)],
580 State.regs[REG_D0 + REG1 (insn)]);
581 }
582
583 /* movbu dm, (d8,an) */
584 void OP_F85000 (insn, extension)
585 unsigned long insn, extension;
586 {
587 store_byte ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff)),
588 State.regs[REG_D0 + REG1_8 (insn)]);
589 }
590
591 /* movbu dm, (d16,an) */
592 void OP_FA500000 (insn, extension)
593 unsigned long insn, extension;
594 {
595 store_byte ((State.regs[REG_A0 + REG0_16 (insn)] + SEXT16 (insn & 0xffff)),
596 State.regs[REG_D0 + REG1_16 (insn)]);
597 }
598
599 /* movbu dm, (d32,an) */
600 void OP_FC500000 (insn, extension)
601 unsigned long insn, extension;
602 {
603 store_byte ((State.regs[REG_A0 + REG0_16 (insn)]
604 + ((insn & 0xffff) << 16) + extension),
605 State.regs[REG_D0 + REG1_16 (insn)]);
606 }
607
608 /* movbu dm, (d8,sp) */
609 void OP_F89200 (insn, extension)
610 unsigned long insn, extension;
611 {
612 store_byte (State.regs[REG_SP] + (insn & 0xff),
613 State.regs[REG_D0 + REG1_8 (insn)]);
614 }
615
616 /* movbu dm, (d16,sp) */
617 void OP_FA920000 (insn, extension)
618 unsigned long insn, extension;
619 {
620 store_byte (State.regs[REG_SP] + (insn & 0xffff),
621 State.regs[REG_D0 + REG1_16 (insn)]);
622 }
623
624 /* movbu dm (d32,sp) */
625 void OP_FC920000 (insn, extension)
626 unsigned long insn, extension;
627 {
628 store_byte (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension),
629 State.regs[REG_D0 + REG1_16 (insn)]);
630 }
631
632 /* movbu dm, (di,an) */
633 void OP_F440 (insn, extension)
634 unsigned long insn, extension;
635 {
636 store_byte ((State.regs[REG_A0 + REG0 (insn)]
637 + State.regs[REG_D0 + REG1 (insn)]),
638 State.regs[REG_D0 + REG0_4 (insn)]);
639 }
640
641 /* movbu dm, (abs16) */
642 void OP_20000 (insn, extension)
643 unsigned long insn, extension;
644 {
645 store_byte ((insn & 0xffff), State.regs[REG_D0 + REG1_16 (insn)]);
646 }
647
648 /* movbu dm, (abs32) */
649 void OP_FC820000 (insn, extension)
650 unsigned long insn, extension;
651 {
652 store_byte ((((insn & 0xffff) << 16) + extension), State.regs[REG_D0 + REG1_16 (insn)]);
653 }
654
655 /* movhu (am), dn */
656 void OP_F060 (insn, extension)
657 unsigned long insn, extension;
658 {
659 State.regs[REG_D0 + REG1 (insn)]
660 = load_half (State.regs[REG_A0 + REG0 (insn)]);
661 }
662
663 /* movhu (d8,am), dn */
664 void OP_F86000 (insn, extension)
665 unsigned long insn, extension;
666 {
667 State.regs[REG_D0 + REG1_8 (insn)]
668 = load_half ((State.regs[REG_A0 + REG0_8 (insn)]
669 + SEXT8 (insn & 0xff)));
670 }
671
672 /* movhu (d16,am), dn */
673 void OP_FA600000 (insn, extension)
674 unsigned long insn, extension;
675 {
676 State.regs[REG_D0 + REG1_16 (insn)]
677 = load_half ((State.regs[REG_A0 + REG0_16 (insn)]
678 + SEXT16 (insn & 0xffff)));
679 }
680
681 /* movhu (d32,am), dn */
682 void OP_FC600000 (insn, extension)
683 unsigned long insn, extension;
684 {
685 State.regs[REG_D0 + REG1_16 (insn)]
686 = load_half ((State.regs[REG_A0 + REG0_16 (insn)]
687 + ((insn & 0xffff) << 16) + extension));
688 }
689
690 /* movhu (d8,sp) dn */
691 void OP_F8BC00 (insn, extension)
692 unsigned long insn, extension;
693 {
694 State.regs[REG_D0 + REG0_8 (insn)]
695 = load_half ((State.regs[REG_SP] + (insn & 0xff)));
696 }
697
698 /* movhu (d16,sp), dn */
699 void OP_FABC0000 (insn, extension)
700 unsigned long insn, extension;
701 {
702 State.regs[REG_D0 + REG0_16 (insn)]
703 = load_half ((State.regs[REG_SP] + (insn & 0xffff)));
704 }
705
706 /* movhu (d32,sp), dn */
707 void OP_FCBC0000 (insn, extension)
708 unsigned long insn, extension;
709 {
710 State.regs[REG_D0 + REG0_16 (insn)]
711 = load_half (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension));
712 }
713
714 /* movhu (di,am), dn */
715 void OP_F480 (insn, extension)
716 unsigned long insn, extension;
717 {
718 State.regs[REG_D0 + REG0_4 (insn)]
719 = load_half ((State.regs[REG_A0 + REG0 (insn)]
720 + State.regs[REG_D0 + REG1 (insn)]));
721 }
722
723 /* movhu (abs16), dn */
724 void OP_380000 (insn, extension)
725 unsigned long insn, extension;
726 {
727 State.regs[REG_D0 + REG0_16 (insn)] = load_half ((insn & 0xffff));
728 }
729
730 /* movhu (abs32), dn */
731 void OP_FCAC0000 (insn, extension)
732 unsigned long insn, extension;
733 {
734 State.regs[REG_D0 + REG0_16 (insn)]
735 = load_half ((((insn & 0xffff) << 16) + extension));
736 }
737
738 /* movhu dm, (an) */
739 void OP_F070 (insn, extension)
740 unsigned long insn, extension;
741 {
742 store_half (State.regs[REG_A0 + REG0 (insn)],
743 State.regs[REG_D0 + REG1 (insn)]);
744 }
745
746 /* movhu dm, (d8,an) */
747 void OP_F87000 (insn, extension)
748 unsigned long insn, extension;
749 {
750 store_half ((State.regs[REG_A0 + REG0_8 (insn)] + SEXT8 (insn & 0xff)),
751 State.regs[REG_D0 + REG1_8 (insn)]);
752 }
753
754 /* movhu dm, (d16,an) */
755 void OP_FA700000 (insn, extension)
756 unsigned long insn, extension;
757 {
758 store_half ((State.regs[REG_A0 + REG0_16 (insn)] + SEXT16 (insn & 0xffff)),
759 State.regs[REG_D0 + REG1_16 (insn)]);
760 }
761
762 /* movhu dm, (d32,an) */
763 void OP_FC700000 (insn, extension)
764 unsigned long insn, extension;
765 {
766 store_half ((State.regs[REG_A0 + REG0_16 (insn)]
767 + ((insn & 0xffff) << 16) + extension),
768 State.regs[REG_D0 + REG1_16 (insn)]);
769 }
770
771 /* movhu dm,(d8,sp) */
772 void OP_F89300 (insn, extension)
773 unsigned long insn, extension;
774 {
775 store_half (State.regs[REG_SP] + (insn & 0xff),
776 State.regs[REG_D0 + REG1_8 (insn)]);
777 }
778
779 /* movhu dm,(d16,sp) */
780 void OP_FA930000 (insn, extension)
781 unsigned long insn, extension;
782 {
783 store_half (State.regs[REG_SP] + (insn & 0xffff),
784 State.regs[REG_D0 + REG1_16 (insn)]);
785 }
786
787 /* movhu dm,(d32,sp) */
788 void OP_FC930000 (insn, extension)
789 unsigned long insn, extension;
790 {
791 store_half (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension),
792 State.regs[REG_D0 + REG1_16 (insn)]);
793 }
794
795 /* movhu dm, (di,an) */
796 void OP_F4C0 (insn, extension)
797 unsigned long insn, extension;
798 {
799 store_half ((State.regs[REG_A0 + REG0 (insn)]
800 + State.regs[REG_D0 + REG1 (insn)]),
801 State.regs[REG_D0 + REG0_4 (insn)]);
802 }
803
804 /* movhu dm, (abs16) */
805 void OP_30000 (insn, extension)
806 unsigned long insn, extension;
807 {
808 store_half ((insn & 0xffff), State.regs[REG_D0 + REG1_16 (insn)]);
809 }
810
811 /* movhu dm, (abs32) */
812 void OP_FC830000 (insn, extension)
813 unsigned long insn, extension;
814 {
815 store_half ((((insn & 0xffff) << 16) + extension), State.regs[REG_D0 + REG1_16 (insn)]);
816 }
817
818 /* ext dn */
819 void OP_F2D0 (insn, extension)
820 unsigned long insn, extension;
821 {
822 if (State.regs[REG_D0 + REG0 (insn)] & 0x80000000)
823 State.regs[REG_MDR] = -1;
824 else
825 State.regs[REG_MDR] = 0;
826 }
827
828 /* extb dn */
829 void OP_10 (insn, extension)
830 unsigned long insn, extension;
831 {
832 State.regs[REG_D0 + REG0 (insn)] = SEXT8 (State.regs[REG_D0 + REG0 (insn)]);
833 }
834
835 /* extbu dn */
836 void OP_14 (insn, extension)
837 unsigned long insn, extension;
838 {
839 State.regs[REG_D0 + REG0 (insn)] &= 0xff;
840 }
841
842 /* exth dn */
843 void OP_18 (insn, extension)
844 unsigned long insn, extension;
845 {
846 State.regs[REG_D0 + REG0 (insn)]
847 = SEXT16 (State.regs[REG_D0 + REG0 (insn)]);
848 }
849
850 /* exthu dn */
851 void OP_1C (insn, extension)
852 unsigned long insn, extension;
853 {
854 State.regs[REG_D0 + REG0 (insn)] &= 0xffff;
855 }
856
857 /* movm (sp), reg_list */
858 void OP_CE00 (insn, extension)
859 unsigned long insn, extension;
860 {
861 unsigned long sp = State.regs[REG_SP];
862 unsigned long mask;
863
864 mask = insn & 0xff;
865
866 if (mask & 0x8)
867 {
868 sp += 4;
869 State.regs[REG_LAR] = load_word (sp);
870 sp += 4;
871 State.regs[REG_LIR] = load_word (sp);
872 sp += 4;
873 State.regs[REG_MDR] = load_word (sp);
874 sp += 4;
875 State.regs[REG_A0 + 1] = load_word (sp);
876 sp += 4;
877 State.regs[REG_A0] = load_word (sp);
878 sp += 4;
879 State.regs[REG_D0 + 1] = load_word (sp);
880 sp += 4;
881 State.regs[REG_D0] = load_word (sp);
882 sp += 4;
883 }
884
885 if (mask & 0x10)
886 {
887 State.regs[REG_A0 + 3] = load_word (sp);
888 sp += 4;
889 }
890
891 if (mask & 0x20)
892 {
893 State.regs[REG_A0 + 2] = load_word (sp);
894 sp += 4;
895 }
896
897 if (mask & 0x40)
898 {
899 State.regs[REG_D0 + 3] = load_word (sp);
900 sp += 4;
901 }
902
903 if (mask & 0x80)
904 {
905 State.regs[REG_D0 + 2] = load_word (sp);
906 sp += 4;
907 }
908
909 /* And make sure to update the stack pointer. */
910 State.regs[REG_SP] = sp;
911 }
912
913 /* movm reg_list, (sp) */
914 void OP_CF00 (insn, extension)
915 unsigned long insn, extension;
916 {
917 unsigned long sp = State.regs[REG_SP];
918 unsigned long mask;
919
920 mask = insn & 0xff;
921
922 if (mask & 0x80)
923 {
924 sp -= 4;
925 store_word (sp, State.regs[REG_D0 + 2]);
926 }
927
928 if (mask & 0x40)
929 {
930 sp -= 4;
931 store_word (sp, State.regs[REG_D0 + 3]);
932 }
933
934 if (mask & 0x20)
935 {
936 sp -= 4;
937 store_word (sp, State.regs[REG_A0 + 2]);
938 }
939
940 if (mask & 0x10)
941 {
942 sp -= 4;
943 store_word (sp, State.regs[REG_A0 + 3]);
944 }
945
946 if (mask & 0x8)
947 {
948 sp -= 4;
949 store_word (sp, State.regs[REG_D0]);
950 sp -= 4;
951 store_word (sp, State.regs[REG_D0 + 1]);
952 sp -= 4;
953 store_word (sp, State.regs[REG_A0]);
954 sp -= 4;
955 store_word (sp, State.regs[REG_A0 + 1]);
956 sp -= 4;
957 store_word (sp, State.regs[REG_MDR]);
958 sp -= 4;
959 store_word (sp, State.regs[REG_LIR]);
960 sp -= 4;
961 store_word (sp, State.regs[REG_LAR]);
962 sp -= 4;
963 }
964
965 /* And make sure to update the stack pointer. */
966 State.regs[REG_SP] = sp;
967 }
968
969 /* clr dn */
970 void OP_0 (insn, extension)
971 unsigned long insn, extension;
972 {
973 State.regs[REG_D0 + REG1 (insn)] = 0;
974
975 PSW |= PSW_Z;
976 PSW &= ~(PSW_V | PSW_C | PSW_N);
977 }
978
979 /* add dm,dn */
980 void OP_E0 (insn, extension)
981 unsigned long insn, extension;
982 {
983 int z, c, n, v;
984 unsigned long reg1, reg2, value;
985
986 reg1 = State.regs[REG_D0 + REG1 (insn)];
987 reg2 = State.regs[REG_D0 + REG0 (insn)];
988 value = reg1 + reg2;
989 State.regs[REG_D0 + REG0 (insn)] = value;
990
991 z = (value == 0);
992 n = (value & 0x80000000);
993 c = (value < reg1) || (value < reg2);
994 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
995 && (reg2 & 0x80000000) != (value & 0x80000000));
996
997 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
998 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
999 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1000 }
1001
1002 /* add dm, an */
1003 void OP_F160 (insn, extension)
1004 unsigned long insn, extension;
1005 {
1006 int z, c, n, v;
1007 unsigned long reg1, reg2, value;
1008
1009 reg1 = State.regs[REG_D0 + REG1 (insn)];
1010 reg2 = State.regs[REG_A0 + REG0 (insn)];
1011 value = reg1 + reg2;
1012 State.regs[REG_A0 + REG0 (insn)] = value;
1013
1014 z = (value == 0);
1015 n = (value & 0x80000000);
1016 c = (value < reg1) || (value < reg2);
1017 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
1018 && (reg2 & 0x80000000) != (value & 0x80000000));
1019
1020 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1021 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1022 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1023 }
1024
1025 /* add am, dn */
1026 void OP_F150 (insn, extension)
1027 unsigned long insn, extension;
1028 {
1029 int z, c, n, v;
1030 unsigned long reg1, reg2, value;
1031
1032 reg1 = State.regs[REG_A0 + REG1 (insn)];
1033 reg2 = State.regs[REG_D0 + REG0 (insn)];
1034 value = reg1 + reg2;
1035 State.regs[REG_D0 + REG0 (insn)] = value;
1036
1037 z = (value == 0);
1038 n = (value & 0x80000000);
1039 c = (value < reg1) || (value < reg2);
1040 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
1041 && (reg2 & 0x80000000) != (value & 0x80000000));
1042
1043 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1044 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1045 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1046 }
1047
1048 /* add am,an */
1049 void OP_F170 (insn, extension)
1050 unsigned long insn, extension;
1051 {
1052 int z, c, n, v;
1053 unsigned long reg1, reg2, value;
1054
1055 reg1 = State.regs[REG_A0 + REG1 (insn)];
1056 reg2 = State.regs[REG_A0 + REG0 (insn)];
1057 value = reg1 + reg2;
1058 State.regs[REG_A0 + REG0 (insn)] = value;
1059
1060 z = (value == 0);
1061 n = (value & 0x80000000);
1062 c = (value < reg1) || (value < reg2);
1063 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
1064 && (reg2 & 0x80000000) != (value & 0x80000000));
1065
1066 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1067 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1068 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1069 }
1070
1071 /* add imm8, dn */
1072 void OP_2800 (insn, extension)
1073 unsigned long insn, extension;
1074 {
1075 int z, c, n, v;
1076 unsigned long reg1, imm, value;
1077
1078 reg1 = State.regs[REG_D0 + REG0_8 (insn)];
1079 imm = SEXT8 (insn & 0xff);
1080 value = reg1 + imm;
1081 State.regs[REG_D0 + REG0_8 (insn)] = value;
1082
1083 z = (value == 0);
1084 n = (value & 0x80000000);
1085 c = (value < reg1) || (value < imm);
1086 v = ((reg1 & 0x80000000) == (imm & 0x80000000)
1087 && (reg1 & 0x80000000) != (value & 0x80000000));
1088
1089 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1090 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1091 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1092 }
1093
1094 /* add imm16, dn */
1095 void OP_FAC00000 (insn, extension)
1096 unsigned long insn, extension;
1097 {
1098 int z, c, n, v;
1099 unsigned long reg1, imm, value;
1100
1101 reg1 = State.regs[REG_D0 + REG0_16 (insn)];
1102 imm = SEXT16 (insn & 0xffff);
1103 value = reg1 + imm;
1104 State.regs[REG_D0 + REG0_16 (insn)] = value;
1105
1106 z = (value == 0);
1107 n = (value & 0x80000000);
1108 c = (value < reg1) || (value < imm);
1109 v = ((reg1 & 0x80000000) == (imm & 0x80000000)
1110 && (reg1 & 0x80000000) != (value & 0x80000000));
1111
1112 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1113 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1114 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1115 }
1116
1117 /* add imm32,dn */
1118 void OP_FCC00000 (insn, extension)
1119 unsigned long insn, extension;
1120 {
1121 int z, c, n, v;
1122 unsigned long reg1, imm, value;
1123
1124 reg1 = State.regs[REG_D0 + REG0_16 (insn)];
1125 imm = ((insn & 0xffff) << 16) + extension;
1126 value = reg1 + imm;
1127 State.regs[REG_D0 + REG0_16 (insn)] = value;
1128
1129 z = (value == 0);
1130 n = (value & 0x80000000);
1131 c = (value < reg1) || (value < imm);
1132 v = ((reg1 & 0x80000000) == (imm & 0x80000000)
1133 && (reg1 & 0x80000000) != (value & 0x80000000));
1134
1135 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1136 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1137 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1138 }
1139
1140 /* add imm8, an */
1141 void OP_2000 (insn, extension)
1142 unsigned long insn, extension;
1143 {
1144 int z, c, n, v;
1145 unsigned long reg1, imm, value;
1146
1147 reg1 = State.regs[REG_A0 + REG0_8 (insn)];
1148 imm = SEXT8 (insn & 0xff);
1149 value = reg1 + imm;
1150 State.regs[REG_A0 + REG0_8 (insn)] = value;
1151
1152 z = (value == 0);
1153 n = (value & 0x80000000);
1154 c = (value < reg1) || (value < imm);
1155 v = ((reg1 & 0x80000000) == (imm & 0x80000000)
1156 && (reg1 & 0x80000000) != (value & 0x80000000));
1157
1158 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1159 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1160 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1161 }
1162
1163 /* add imm16, an */
1164 void OP_FAD00000 (insn, extension)
1165 unsigned long insn, extension;
1166 {
1167 int z, c, n, v;
1168 unsigned long reg1, imm, value;
1169
1170 reg1 = State.regs[REG_A0 + REG0_16 (insn)];
1171 imm = SEXT16 (insn & 0xffff);
1172 value = reg1 + imm;
1173 State.regs[REG_A0 + REG0_16 (insn)] = value;
1174
1175 z = (value == 0);
1176 n = (value & 0x80000000);
1177 c = (value < reg1) || (value < imm);
1178 v = ((reg1 & 0x80000000) == (imm & 0x80000000)
1179 && (reg1 & 0x80000000) != (value & 0x80000000));
1180
1181 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1182 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1183 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1184 }
1185
1186 /* add imm32, an */
1187 void OP_FCD00000 (insn, extension)
1188 unsigned long insn, extension;
1189 {
1190 int z, c, n, v;
1191 unsigned long reg1, imm, value;
1192
1193 reg1 = State.regs[REG_A0 + REG0_16 (insn)];
1194 imm = ((insn & 0xffff) << 16) + extension;
1195 value = reg1 + imm;
1196 State.regs[REG_A0 + REG0_16 (insn)] = value;
1197
1198 z = (value == 0);
1199 n = (value & 0x80000000);
1200 c = (value < reg1) || (value < imm);
1201 v = ((reg1 & 0x80000000) == (imm & 0x80000000)
1202 && (reg1 & 0x80000000) != (value & 0x80000000));
1203
1204 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1205 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1206 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1207 }
1208
1209 /* add imm8, sp */
1210 void OP_F8FE00 (insn, extension)
1211 unsigned long insn, extension;
1212 {
1213 unsigned long reg1, imm, value;
1214
1215 reg1 = State.regs[REG_SP];
1216 imm = SEXT8 (insn & 0xff);
1217 value = reg1 + imm;
1218 State.regs[REG_SP] = value;
1219 }
1220
1221 /* add imm16,sp */
1222 void OP_FAFE0000 (insn, extension)
1223 unsigned long insn, extension;
1224 {
1225 unsigned long reg1, imm, value;
1226
1227 reg1 = State.regs[REG_SP];
1228 imm = SEXT16 (insn & 0xffff);
1229 value = reg1 + imm;
1230 State.regs[REG_SP] = value;
1231 }
1232
1233 /* add imm32, sp */
1234 void OP_FCFE0000 (insn, extension)
1235 unsigned long insn, extension;
1236 {
1237 unsigned long reg1, imm, value;
1238
1239 reg1 = State.regs[REG_SP];
1240 imm = ((insn & 0xffff) << 16) + extension;
1241 value = reg1 + imm;
1242 State.regs[REG_SP] = value;
1243 }
1244
1245 /* addc dm,dn */
1246 void OP_F140 (insn, extension)
1247 unsigned long insn, extension;
1248 {
1249 int z, c, n, v;
1250 unsigned long reg1, reg2, value;
1251
1252 reg1 = State.regs[REG_D0 + REG1 (insn)];
1253 reg2 = State.regs[REG_D0 + REG0 (insn)];
1254 value = reg1 + reg2 + ((PSW & PSW_C) != 0);
1255 State.regs[REG_D0 + REG0 (insn)] = value;
1256
1257 z = (value == 0);
1258 n = (value & 0x80000000);
1259 c = (value < reg1) || (value < reg2);
1260 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
1261 && (reg2 & 0x80000000) != (value & 0x80000000));
1262
1263 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1264 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1265 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1266 }
1267
1268 /* sub dm, dn */
1269 void OP_F100 (insn, extension)
1270 unsigned long insn, extension;
1271 {
1272 int z, c, n, v;
1273 unsigned long reg1, reg2, value;
1274
1275 reg1 = State.regs[REG_D0 + REG1 (insn)];
1276 reg2 = State.regs[REG_D0 + REG0 (insn)];
1277 value = reg2 - reg1;
1278 State.regs[REG_D0 + REG0 (insn)] = value;
1279
1280 z = (value == 0);
1281 n = (value & 0x80000000);
1282 c = (reg1 > reg2);
1283 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1284 && (reg2 & 0x80000000) != (value & 0x80000000));
1285
1286 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1287 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1288 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1289 }
1290
1291 /* sub dm, an */
1292 void OP_F120 (insn, extension)
1293 unsigned long insn, extension;
1294 {
1295 int z, c, n, v;
1296 unsigned long reg1, reg2, value;
1297
1298 reg1 = State.regs[REG_D0 + REG1 (insn)];
1299 reg2 = State.regs[REG_A0 + REG0 (insn)];
1300 value = reg2 - reg1;
1301 State.regs[REG_A0 + REG0 (insn)] = value;
1302
1303 z = (value == 0);
1304 n = (value & 0x80000000);
1305 c = (reg1 > reg2);
1306 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1307 && (reg2 & 0x80000000) != (value & 0x80000000));
1308
1309 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1310 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1311 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1312 }
1313
1314 /* sub am, dn */
1315 void OP_F110 (insn, extension)
1316 unsigned long insn, extension;
1317 {
1318 int z, c, n, v;
1319 unsigned long reg1, reg2, value;
1320
1321 reg1 = State.regs[REG_A0 + REG1 (insn)];
1322 reg2 = State.regs[REG_D0 + REG0 (insn)];
1323 value = reg2 - reg1;
1324 State.regs[REG_D0 + REG0 (insn)] = value;
1325
1326 z = (value == 0);
1327 n = (value & 0x80000000);
1328 c = (reg1 > reg2);
1329 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1330 && (reg2 & 0x80000000) != (value & 0x80000000));
1331
1332 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1333 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1334 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1335 }
1336
1337 /* sub am, an */
1338 void OP_F130 (insn, extension)
1339 unsigned long insn, extension;
1340 {
1341 int z, c, n, v;
1342 unsigned long reg1, reg2, value;
1343
1344 reg1 = State.regs[REG_A0 + REG1 (insn)];
1345 reg2 = State.regs[REG_A0 + REG0 (insn)];
1346 value = reg2 - reg1;
1347 State.regs[REG_A0 + REG0 (insn)] = value;
1348
1349 z = (value == 0);
1350 n = (value & 0x80000000);
1351 c = (reg1 > reg2);
1352 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1353 && (reg2 & 0x80000000) != (value & 0x80000000));
1354
1355 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1356 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1357 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1358 }
1359
1360 /* sub imm32, dn */
1361 void OP_FCC40000 (insn, extension)
1362 unsigned long insn, extension;
1363 {
1364 int z, c, n, v;
1365 unsigned long reg1, imm, value;
1366
1367 reg1 = State.regs[REG_D0 + REG0_16 (insn)];
1368 imm = ((insn & 0xffff) << 16) + extension;
1369 value = reg1 - imm;
1370 State.regs[REG_D0 + REG0_16 (insn)] = value;
1371
1372 z = (value == 0);
1373 n = (value & 0x80000000);
1374 c = (reg1 < imm);
1375 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1376 && (reg1 & 0x80000000) != (value & 0x80000000));
1377
1378 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1379 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1380 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1381 }
1382
1383 /* sub imm32, an */
1384 void OP_FCD40000 (insn, extension)
1385 unsigned long insn, extension;
1386 {
1387 int z, c, n, v;
1388 unsigned long reg1, imm, value;
1389
1390 reg1 = State.regs[REG_A0 + REG0_16 (insn)];
1391 imm = ((insn & 0xffff) << 16) + extension;
1392 value = reg1 - imm;
1393 State.regs[REG_A0 + REG0_16 (insn)] = value;
1394
1395 z = (value == 0);
1396 n = (value & 0x80000000);
1397 c = (reg1 < imm);
1398 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1399 && (reg1 & 0x80000000) != (value & 0x80000000));
1400
1401 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1402 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1403 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1404 }
1405
1406 /* subc dm, dn */
1407 void OP_F180 (insn, extension)
1408 unsigned long insn, extension;
1409 {
1410 int z, c, n, v;
1411 unsigned long reg1, reg2, value;
1412
1413 reg1 = State.regs[REG_D0 + REG1 (insn)];
1414 reg2 = State.regs[REG_D0 + REG0 (insn)];
1415 value = reg2 - reg1 - ((PSW & PSW_C) != 0);
1416 State.regs[REG_D0 + REG0 (insn)] = value;
1417
1418 z = (value == 0);
1419 n = (value & 0x80000000);
1420 c = (reg1 > reg2);
1421 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1422 && (reg2 & 0x80000000) != (value & 0x80000000));
1423
1424 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1425 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1426 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1427 }
1428
1429 /* mul dm, dn */
1430 void OP_F240 (insn, extension)
1431 unsigned long insn, extension;
1432 {
1433 unsigned long long temp;
1434 int n, z;
1435
1436 temp = ((signed64)(signed32)State.regs[REG_D0 + REG0 (insn)]
1437 * (signed64)(signed32)State.regs[REG_D0 + REG1 (insn)]);
1438 State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff;
1439 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
1440 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1441 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
1442 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1443 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1444 }
1445
1446 /* mulu dm, dn */
1447 void OP_F250 (insn, extension)
1448 unsigned long insn, extension;
1449 {
1450 unsigned long long temp;
1451 int n, z;
1452
1453 temp = ((unsigned64)State.regs[REG_D0 + REG0 (insn)]
1454 * (unsigned64)State.regs[REG_D0 + REG1 (insn)]);
1455 State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff;
1456 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1457 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1458 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
1459 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1460 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1461 }
1462
1463 /* div dm, dn */
1464 void OP_F260 (insn, extension)
1465 unsigned long insn, extension;
1466 {
1467 long long temp;
1468 int n, z;
1469
1470 temp = State.regs[REG_MDR];
1471 temp <<= 32;
1472 temp |= State.regs[REG_D0 + REG0 (insn)];
1473 State.regs[REG_MDR] = temp % (long)State.regs[REG_D0 + REG1 (insn)];
1474 temp /= (long)State.regs[REG_D0 + REG1 (insn)];
1475 State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff;
1476 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1477 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
1478 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1479 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1480 }
1481
1482 /* divu dm, dn */
1483 void OP_F270 (insn, extension)
1484 unsigned long insn, extension;
1485 {
1486 unsigned long long temp;
1487 int n, z;
1488
1489 temp = State.regs[REG_MDR];
1490 temp <<= 32;
1491 temp |= State.regs[REG_D0 + REG0 (insn)];
1492 State.regs[REG_MDR] = temp % State.regs[REG_D0 + REG1 (insn)];
1493 temp /= State.regs[REG_D0 + REG1 (insn)];
1494 State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff;
1495 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1496 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
1497 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1498 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1499 }
1500
1501 /* inc dn */
1502 void OP_40 (insn, extension)
1503 unsigned long insn, extension;
1504 {
1505 int z,n,c,v;
1506 unsigned int value, imm, reg1;
1507
1508 reg1 = State.regs[REG_D0 + REG1 (insn)];
1509 imm = 1;
1510 value = reg1 + imm;
1511 State.regs[REG_D0 + REG1 (insn)] = value;
1512
1513 z = (value == 0);
1514 n = (value & 0x80000000);
1515 c = (value < imm);
1516 v = ((reg1 & 0x80000000) == (imm & 0x80000000)
1517 && (reg1 & 0x80000000) != (value & 0x80000000));
1518
1519 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1520 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1521 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1522 }
1523
1524 /* inc an */
1525 void OP_41 (insn, extension)
1526 unsigned long insn, extension;
1527 {
1528 State.regs[REG_A0 + REG1 (insn)] += 1;
1529 }
1530
1531 /* inc4 an */
1532 void OP_50 (insn, extension)
1533 unsigned long insn, extension;
1534 {
1535 State.regs[REG_A0 + REG0 (insn)] += 4;
1536 }
1537
1538 /* cmp imm8, dn */
1539 void OP_A000 (insn, extension)
1540 unsigned long insn, extension;
1541 {
1542 int z, c, n, v;
1543 unsigned long reg1, imm, value;
1544
1545 reg1 = State.regs[REG_D0 + REG0_8 (insn)];
1546 imm = SEXT8 (insn & 0xff);
1547 value = reg1 - imm;
1548
1549 z = (value == 0);
1550 n = (value & 0x80000000);
1551 c = (reg1 < imm);
1552 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1553 && (reg1 & 0x80000000) != (value & 0x80000000));
1554
1555 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1556 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1557 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1558 }
1559
1560 /* cmp dm, dn */
1561 void OP_A0 (insn, extension)
1562 unsigned long insn, extension;
1563 {
1564 int z, c, n, v;
1565 unsigned long reg1, reg2, value;
1566
1567 reg1 = State.regs[REG_D0 + REG1 (insn)];
1568 reg2 = State.regs[REG_D0 + REG0 (insn)];
1569 value = reg2 - reg1;
1570
1571 z = (value == 0);
1572 n = (value & 0x80000000);
1573 c = (reg1 > reg2);
1574 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1575 && (reg2 & 0x80000000) != (value & 0x80000000));
1576
1577 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1578 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1579 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1580 }
1581
1582 /* cmp dm, an */
1583 void OP_F1A0 (insn, extension)
1584 unsigned long insn, extension;
1585 {
1586 int z, c, n, v;
1587 unsigned long reg1, reg2, value;
1588
1589 reg1 = State.regs[REG_D0 + REG1 (insn)];
1590 reg2 = State.regs[REG_A0 + REG0 (insn)];
1591 value = reg2 - reg1;
1592
1593 z = (value == 0);
1594 n = (value & 0x80000000);
1595 c = (reg1 > reg2);
1596 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1597 && (reg2 & 0x80000000) != (value & 0x80000000));
1598
1599 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1600 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1601 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1602 }
1603
1604 /* cmp am, dn */
1605 void OP_F190 (insn, extension)
1606 unsigned long insn, extension;
1607 {
1608 int z, c, n, v;
1609 unsigned long reg1, reg2, value;
1610
1611 reg1 = State.regs[REG_A0 + REG1 (insn)];
1612 reg2 = State.regs[REG_D0 + REG0 (insn)];
1613 value = reg2 - reg1;
1614
1615 z = (value == 0);
1616 n = (value & 0x80000000);
1617 c = (reg1 > reg2);
1618 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1619 && (reg2 & 0x80000000) != (value & 0x80000000));
1620
1621 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1622 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1623 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1624 }
1625
1626 /* cmp imm8, an */
1627 void OP_B000 (insn, extension)
1628 unsigned long insn, extension;
1629 {
1630 int z, c, n, v;
1631 unsigned long reg1, imm, value;
1632
1633 reg1 = State.regs[REG_A0 + REG0_8 (insn)];
1634 imm = insn & 0xff;
1635 value = reg1 - imm;
1636
1637 z = (value == 0);
1638 n = (value & 0x80000000);
1639 c = (reg1 < imm);
1640 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1641 && (reg1 & 0x80000000) != (value & 0x80000000));
1642
1643 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1644 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1645 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1646 }
1647
1648 /* cmp am, an */
1649 void OP_B0 (insn, extension)
1650 unsigned long insn, extension;
1651 {
1652 int z, c, n, v;
1653 unsigned long reg1, reg2, value;
1654
1655 reg1 = State.regs[REG_A0 + REG1 (insn)];
1656 reg2 = State.regs[REG_A0 + REG0 (insn)];
1657 value = reg2 - reg1;
1658
1659 z = (value == 0);
1660 n = (value & 0x80000000);
1661 c = (reg1 > reg2);
1662 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1663 && (reg2 & 0x80000000) != (value & 0x80000000));
1664
1665 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1666 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1667 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1668 }
1669
1670 /* cmp imm16, dn */
1671 void OP_FAC80000 (insn, extension)
1672 unsigned long insn, extension;
1673 {
1674 int z, c, n, v;
1675 unsigned long reg1, imm, value;
1676
1677 reg1 = State.regs[REG_D0 + REG0_16 (insn)];
1678 imm = SEXT16 (insn & 0xffff);
1679 value = reg1 - imm;
1680
1681 z = (value == 0);
1682 n = (value & 0x80000000);
1683 c = (reg1 < imm);
1684 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1685 && (reg1 & 0x80000000) != (value & 0x80000000));
1686
1687 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1688 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1689 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1690 }
1691
1692 /* cmp imm32, dn */
1693 void OP_FCC80000 (insn, extension)
1694 unsigned long insn, extension;
1695 {
1696 int z, c, n, v;
1697 unsigned long reg1, imm, value;
1698
1699 reg1 = State.regs[REG_D0 + REG0_16 (insn)];
1700 imm = ((insn & 0xffff) << 16) + extension;
1701 value = reg1 - imm;
1702
1703 z = (value == 0);
1704 n = (value & 0x80000000);
1705 c = (reg1 < imm);
1706 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1707 && (reg1 & 0x80000000) != (value & 0x80000000));
1708
1709 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1710 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1711 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1712 }
1713
1714 /* cmp imm16, an */
1715 void OP_FAD80000 (insn, extension)
1716 unsigned long insn, extension;
1717 {
1718 int z, c, n, v;
1719 unsigned long reg1, imm, value;
1720
1721 reg1 = State.regs[REG_A0 + REG0_16 (insn)];
1722 imm = insn & 0xffff;
1723 value = reg1 - imm;
1724
1725 z = (value == 0);
1726 n = (value & 0x80000000);
1727 c = (reg1 < imm);
1728 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1729 && (reg1 & 0x80000000) != (value & 0x80000000));
1730
1731 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1732 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1733 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1734 }
1735
1736 /* cmp imm32, an */
1737 void OP_FCD80000 (insn, extension)
1738 unsigned long insn, extension;
1739 {
1740 int z, c, n, v;
1741 unsigned long reg1, imm, value;
1742
1743 reg1 = State.regs[REG_A0 + REG0_16 (insn)];
1744 imm = ((insn & 0xffff) << 16) + extension;
1745 value = reg1 - imm;
1746
1747 z = (value == 0);
1748 n = (value & 0x80000000);
1749 c = (reg1 < imm);
1750 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1751 && (reg1 & 0x80000000) != (value & 0x80000000));
1752
1753 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1754 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1755 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1756 }
1757
1758 /* and dm, dn */
1759 void OP_F200 (insn, extension)
1760 unsigned long insn, extension;
1761 {
1762 int n, z;
1763
1764 State.regs[REG_D0 + REG0 (insn)] &= State.regs[REG_D0 + REG1 (insn)];
1765 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1766 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
1767 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1768 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1769 }
1770
1771 /* and imm8, dn */
1772 void OP_F8E000 (insn, extension)
1773 unsigned long insn, extension;
1774 {
1775 int n, z;
1776
1777 State.regs[REG_D0 + REG0_8 (insn)] &= (insn & 0xff);
1778 z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
1779 n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
1780 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1781 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1782 }
1783
1784 /* and imm16, dn */
1785 void OP_FAE00000 (insn, extension)
1786 unsigned long insn, extension;
1787 {
1788 int n, z;
1789
1790 State.regs[REG_D0 + REG0_16 (insn)] &= (insn & 0xffff);
1791 z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
1792 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
1793 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1794 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1795 }
1796
1797 /* and imm32, dn */
1798 void OP_FCE00000 (insn, extension)
1799 unsigned long insn, extension;
1800 {
1801 int n, z;
1802
1803 State.regs[REG_D0 + REG0_16 (insn)]
1804 &= ((insn & 0xffff) << 16) + extension;
1805 z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
1806 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
1807 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1808 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1809 }
1810
1811 /* and imm16, psw */
1812 void OP_FAFC0000 (insn, extension)
1813 unsigned long insn, extension;
1814 {
1815 PSW &= (insn & 0xffff);
1816 }
1817
1818 /* or dm, dn*/
1819 void OP_F210 (insn, extension)
1820 unsigned long insn, extension;
1821 {
1822 int n, z;
1823
1824 State.regs[REG_D0 + REG0 (insn)] |= State.regs[REG_D0 + REG1 (insn)];
1825 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1826 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
1827 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1828 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1829 }
1830
1831 /* or imm8, dn */
1832 void OP_F8E400 (insn, extension)
1833 unsigned long insn, extension;
1834 {
1835 int n, z;
1836
1837 State.regs[REG_D0 + REG0_8 (insn)] |= insn & 0xff;
1838 z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
1839 n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
1840 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1841 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1842 }
1843
1844 /* or imm16, dn*/
1845 void OP_FAE40000 (insn, extension)
1846 unsigned long insn, extension;
1847 {
1848 int n, z;
1849
1850 State.regs[REG_D0 + REG0_16 (insn)] |= insn & 0xffff;
1851 z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
1852 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
1853 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1854 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1855 }
1856
1857 /* or imm32, dn */
1858 void OP_FCE40000 (insn, extension)
1859 unsigned long insn, extension;
1860 {
1861 int n, z;
1862
1863 State.regs[REG_D0 + REG0_16 (insn)]
1864 |= ((insn & 0xffff) << 16) + extension;
1865 z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
1866 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
1867 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1868 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1869 }
1870
1871 /* or imm16,psw */
1872 void OP_FAFD0000 (insn, extension)
1873 unsigned long insn, extension;
1874 {
1875 PSW |= (insn & 0xffff);
1876 }
1877
1878 /* xor dm, dn */
1879 void OP_F220 (insn, extension)
1880 unsigned long insn, extension;
1881 {
1882 int n, z;
1883
1884 State.regs[REG_D0 + REG0 (insn)] ^= State.regs[REG_D0 + REG1 (insn)];
1885 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1886 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
1887 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1888 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1889 }
1890
1891 /* xor imm16, dn */
1892 void OP_FAE80000 (insn, extension)
1893 unsigned long insn, extension;
1894 {
1895 int n, z;
1896
1897 State.regs[REG_D0 + REG0_16 (insn)] ^= insn & 0xffff;
1898 z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
1899 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
1900 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1901 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1902 }
1903
1904 /* xor imm32, dn */
1905 void OP_FCE80000 (insn, extension)
1906 unsigned long insn, extension;
1907 {
1908 int n, z;
1909
1910 State.regs[REG_D0 + REG0_16 (insn)]
1911 ^= ((insn & 0xffff) << 16) + extension;
1912 z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
1913 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
1914 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1915 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1916 }
1917
1918 /* not dn */
1919 void OP_F230 (insn, extension)
1920 unsigned long insn, extension;
1921 {
1922 int n, z;
1923
1924 State.regs[REG_D0 + REG0 (insn)] = ~State.regs[REG_D0 + REG0 (insn)];
1925 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
1926 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
1927 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1928 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1929 }
1930
1931 /* btst imm8, dn */
1932 void OP_F8EC00 (insn, extension)
1933 unsigned long insn, extension;
1934 {
1935 unsigned long temp;
1936 int z, n;
1937
1938 temp = State.regs[REG_D0 + REG0_8 (insn)];
1939 temp &= (insn & 0xff);
1940 n = (temp & 0x80000000) != 0;
1941 z = (temp == 0);
1942 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1943 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
1944 }
1945
1946 /* btst imm16, dn */
1947 void OP_FAEC0000 (insn, extension)
1948 unsigned long insn, extension;
1949 {
1950 unsigned long temp;
1951 int z, n;
1952
1953 temp = State.regs[REG_D0 + REG0_16 (insn)];
1954 temp &= (insn & 0xffff);
1955 n = (temp & 0x80000000) != 0;
1956 z = (temp == 0);
1957 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1958 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
1959 }
1960
1961 /* btst imm32, dn */
1962 void OP_FCEC0000 (insn, extension)
1963 unsigned long insn, extension;
1964 {
1965 unsigned long temp;
1966 int z, n;
1967
1968 temp = State.regs[REG_D0 + REG0_16 (insn)];
1969 temp &= ((insn & 0xffff) << 16) + extension;
1970 n = (temp & 0x80000000) != 0;
1971 z = (temp == 0);
1972 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1973 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
1974 }
1975
1976 /* btst imm8,(abs32) */
1977 void OP_FE020000 (insn, extension)
1978 unsigned long insn, extension;
1979 {
1980 unsigned long temp;
1981 int n, z;
1982
1983 temp = load_byte (((insn & 0xffff) << 16) | (extension >> 8));
1984 temp &= (extension & 0xff);
1985 n = (temp & 0x80000000) != 0;
1986 z = (temp == 0);
1987 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1988 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
1989 }
1990
1991 /* btst imm8,(d8,an) */
1992 void OP_FAF80000 (insn, extension)
1993 unsigned long insn, extension;
1994 {
1995 unsigned long temp;
1996 int n, z;
1997
1998 temp = load_byte ((State.regs[REG_A0 + REG0_16 (insn)]
1999 + SEXT8 ((insn & 0xff00) >> 8)));
2000 temp &= (insn & 0xff);
2001 n = (temp & 0x80000000) != 0;
2002 z = (temp == 0);
2003 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2004 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
2005 }
2006
2007 /* bset dm, (an) */
2008 void OP_F080 (insn, extension)
2009 unsigned long insn, extension;
2010 {
2011 unsigned long temp;
2012 int z;
2013
2014 temp = load_byte (State.regs[REG_A0 + REG0 (insn)]);
2015 z = (temp & State.regs[REG_D0 + REG1 (insn)]) == 0;
2016 temp |= State.regs[REG_D0 + REG1 (insn)];
2017 store_byte (State.regs[REG_A0 + REG0 (insn)], temp);
2018 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2019 PSW |= (z ? PSW_Z : 0);
2020 }
2021
2022 /* bset imm8, (abs32) */
2023 void OP_FE000000 (insn, extension)
2024 unsigned long insn, extension;
2025 {
2026 unsigned long temp;
2027 int z;
2028
2029 temp = load_byte (((insn & 0xffff) << 16 | (extension >> 8)));
2030 z = (temp & (extension & 0xff)) == 0;
2031 temp |= (extension & 0xff);
2032 store_byte ((((insn & 0xffff) << 16) | (extension >> 8)), temp);
2033 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2034 PSW |= (z ? PSW_Z : 0);
2035 }
2036
2037 /* bset imm8,(d8,an) */
2038 void OP_FAF00000 (insn, extension)
2039 unsigned long insn, extension;
2040 {
2041 unsigned long temp;
2042 int z;
2043
2044 temp = load_byte ((State.regs[REG_A0 + REG0_16 (insn)]
2045 + SEXT8 ((insn & 0xff00) >> 8)));
2046 z = (temp & (insn & 0xff)) == 0;
2047 temp |= (insn & 0xff);
2048 store_byte ((State.regs[REG_A0 + REG0_16 (insn)]
2049 + SEXT8 ((insn & 0xff00) >> 8)), temp);
2050 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2051 PSW |= (z ? PSW_Z : 0);
2052 }
2053
2054 /* bclr dm, (an) */
2055 void OP_F090 (insn, extension)
2056 unsigned long insn, extension;
2057 {
2058 unsigned long temp;
2059 int z;
2060
2061 temp = load_byte (State.regs[REG_A0 + REG0 (insn)]);
2062 z = (temp & State.regs[REG_D0 + REG1 (insn)]) == 0;
2063 temp = temp & ~State.regs[REG_D0 + REG1 (insn)];
2064 store_byte (State.regs[REG_A0 + REG0 (insn)], temp);
2065 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2066 PSW |= (z ? PSW_Z : 0);
2067 }
2068
2069 /* bclr imm8, (abs32) */
2070 void OP_FE010000 (insn, extension)
2071 unsigned long insn, extension;
2072 {
2073 unsigned long temp;
2074 int z;
2075
2076 temp = load_byte (((insn & 0xffff) << 16) | (extension >> 8));
2077 z = (temp & (extension & 0xff)) == 0;
2078 temp = temp & ~(extension & 0xff);
2079 store_byte (((insn & 0xffff) << 16) | (extension >> 8), temp);
2080 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2081 PSW |= (z ? PSW_Z : 0);
2082 }
2083
2084 /* bclr imm8,(d8,an) */
2085 void OP_FAF40000 (insn, extension)
2086 unsigned long insn, extension;
2087 {
2088 unsigned long temp;
2089 int z;
2090
2091 temp = load_byte ((State.regs[REG_A0 + REG0_16 (insn)]
2092 + SEXT8 ((insn & 0xff00) >> 8)));
2093 z = (temp & (insn & 0xff)) == 0;
2094 temp = temp & ~(insn & 0xff);
2095 store_byte ((State.regs[REG_A0 + REG0_16 (insn)]
2096 + SEXT8 ((insn & 0xff00) >> 8)), temp);
2097 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2098 PSW |= (z ? PSW_Z : 0);
2099 }
2100
2101 /* asr dm, dn */
2102 void OP_F2B0 (insn, extension)
2103 unsigned long insn, extension;
2104 {
2105 long temp;
2106 int z, n, c;
2107
2108 temp = State.regs[REG_D0 + REG0 (insn)];
2109 c = temp & 1;
2110 temp >>= State.regs[REG_D0 + REG1 (insn)];
2111 State.regs[REG_D0 + REG0 (insn)] = temp;
2112 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
2113 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
2114 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2115 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2116 }
2117
2118 /* asr imm8, dn */
2119 void OP_F8C800 (insn, extension)
2120 unsigned long insn, extension;
2121 {
2122 long temp;
2123 int z, n, c;
2124
2125 temp = State.regs[REG_D0 + REG0_8 (insn)];
2126 c = temp & 1;
2127 temp >>= (insn & 0xff);
2128 State.regs[REG_D0 + REG0_8 (insn)] = temp;
2129 z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
2130 n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
2131 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2132 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2133 }
2134
2135 /* lsr dm, dn */
2136 void OP_F2A0 (insn, extension)
2137 unsigned long insn, extension;
2138 {
2139 int z, n, c;
2140
2141 c = State.regs[REG_D0 + REG0 (insn)] & 1;
2142 State.regs[REG_D0 + REG0 (insn)]
2143 >>= State.regs[REG_D0 + REG1 (insn)];
2144 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
2145 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
2146 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2147 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2148 }
2149
2150 /* lsr imm8, dn */
2151 void OP_F8C400 (insn, extension)
2152 unsigned long insn, extension;
2153 {
2154 int z, n, c;
2155
2156 c = State.regs[REG_D0 + REG0_8 (insn)] & 1;
2157 State.regs[REG_D0 + REG0_8 (insn)] >>= (insn & 0xff);
2158 z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
2159 n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
2160 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2161 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2162 }
2163
2164 /* asl dm, dn */
2165 void OP_F290 (insn, extension)
2166 unsigned long insn, extension;
2167 {
2168 int n, z;
2169
2170 State.regs[REG_D0 + REG0 (insn)]
2171 <<= State.regs[REG_D0 + REG1 (insn)];
2172 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
2173 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
2174 PSW &= ~(PSW_Z | PSW_N);
2175 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2176 }
2177
2178 /* asl imm8, dn */
2179 void OP_F8C000 (insn, extension)
2180 unsigned long insn, extension;
2181 {
2182 int n, z;
2183
2184 State.regs[REG_D0 + REG0_8 (insn)] <<= (insn & 0xff);
2185 z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
2186 n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
2187 PSW &= ~(PSW_Z | PSW_N);
2188 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2189 }
2190
2191 /* asl2 dn */
2192 void OP_54 (insn, extension)
2193 unsigned long insn, extension;
2194 {
2195 int n, z;
2196
2197 State.regs[REG_D0 + REG0 (insn)] <<= 2;
2198 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
2199 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
2200 PSW &= ~(PSW_Z | PSW_N);
2201 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2202 }
2203
2204 /* ror dn */
2205 void OP_F284 (insn, extension)
2206 unsigned long insn, extension;
2207 {
2208 unsigned long value;
2209 int c,n,z;
2210
2211 value = State.regs[REG_D0 + REG0 (insn)];
2212 c = (value & 0x1);
2213
2214 value >>= 1;
2215 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
2216 State.regs[REG_D0 + REG0 (insn)] = value;
2217 z = (value == 0);
2218 n = (value & 0x80000000) != 0;
2219 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2220 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2221 }
2222
2223 /* rol dn */
2224 void OP_F280 (insn, extension)
2225 unsigned long insn, extension;
2226 {
2227 unsigned long value;
2228 int c,n,z;
2229
2230 value = State.regs[REG_D0 + REG0 (insn)];
2231 c = (value & 0x80000000) ? 1 : 0;
2232
2233 value <<= 1;
2234 value |= ((PSW & PSW_C) != 0);
2235 State.regs[REG_D0 + REG0 (insn)] = value;
2236 z = (value == 0);
2237 n = (value & 0x80000000) != 0;
2238 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2239 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2240 }
2241
2242 /* beq label:8 */
2243 void OP_C800 (insn, extension)
2244 unsigned long insn, extension;
2245 {
2246 /* The dispatching code will add 2 after we return, so
2247 we subtract two here to make things right. */
2248 if (PSW & PSW_Z)
2249 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2250 }
2251
2252 /* bne label:8 */
2253 void OP_C900 (insn, extension)
2254 unsigned long insn, extension;
2255 {
2256 /* The dispatching code will add 2 after we return, so
2257 we subtract two here to make things right. */
2258 if (!(PSW & PSW_Z))
2259 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2260 }
2261
2262 /* bgt label:8 */
2263 void OP_C100 (insn, extension)
2264 unsigned long insn, extension;
2265 {
2266 /* The dispatching code will add 2 after we return, so
2267 we subtract two here to make things right. */
2268 if (!((PSW & PSW_Z)
2269 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
2270 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2271 }
2272
2273 /* bge label:8 */
2274 void OP_C200 (insn, extension)
2275 unsigned long insn, extension;
2276 {
2277 /* The dispatching code will add 2 after we return, so
2278 we subtract two here to make things right. */
2279 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2280 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2281 }
2282
2283 /* ble label:8 */
2284 void OP_C300 (insn, extension)
2285 unsigned long insn, extension;
2286 {
2287 /* The dispatching code will add 2 after we return, so
2288 we subtract two here to make things right. */
2289 if ((PSW & PSW_Z)
2290 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2291 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2292 }
2293
2294 /* blt label:8 */
2295 void OP_C000 (insn, extension)
2296 unsigned long insn, extension;
2297 {
2298 /* The dispatching code will add 2 after we return, so
2299 we subtract two here to make things right. */
2300 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
2301 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2302 }
2303
2304 /* bhi label:8 */
2305 void OP_C500 (insn, extension)
2306 unsigned long insn, extension;
2307 {
2308 /* The dispatching code will add 2 after we return, so
2309 we subtract two here to make things right. */
2310 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
2311 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2312 }
2313
2314 /* bcc label:8 */
2315 void OP_C600 (insn, extension)
2316 unsigned long insn, extension;
2317 {
2318 /* The dispatching code will add 2 after we return, so
2319 we subtract two here to make things right. */
2320 if (!(PSW & PSW_C))
2321 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2322 }
2323
2324 /* bls label:8 */
2325 void OP_C700 (insn, extension)
2326 unsigned long insn, extension;
2327 {
2328 /* The dispatching code will add 2 after we return, so
2329 we subtract two here to make things right. */
2330 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
2331 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2332 }
2333
2334 /* bcs label:8 */
2335 void OP_C400 (insn, extension)
2336 unsigned long insn, extension;
2337 {
2338 /* The dispatching code will add 2 after we return, so
2339 we subtract two here to make things right. */
2340 if (PSW & PSW_C)
2341 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2342 }
2343
2344 /* bvc label:8 */
2345 void OP_F8E800 (insn, extension)
2346 unsigned long insn, extension;
2347 {
2348 /* The dispatching code will add 3 after we return, so
2349 we subtract two here to make things right. */
2350 if (!(PSW & PSW_V))
2351 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3;
2352 }
2353
2354 /* bvs label:8 */
2355 void OP_F8E900 (insn, extension)
2356 unsigned long insn, extension;
2357 {
2358 /* The dispatching code will add 3 after we return, so
2359 we subtract two here to make things right. */
2360 if (PSW & PSW_V)
2361 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3;
2362 }
2363
2364 /* bnc label:8 */
2365 void OP_F8EA00 (insn, extension)
2366 unsigned long insn, extension;
2367 {
2368 /* The dispatching code will add 3 after we return, so
2369 we subtract two here to make things right. */
2370 if (!(PSW & PSW_N))
2371 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3;
2372 }
2373
2374 /* bns label:8 */
2375 void OP_F8EB00 (insn, extension)
2376 unsigned long insn, extension;
2377 {
2378 /* The dispatching code will add 3 after we return, so
2379 we subtract two here to make things right. */
2380 if (PSW & PSW_N)
2381 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 3;
2382 }
2383
2384 /* bra label:8 */
2385 void OP_CA00 (insn, extension)
2386 unsigned long insn, extension;
2387 {
2388 /* The dispatching code will add 2 after we return, so
2389 we subtract two here to make things right. */
2390 State.regs[REG_PC] += SEXT8 (insn & 0xff) - 2;
2391 }
2392
2393 /* leq */
2394 void OP_D8 (insn, extension)
2395 unsigned long insn, extension;
2396 {
2397 /* The dispatching code will add 1 after we return, so
2398 we subtract one here to make things right. */
2399 if (PSW & PSW_Z)
2400 State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
2401 }
2402
2403 /* lne */
2404 void OP_D9 (insn, extension)
2405 unsigned long insn, extension;
2406 {
2407 /* The dispatching code will add 1 after we return, so
2408 we subtract one here to make things right. */
2409 if (!(PSW & PSW_Z))
2410 State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
2411 }
2412
2413 /* lgt */
2414 void OP_D1 (insn, extension)
2415 unsigned long insn, extension;
2416 {
2417 /* The dispatching code will add 1 after we return, so
2418 we subtract one here to make things right. */
2419 if (!((PSW & PSW_Z)
2420 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
2421 State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
2422 }
2423
2424 /* lge */
2425 void OP_D2 (insn, extension)
2426 unsigned long insn, extension;
2427 {
2428 /* The dispatching code will add 1 after we return, so
2429 we subtract one here to make things right. */
2430 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2431 State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
2432 }
2433
2434 /* lle */
2435 void OP_D3 (insn, extension)
2436 unsigned long insn, extension;
2437 {
2438 /* The dispatching code will add 1 after we return, so
2439 we subtract one here to make things right. */
2440 if ((PSW & PSW_Z)
2441 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2442 State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
2443 }
2444
2445 /* llt */
2446 void OP_D0 (insn, extension)
2447 unsigned long insn, extension;
2448 {
2449 /* The dispatching code will add 1 after we return, so
2450 we subtract one here to make things right. */
2451 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
2452 State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
2453 }
2454
2455 /* lhi */
2456 void OP_D5 (insn, extension)
2457 unsigned long insn, extension;
2458 {
2459 /* The dispatching code will add 1 after we return, so
2460 we subtract one here to make things right. */
2461 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
2462 State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
2463 }
2464
2465 /* lcc */
2466 void OP_D6 (insn, extension)
2467 unsigned long insn, extension;
2468 {
2469 /* The dispatching code will add 1 after we return, so
2470 we subtract one here to make things right. */
2471 if (!(PSW & PSW_C))
2472 State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
2473 }
2474
2475 /* lls */
2476 void OP_D7 (insn, extension)
2477 unsigned long insn, extension;
2478 {
2479 /* The dispatching code will add 1 after we return, so
2480 we subtract one here to make things right. */
2481 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
2482 State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
2483 }
2484
2485 /* lcs */
2486 void OP_D4 (insn, extension)
2487 unsigned long insn, extension;
2488 {
2489 /* The dispatching code will add 1 after we return, so
2490 we subtract one here to make things right. */
2491 if (PSW & PSW_C)
2492 State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
2493 }
2494
2495 /* lra */
2496 void OP_DA (insn, extension)
2497 unsigned long insn, extension;
2498 {
2499 State.regs[REG_PC] = State.regs[REG_LAR] - 4 - 1;
2500 }
2501
2502 /* setlb */
2503 void OP_DB (insn, extension)
2504 unsigned long insn, extension;
2505 {
2506 State.regs[REG_LIR] = load_mem_big (State.regs[REG_PC] + 1, 4);
2507 State.regs[REG_LAR] = State.regs[REG_PC] + 5;
2508 }
2509
2510 /* jmp (an) */
2511 void OP_F0F4 (insn, extension)
2512 unsigned long insn, extension;
2513 {
2514 State.regs[REG_PC] = State.regs[REG_A0 + REG0 (insn)] - 2;
2515 }
2516
2517 /* jmp label:16 */
2518 void OP_CC0000 (insn, extension)
2519 unsigned long insn, extension;
2520 {
2521 State.regs[REG_PC] += SEXT16 (insn & 0xffff) - 3;
2522 }
2523
2524 /* jmp label:32 */
2525 void OP_DC000000 (insn, extension)
2526 unsigned long insn, extension;
2527 {
2528 State.regs[REG_PC] += (((insn & 0xffffff) << 8) + extension) - 5;
2529 }
2530
2531 /* call label:16,reg_list,imm8 */
2532 void OP_CD000000 (insn, extension)
2533 unsigned long insn, extension;
2534 {
2535 unsigned int next_pc, sp;
2536 unsigned long mask;
2537
2538 sp = State.regs[REG_SP];
2539 next_pc = State.regs[REG_PC] + 5;
2540 State.mem[sp] = next_pc & 0xff;
2541 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2542 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2543 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2544
2545 mask = insn & 0xff;
2546
2547 if (mask & 0x80)
2548 {
2549 sp -= 4;
2550 store_word (sp, State.regs[REG_D0 + 2]);
2551 }
2552
2553 if (mask & 0x40)
2554 {
2555 sp -= 4;
2556 store_word (sp, State.regs[REG_D0 + 3]);
2557 }
2558
2559 if (mask & 0x20)
2560 {
2561 sp -= 4;
2562 store_word (sp, State.regs[REG_A0 + 2]);
2563 }
2564
2565 if (mask & 0x10)
2566 {
2567 sp -= 4;
2568 store_word (sp, State.regs[REG_A0 + 3]);
2569 }
2570
2571 if (mask & 0x8)
2572 {
2573 sp -= 4;
2574 store_word (sp, State.regs[REG_D0]);
2575 sp -= 4;
2576 store_word (sp, State.regs[REG_D0 + 1]);
2577 sp -= 4;
2578 store_word (sp, State.regs[REG_A0]);
2579 sp -= 4;
2580 store_word (sp, State.regs[REG_A0 + 1]);
2581 sp -= 4;
2582 store_word (sp, State.regs[REG_MDR]);
2583 sp -= 4;
2584 store_word (sp, State.regs[REG_LIR]);
2585 sp -= 4;
2586 store_word (sp, State.regs[REG_LAR]);
2587 sp -= 4;
2588 }
2589
2590 /* Update the stack pointer, note that the register saves to do not
2591 modify SP. The SP adjustment is derived totally from the imm8
2592 field. */
2593 State.regs[REG_SP] -= extension;
2594 State.regs[REG_MDR] = next_pc;
2595 State.regs[REG_PC] += SEXT16 ((insn & 0xffff00) >> 8) - 5;
2596 }
2597
2598 /* call label:32,reg_list,imm8*/
2599 void OP_DD000000 (insn, extension)
2600 unsigned long insn, extension;
2601 {
2602 unsigned int next_pc, sp, adjust;
2603 unsigned long mask;
2604
2605 sp = State.regs[REG_SP];
2606 next_pc = State.regs[REG_PC] + 7;
2607 State.mem[sp] = next_pc & 0xff;
2608 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2609 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2610 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2611
2612 mask = (extension & 0xff00) >> 8;
2613
2614 if (mask & 0x80)
2615 {
2616 sp -= 4;
2617 store_word (sp, State.regs[REG_D0 + 2]);
2618 }
2619
2620 if (mask & 0x40)
2621 {
2622 sp -= 4;
2623 store_word (sp, State.regs[REG_D0 + 3]);
2624 }
2625
2626 if (mask & 0x20)
2627 {
2628 sp -= 4;
2629 store_word (sp, State.regs[REG_A0 + 2]);
2630 }
2631
2632 if (mask & 0x10)
2633 {
2634 sp -= 4;
2635 store_word (sp, State.regs[REG_A0 + 3]);
2636 }
2637
2638 if (mask & 0x8)
2639 {
2640 sp -= 4;
2641 store_word (sp, State.regs[REG_D0]);
2642 sp -= 4;
2643 store_word (sp, State.regs[REG_D0 + 1]);
2644 sp -= 4;
2645 store_word (sp, State.regs[REG_A0]);
2646 sp -= 4;
2647 store_word (sp, State.regs[REG_A0 + 1]);
2648 sp -= 4;
2649 store_word (sp, State.regs[REG_MDR]);
2650 sp -= 4;
2651 store_word (sp, State.regs[REG_LIR]);
2652 sp -= 4;
2653 store_word (sp, State.regs[REG_LAR]);
2654 sp -= 4;
2655 }
2656
2657 /* Update the stack pointer, note that the register saves to do not
2658 modify SP. The SP adjustment is derived totally from the imm8
2659 field. */
2660 State.regs[REG_SP] -= (extension & 0xff);
2661 State.regs[REG_MDR] = next_pc;
2662 State.regs[REG_PC] += (((insn & 0xffffff) << 8) | ((extension & 0xff0000) >> 16)) - 7;
2663 }
2664
2665 /* calls (an) */
2666 void OP_F0F0 (insn, extension)
2667 unsigned long insn, extension;
2668 {
2669 unsigned int next_pc, sp;
2670
2671 sp = State.regs[REG_SP];
2672 next_pc = State.regs[REG_PC] + 2;
2673 State.mem[sp] = next_pc & 0xff;
2674 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2675 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2676 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2677 State.regs[REG_MDR] = next_pc;
2678 State.regs[REG_PC] = State.regs[REG_A0 + REG0 (insn)] - 2;
2679 }
2680
2681 /* calls label:16 */
2682 void OP_FAFF0000 (insn, extension)
2683 unsigned long insn, extension;
2684 {
2685 unsigned int next_pc, sp;
2686
2687 sp = State.regs[REG_SP];
2688 next_pc = State.regs[REG_PC] + 4;
2689 State.mem[sp] = next_pc & 0xff;
2690 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2691 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2692 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2693 State.regs[REG_MDR] = next_pc;
2694 State.regs[REG_PC] += SEXT16 (insn & 0xffff) - 4;
2695 }
2696
2697 /* calls label:32 */
2698 void OP_FCFF0000 (insn, extension)
2699 unsigned long insn, extension;
2700 {
2701 unsigned int next_pc, sp;
2702
2703 sp = State.regs[REG_SP];
2704 next_pc = State.regs[REG_PC] + 6;
2705 State.mem[sp] = next_pc & 0xff;
2706 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2707 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2708 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2709 State.regs[REG_MDR] = next_pc;
2710 State.regs[REG_PC] += (((insn & 0xffff) << 16) + extension) - 6;
2711 }
2712
2713 /* ret reg_list, imm8 */
2714 void OP_DF0000 (insn, extension)
2715 unsigned long insn, extension;
2716 {
2717 unsigned int sp, offset;
2718 unsigned long mask;
2719
2720 State.regs[REG_SP] += insn & 0xff;
2721 sp = State.regs[REG_SP];
2722
2723 offset = -4;
2724 mask = (insn & 0xff00) >> 8;
2725
2726 if (mask & 0x80)
2727 {
2728 State.regs[REG_D0 + 2] = load_word (sp + offset);
2729 offset -= 4;
2730 }
2731
2732 if (mask & 0x40)
2733 {
2734 State.regs[REG_D0 + 3] = load_word (sp + offset);
2735 offset -= 4;
2736 }
2737
2738 if (mask & 0x20)
2739 {
2740 State.regs[REG_A0 + 2] = load_word (sp + offset);
2741 offset -= 4;
2742 }
2743
2744 if (mask & 0x10)
2745 {
2746 State.regs[REG_A0 + 3] = load_word (sp + offset);
2747 offset -= 4;
2748 }
2749
2750 if (mask & 0x8)
2751 {
2752 State.regs[REG_D0] = load_word (sp + offset);
2753 offset -= 4;
2754 State.regs[REG_D0 + 1] = load_word (sp + offset);
2755 offset -= 4;
2756 State.regs[REG_A0] = load_word (sp + offset);
2757 offset -= 4;
2758 State.regs[REG_A0 + 1] = load_word (sp + offset);
2759 offset -= 4;
2760 State.regs[REG_MDR] = load_word (sp + offset);
2761 offset -= 4;
2762 State.regs[REG_LIR] = load_word (sp + offset);
2763 offset -= 4;
2764 State.regs[REG_LAR] = load_word (sp + offset);
2765 offset -= 4;
2766 }
2767
2768 /* Restore the PC value. */
2769 State.regs[REG_PC] = (State.mem[sp] | (State.mem[sp+1] << 8)
2770 | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
2771 State.regs[REG_PC] -= 3;
2772 }
2773
2774 /* retf reg_list,imm8 */
2775 void OP_DE0000 (insn, extension)
2776 unsigned long insn, extension;
2777 {
2778 unsigned int sp, offset;
2779 unsigned long mask;
2780
2781 State.regs[REG_SP] += (insn & 0xff);
2782 sp = State.regs[REG_SP];
2783 State.regs[REG_PC] = State.regs[REG_MDR] - 3;
2784
2785 offset = -4;
2786 mask = (insn & 0xff00) >> 8;
2787
2788 if (mask & 0x80)
2789 {
2790 State.regs[REG_D0 + 2] = load_word (sp + offset);
2791 offset -= 4;
2792 }
2793
2794 if (mask & 0x40)
2795 {
2796 State.regs[REG_D0 + 3] = load_word (sp + offset);
2797 offset -= 4;
2798 }
2799
2800 if (mask & 0x20)
2801 {
2802 State.regs[REG_A0 + 2] = load_word (sp + offset);
2803 offset -= 4;
2804 }
2805
2806 if (mask & 0x10)
2807 {
2808 State.regs[REG_A0 + 3] = load_word (sp + offset);
2809 offset -= 4;
2810 }
2811
2812 if (mask & 0x8)
2813 {
2814 State.regs[REG_D0] = load_word (sp + offset);
2815 offset -= 4;
2816 State.regs[REG_D0 + 1] = load_word (sp + offset);
2817 offset -= 4;
2818 State.regs[REG_A0] = load_word (sp + offset);
2819 offset -= 4;
2820 State.regs[REG_A0 + 1] = load_word (sp + offset);
2821 offset -= 4;
2822 State.regs[REG_MDR] = load_word (sp + offset);
2823 offset -= 4;
2824 State.regs[REG_LIR] = load_word (sp + offset);
2825 offset -= 4;
2826 State.regs[REG_LAR] = load_word (sp + offset);
2827 offset -= 4;
2828 }
2829 }
2830
2831 /* rets */
2832 void OP_F0FC (insn, extension)
2833 unsigned long insn, extension;
2834 {
2835 unsigned int sp;
2836
2837 sp = State.regs[REG_SP];
2838 State.regs[REG_PC] = (State.mem[sp] | (State.mem[sp+1] << 8)
2839 | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
2840 State.regs[REG_PC] -= 2;
2841 }
2842
2843 /* rti */
2844 void OP_F0FD (insn, extension)
2845 unsigned long insn, extension;
2846 {
2847 unsigned int sp, next_pc;
2848
2849 sp = State.regs[REG_SP];
2850 PSW = State.mem[sp] | (State.mem[sp + 1] << 8);
2851 State.regs[REG_PC] = (State.mem[sp+4] | (State.mem[sp+5] << 8)
2852 | (State.mem[sp+6] << 16) | (State.mem[sp+7] << 24));
2853 State.regs[REG_SP] += 8;
2854 }
2855
2856 /* trap */
2857 void OP_F0FE (insn, extension)
2858 unsigned long insn, extension;
2859 {
2860 unsigned int sp, next_pc;
2861
2862 sp = State.regs[REG_SP];
2863 next_pc = State.regs[REG_PC] + 2;
2864 State.mem[sp] = next_pc & 0xff;
2865 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2866 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2867 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2868 State.regs[REG_PC] = 0x40000010 - 2;
2869 }
2870
2871 /* syscall */
2872 void OP_F0C0 (insn, extension)
2873 unsigned long insn, extension;
2874 {
2875 /* We use this for simulated system calls; we may need to change
2876 it to a reserved instruction if we conflict with uses at
2877 Matsushita. */
2878 int save_errno = errno;
2879 errno = 0;
2880
2881 /* Registers passed to trap 0 */
2882
2883 /* Function number. */
2884 #define FUNC (State.regs[0])
2885
2886 /* Parameters. */
2887 #define PARM1 (State.regs[1])
2888 #define PARM2 (load_word (State.regs[REG_SP] + 12))
2889 #define PARM3 (load_word (State.regs[REG_SP] + 16))
2890
2891 /* Registers set by trap 0 */
2892
2893 #define RETVAL State.regs[0] /* return value */
2894 #define RETERR State.regs[1] /* return error code */
2895
2896 /* Turn a pointer in a register into a pointer into real memory. */
2897
2898 #define MEMPTR(x) (State.mem + x)
2899
2900 switch (FUNC)
2901 {
2902 #if !defined(__GO32__) && !defined(_WIN32)
2903 #ifdef TARGET_SYS_fork
2904 case TARGET_SYS_fork:
2905 RETVAL = fork ();
2906 break;
2907 #endif
2908 #ifdef TARGET_SYS_execve
2909 case TARGET_SYS_execve:
2910 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2911 (char **)MEMPTR (PARM3));
2912 break;
2913 #endif
2914 #ifdef TARGET_SYS_execv
2915 case TARGET_SYS_execv:
2916 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
2917 break;
2918 #endif
2919 #endif /* ! GO32 and ! WIN32 */
2920
2921 case TARGET_SYS_read:
2922 RETVAL = mn10300_callback->read (mn10300_callback, PARM1,
2923 MEMPTR (PARM2), PARM3);
2924 break;
2925 case TARGET_SYS_write:
2926 RETVAL = (int)mn10300_callback->write (mn10300_callback, PARM1,
2927 MEMPTR (PARM2), PARM3);
2928 break;
2929 case TARGET_SYS_lseek:
2930 RETVAL = mn10300_callback->lseek (mn10300_callback, PARM1, PARM2, PARM3);
2931 break;
2932 case TARGET_SYS_close:
2933 RETVAL = mn10300_callback->close (mn10300_callback, PARM1);
2934 break;
2935 case TARGET_SYS_open:
2936 RETVAL = mn10300_callback->open (mn10300_callback, MEMPTR (PARM1), PARM2);
2937 break;
2938 case TARGET_SYS_exit:
2939 /* EXIT - caller can look in PARM1 to work out the
2940 reason */
2941 if (PARM1 == 0xdead)
2942 State.exception = SIGABRT;
2943 else
2944 State.exception = SIGQUIT;
2945 State.exited = 1;
2946 break;
2947
2948 case TARGET_SYS_stat: /* added at hmsi */
2949 /* stat system call */
2950 {
2951 struct stat host_stat;
2952 reg_t buf;
2953
2954 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2955
2956 buf = PARM2;
2957
2958 /* Just wild-assed guesses. */
2959 store_half (buf, host_stat.st_dev);
2960 store_half (buf + 2, host_stat.st_ino);
2961 store_word (buf + 4, host_stat.st_mode);
2962 store_half (buf + 8, host_stat.st_nlink);
2963 store_half (buf + 10, host_stat.st_uid);
2964 store_half (buf + 12, host_stat.st_gid);
2965 store_half (buf + 14, host_stat.st_rdev);
2966 store_word (buf + 16, host_stat.st_size);
2967 store_word (buf + 20, host_stat.st_atime);
2968 store_word (buf + 28, host_stat.st_mtime);
2969 store_word (buf + 36, host_stat.st_ctime);
2970 }
2971 break;
2972
2973 #ifdef TARGET_SYS_chown
2974 case TARGET_SYS_chown:
2975 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2976 break;
2977 #endif
2978 case TARGET_SYS_chmod:
2979 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2980 break;
2981 #ifdef TARGET_SYS_time
2982 case TARGET_SYS_time:
2983 RETVAL = time ((void*) MEMPTR (PARM1));
2984 break;
2985 #endif
2986 #ifdef TARGET_SYS_times
2987 case TARGET_SYS_times:
2988 {
2989 struct tms tms;
2990 RETVAL = times (&tms);
2991 store_word (PARM1, tms.tms_utime);
2992 store_word (PARM1 + 4, tms.tms_stime);
2993 store_word (PARM1 + 8, tms.tms_cutime);
2994 store_word (PARM1 + 12, tms.tms_cstime);
2995 break;
2996 }
2997 #endif
2998 #ifdef TARGET_SYS_gettimeofday
2999 case TARGET_SYS_gettimeofday:
3000 {
3001 struct timeval t;
3002 struct timezone tz;
3003 RETVAL = gettimeofday (&t, &tz);
3004 store_word (PARM1, t.tv_sec);
3005 store_word (PARM1 + 4, t.tv_usec);
3006 store_word (PARM2, tz.tz_minuteswest);
3007 store_word (PARM2 + 4, tz.tz_dsttime);
3008 break;
3009 }
3010 #endif
3011 #ifdef TARGET_SYS_utime
3012 case TARGET_SYS_utime:
3013 /* Cast the second argument to void *, to avoid type mismatch
3014 if a prototype is present. */
3015 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
3016 break;
3017 #endif
3018 default:
3019 abort ();
3020 }
3021 RETERR = errno;
3022 errno = save_errno;
3023 }
3024
3025 /* rtm */
3026 void OP_F0FF (insn, extension)
3027 unsigned long insn, extension;
3028 {
3029 abort ();
3030 }
3031
3032 /* nop */
3033 void OP_CB (insn, extension)
3034 unsigned long insn, extension;
3035 {
3036 }
3037
3038 /* putx dm,dm */
3039 void OP_F500 (insn, extension)
3040 unsigned long insn, extension;
3041 {
3042 State.regs[REG_MDRQ] = State.regs[REG_D0 + REG0 (insn)];
3043 }
3044
3045 /* getx dm,dm */
3046 void OP_F6F0 (insn, extension)
3047 unsigned long insn, extension;
3048 {
3049 int z, n;
3050 z = (State.regs[REG_MDRQ] == 0);
3051 n = ((State.regs[REG_MDRQ] & 0x80000000) != 0);
3052 State.regs[REG_D0 + REG0 (insn)] = State.regs[REG_MDRQ];
3053
3054 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3055 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
3056 }
3057
3058 /* mulq dm,dn */
3059 void OP_F600 (insn, extension)
3060 unsigned long insn, extension;
3061 {
3062 unsigned long long temp;
3063 int n, z;
3064
3065 temp = ((signed64)(signed32)State.regs[REG_D0 + REG0 (insn)]
3066 * (signed64)(signed32)State.regs[REG_D0 + REG1 (insn)]);
3067 State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff;
3068 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3069 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
3070 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
3071 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3072 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3073 }
3074
3075 /* mulq imm8,dn */
3076 void OP_F90000 (insn, extension)
3077 unsigned long insn, extension;
3078 {
3079 unsigned long long temp;
3080 int n, z;
3081
3082 temp = ((signed64)(signed32)State.regs[REG_D0 + REG0_8 (insn)]
3083 * (signed64)(signed32)SEXT8 (insn & 0xff));
3084 State.regs[REG_D0 + REG0_8 (insn)] = temp & 0xffffffff;
3085 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3086 z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
3087 n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
3088 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3089 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3090 }
3091
3092 /* mulq imm16,dn */
3093 void OP_FB000000 (insn, extension)
3094 unsigned long insn, extension;
3095 {
3096 unsigned long long temp;
3097 int n, z;
3098
3099 temp = ((signed64)(signed32)State.regs[REG_D0 + REG0_16 (insn)]
3100 * (signed64)(signed32)SEXT16 (insn & 0xffff));
3101 State.regs[REG_D0 + REG0_16 (insn)] = temp & 0xffffffff;
3102 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3103 z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
3104 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
3105 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3106 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3107 }
3108
3109 /* mulq imm32,dn */
3110 void OP_FD000000 (insn, extension)
3111 unsigned long insn, extension;
3112 {
3113 unsigned long long temp;
3114 int n, z;
3115
3116 temp = ((signed64)(signed32)State.regs[REG_D0 + REG0_16 (insn)]
3117 * (signed64)(signed32)(((insn & 0xffff) << 16) + extension));
3118 State.regs[REG_D0 + REG0_16 (insn)] = temp & 0xffffffff;
3119 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3120 z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
3121 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
3122 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3123 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3124 }
3125
3126 /* mulqu dm,dn */
3127 void OP_F610 (insn, extension)
3128 unsigned long insn, extension;
3129 {
3130 unsigned long long temp;
3131 int n, z;
3132
3133 temp = ((unsigned64) State.regs[REG_D0 + REG0 (insn)]
3134 * (unsigned64) State.regs[REG_D0 + REG1 (insn)]);
3135 State.regs[REG_D0 + REG0 (insn)] = temp & 0xffffffff;
3136 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3137 z = (State.regs[REG_D0 + REG0 (insn)] == 0);
3138 n = (State.regs[REG_D0 + REG0 (insn)] & 0x80000000) != 0;
3139 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3140 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3141 }
3142
3143 /* mulqu imm8,dn */
3144 void OP_F91400 (insn, extension)
3145 unsigned long insn, extension;
3146 {
3147 unsigned long long temp;
3148 int n, z;
3149
3150 temp = ((unsigned64)State.regs[REG_D0 + REG0_8 (insn)]
3151 * (unsigned64)SEXT8 (insn & 0xff));
3152 State.regs[REG_D0 + REG0_8 (insn)] = temp & 0xffffffff;
3153 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3154 z = (State.regs[REG_D0 + REG0_8 (insn)] == 0);
3155 n = (State.regs[REG_D0 + REG0_8 (insn)] & 0x80000000) != 0;
3156 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3157 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3158 }
3159
3160 /* mulqu imm16,dn */
3161 void OP_FB140000 (insn, extension)
3162 unsigned long insn, extension;
3163 {
3164 unsigned long long temp;
3165 int n, z;
3166
3167 temp = ((unsigned64)State.regs[REG_D0 + REG0_16 (insn)]
3168 * (unsigned64) SEXT16 (insn & 0xffff));
3169 State.regs[REG_D0 + REG0_16 (insn)] = temp & 0xffffffff;
3170 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3171 z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
3172 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
3173 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3174 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3175 }
3176
3177 /* mulqu imm32,dn */
3178 void OP_FD140000 (insn, extension)
3179 unsigned long insn, extension;
3180 {
3181 unsigned long long temp;
3182 int n, z;
3183
3184 temp = ((unsigned64)State.regs[REG_D0 + REG0_16 (insn)]
3185 * (unsigned64)(((insn & 0xffff) << 16) + extension));
3186 State.regs[REG_D0 + REG0_16 (insn)] = temp & 0xffffffff;
3187 State.regs[REG_MDRQ] = (temp & 0xffffffff00000000LL) >> 32;;
3188 z = (State.regs[REG_D0 + REG0_16 (insn)] == 0);
3189 n = (State.regs[REG_D0 + REG0_16 (insn)] & 0x80000000) != 0;
3190 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3191 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3192 }
3193
3194 /* sat16 dm,dn */
3195 void OP_F640 (insn, extension)
3196 unsigned long insn, extension;
3197 {
3198 int temp;
3199
3200 temp = State.regs[REG_D0 + REG1 (insn)];
3201 temp = (temp > 0x7fff ? 0x7fff : temp);
3202 temp = (temp < -0x8000 ? -0x8000 : temp);
3203 State.regs[REG_D0 + REG0 (insn)] = temp;
3204 }
3205
3206 /* sat24 dm,dn */
3207 void OP_F650 (insn, extension)
3208 unsigned long insn, extension;
3209 {
3210 int temp;
3211
3212 temp = State.regs[REG_D0 + REG1 (insn)];
3213 temp = (temp > 0x7fffff ? 0x7fffff : temp);
3214 temp = (temp < -0x800000 ? -0x800000 : temp);
3215 State.regs[REG_D0 + REG0 (insn)] = temp;
3216 }
3217
3218 /* bsch dm,dn */
3219 void OP_F670 (insn, extension)
3220 unsigned long insn, extension;
3221 {
3222 int temp, c;
3223
3224 temp = State.regs[REG_D0 + REG1 (insn)];
3225 temp <<= (State.regs[REG_D0 + REG0 (insn)] & 0x1f);
3226 c = (temp != 0 ? 1 : 0);
3227 PSW &= ~(PSW_C);
3228 PSW |= (c ? PSW_C : 0);
3229 }
3230
3231 /* breakpoint */
3232 void
3233 OP_FF (insn, extension)
3234 unsigned long insn, extension;
3235 {
3236 State.exception = SIGTRAP;
3237 PC -= 1;
3238 }
3239
The GNU Binutils are a collection of binary tools.