| blob | ab4e57b95e4cf86e464849dd13eb3d7019ac67f3 |
1 /* tc-i386.c -- Assemble code for the Intel 80386
2 Copyright (C) 1989-2024 Free Software Foundation, Inc.
4 This file is part of GAS, the GNU Assembler.
6 GAS is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3, or (at your option)
9 any later version.
11 GAS is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with GAS; see the file COPYING. If not, write to the Free
18 Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 02110-1301, USA. */
21 /* Intel 80386 machine specific gas.
22 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
23 x86_64 support by Jan Hubicka (jh@suse.cz)
24 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
25 Bugs & suggestions are completely welcome. This is free software.
26 Please help us make it better. */
39 #include <limits.h>
41 #ifndef INFER_ADDR_PREFIX
42 #define INFER_ADDR_PREFIX 1
43 #endif
45 #ifndef DEFAULT_ARCH
47 #endif
49 #ifndef INLINE
50 #if __GNUC__ >= 2
51 #define INLINE __inline__
52 #else
53 #define INLINE
54 #endif
55 #endif
57 /* Prefixes will be emitted in the order defined below.
58 WAIT_PREFIX must be the first prefix since FWAIT is really is an
59 instruction, and so must come before any prefixes.
60 The preferred prefix order is SEG_PREFIX, ADDR_PREFIX, DATA_PREFIX,
61 REP_PREFIX/HLE_PREFIX, LOCK_PREFIX. */
62 #define WAIT_PREFIX 0
63 #define SEG_PREFIX 1
64 #define ADDR_PREFIX 2
65 #define DATA_PREFIX 3
66 #define REP_PREFIX 4
67 #define HLE_PREFIX REP_PREFIX
68 #define BND_PREFIX REP_PREFIX
69 #define LOCK_PREFIX 5
73 /* we define the syntax here (modulo base,index,scale syntax) */
78 /* these are the instruction mnemonic suffixes in AT&T syntax or
79 memory operand size in Intel syntax. */
88 #define OPERAND_TYPE_NONE { .bitfield = { .class = ClassNone } }
90 /* This matches the C -> StaticRounding alias in the opcode table. */
91 #define commutative staticrounding
93 /*
94 'templates' is for grouping together 'template' structures for opcodes
95 of the same name. This is only used for storing the insns in the grand
96 ole hash table of insns.
97 The templates themselves start at START and range up to (but not including)
98 END.
99 */
101 {
104 }
105 templates;
107 /* 386 operand encoding bytes: see 386 book for details of this. */
109 {
113 }
114 modrm_byte;
116 /* x86-64 extension prefix. */
119 /* 386 opcode byte to code indirect addressing. */
121 {
125 }
126 sib_byte;
128 /* x86 arch names, types and features */
130 {
138 }
139 arch_entry;
141 /* Modes for parse_insn() to operate in. */
143 parse_all,
144 parse_prefix,
145 parse_pseudo_prefix,
146 };
158 #ifdef TE_PE
161 #endif
194 #ifdef OBJ_AOUT
196 #endif
197 #ifdef OBJ_ELF
200 /* GNU_PROPERTY_X86_ISA_1_USED. */
202 /* GNU_PROPERTY_X86_FEATURE_2_USED. */
204 /* Generate x86 used ISA and feature properties. */
206 #endif
210 /* parse_register() returns this when a register alias cannot be used. */
221 /* VEX prefix. */
223 {
224 /* VEX prefix is either 2 byte or 3 byte. EVEX is 4 byte. */
227 /* Destination or source register specifier. */
231 /* 'md_assemble ()' gathers together information and puts it into a
232 i386_insn. */
234 union i386_op
235 {
239 };
241 enum i386_error
242 {
244 operand_size_mismatch,
245 operand_type_mismatch,
246 register_type_mismatch,
247 number_of_operands_mismatch,
248 invalid_instruction_suffix,
249 bad_imm4,
250 unsupported_with_intel_mnemonic,
251 unsupported_syntax,
252 unsupported_EGPR_for_addressing,
253 unsupported_nf,
254 unsupported,
255 unsupported_on_arch,
256 unsupported_64bit,
257 no_vex_encoding,
258 no_evex_encoding,
259 invalid_sib_address,
260 invalid_vsib_address,
261 invalid_vector_register_set,
262 invalid_tmm_register_set,
263 invalid_dest_and_src_register_set,
264 invalid_dest_register_set,
265 invalid_pseudo_prefix,
266 unsupported_vector_index_register,
267 unsupported_broadcast,
268 broadcast_needed,
269 unsupported_masking,
270 mask_not_on_destination,
271 no_default_mask,
272 unsupported_rc_sae,
273 unsupported_vector_size,
274 unsupported_rsp_register,
275 internal_error,
276 };
278 #ifdef OBJ_ELF
279 enum x86_tls_error_type
280 {
281 x86_tls_error_continue,
282 x86_tls_error_none,
283 x86_tls_error_insn,
284 x86_tls_error_opcode,
285 x86_tls_error_sib,
286 x86_tls_error_no_base_reg,
287 x86_tls_error_require_no_base_index_reg,
288 x86_tls_error_base_reg,
289 x86_tls_error_index_ebx,
290 x86_tls_error_eax,
291 x86_tls_error_RegA,
292 x86_tls_error_ebx,
293 x86_tls_error_rip,
294 x86_tls_error_dest_eax,
295 x86_tls_error_dest_rdi,
296 x86_tls_error_scale_factor,
297 x86_tls_error_base_reg_size,
298 x86_tls_error_dest_32bit_reg_size,
299 x86_tls_error_dest_64bit_reg_size,
300 x86_tls_error_dest_32bit_or_64bit_reg_size
301 };
302 #endif
304 struct _i386_insn
305 {
306 /* TM holds the template for the insn were currently assembling. */
307 insn_template tm;
309 /* SUFFIX holds the instruction size suffix for byte, word, dword
310 or qword, if given. */
313 /* OPCODE_LENGTH holds the number of base opcode bytes. */
316 /* OPERANDS gives the number of given operands. */
319 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
320 of given register, displacement, memory operands and immediate
321 operands. */
324 /* TYPES [i] is the type (see above #defines) which tells us how to
325 use OP[i] for the corresponding operand. */
328 /* Displacement expression, immediate expression, or register for each
329 operand. */
332 /* Flags for operands. */
334 #define Operand_PCrel 1
335 #define Operand_Mem 2
338 /* Relocation type for operand */
341 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
342 the base index byte below. */
347 /* SEG gives the seg_entries of this insn. They are zero unless
348 explicit segment overrides are given. */
351 /* PREFIX holds all the given prefix opcodes (usually null).
352 PREFIXES is the number of prefix opcodes. */
356 /* .insn allows for reserved opcode spaces. */
359 /* .insn also allows (requires) specifying immediate size. */
362 /* Register is in low 3 bits of opcode. */
365 /* The operand to a branch insn indicates an absolute branch. */
368 /* The operand to a branch insn indicates a far branch. */
371 /* There is a memory operand of (%dx) which should be only used
372 with input/output instructions. */
375 /* Extended states. */
376 enum
377 {
378 /* Use MMX state. */
380 /* Use XMM state. */
382 /* Use YMM state. */
384 /* Use ZMM state. */
386 /* Use TMM state. */
388 /* Use MASK state. */
392 /* Has GOTPC or TLS relocation. */
395 /* Has relocation entry from the gotrel array. */
398 /* RM and SIB are the modrm byte and the sib byte where the
399 addressing modes of this insn are encoded. */
400 modrm_byte rm;
401 rex_byte rex;
402 rex_byte vrex;
403 rex_byte rex2;
404 sib_byte sib;
405 vex_prefix vex;
407 /* Masking attributes.
409 The struct describes masking, applied to OPERAND in the instruction.
410 REG is a pointer to the corresponding mask register. ZEROING tells
411 whether merging or zeroing mask is used. */
412 struct Mask_Operation
413 {
416 /* The operand where this operation is associated. */
420 /* Rounding control and SAE attributes. */
421 struct RC_Operation
422 {
423 enum rc_type
424 {
426 rne,
427 rd,
428 ru,
429 rz,
430 saeonly
432 /* In Intel syntax the operand modifier form is supposed to be used, but
433 we continue to accept the immediate forms as well. */
437 /* Broadcasting attributes.
439 The struct describes broadcasting, applied to OPERAND. TYPE is
440 expresses the broadcast factor. */
441 struct Broadcast_Operation
442 {
443 /* Type of broadcast: {1to2}, {1to4}, {1to8}, {1to16} or {1to32}. */
446 /* Index of broadcasted operand. */
449 /* Number of bytes to broadcast. */
453 /* Compressed disp8*N attribute. */
456 /* SCC = EVEX.[SC3,SC2,SC1,SC0]. */
459 /* Store 4 bits of EVEX.[OF,SF,ZF,CF]. */
460 #define OSZC_CF 1
461 #define OSZC_ZF 2
462 #define OSZC_SF 4
463 #define OSZC_OF 8
466 /* Invert the condition encoded in a base opcode. */
469 /* REP prefix. */
472 /* HLE prefix. */
475 /* Have BND prefix. */
478 /* Have NOTRACK prefix. */
481 /* Error message. */
483 };
487 /* Pseudo-prefix recording state, separate from i386_insn. */
489 /* How to encode instructions. */
492 encoding_vex,
493 encoding_vex3,
495 encoding_evex,
496 encoding_evex512,
497 encoding_error
500 /* Prefer load or store in encoding. */
503 dir_encoding_load,
504 dir_encoding_store,
505 dir_encoding_swap
508 /* Prefer 8bit, 16bit, 32bit displacement in encoding. */
511 disp_encoding_8bit,
512 disp_encoding_16bit,
513 disp_encoding_32bit
516 /* Prefer the REX byte in encoding. */
519 /* Prefer the REX2 prefix in encoding. */
522 /* No CSPAZO flags update. */
525 /* Disable instruction size optimization. */
529 /* Link RC type with corresponding string, that'll be looked for in
530 asm. */
531 struct RC_name
532 {
536 };
539 {
545 };
547 /* To be indexed by segment register number. */
549 ES_PREFIX_OPCODE,
550 CS_PREFIX_OPCODE,
551 SS_PREFIX_OPCODE,
552 DS_PREFIX_OPCODE,
553 FS_PREFIX_OPCODE,
554 GS_PREFIX_OPCODE
555 };
557 /* List of chars besides those in app.c:symbol_chars that can start an
558 operand. Used to prevent the scrubber eating vital white-space. */
560 #ifdef LEX_AT
561 "@"
562 #endif
563 #ifdef LEX_QM
564 "?"
565 #endif
566 ;
568 #if (defined (OBJ_ELF) \
569 && !defined (TE_GNU) \
570 && !defined (TE_LINUX) \
571 && !defined (TE_Haiku) \
572 && !defined (TE_FreeBSD) \
573 && !defined (TE_DragonFly) \
574 && !defined (TE_NetBSD))
575 /* This array holds the chars that always start a comment. If the
576 pre-processor is disabled, these aren't very useful. The option
577 --divide will remove '/' from this list. */
579 #define SVR4_COMMENT_CHARS 1
582 #else
585 #endif
587 /* This array holds the chars that only start a comment at the beginning of
588 a line. If the line seems to have the form '# 123 filename'
589 .line and .file directives will appear in the pre-processed output.
590 Note that input_file.c hand checks for '#' at the beginning of the
591 first line of the input file. This is because the compiler outputs
592 #NO_APP at the beginning of its output.
593 Also note that comments started like this one will always work if
594 '/' isn't otherwise defined. */
599 /* Chars that can be used to separate mant from exp in floating point
600 nums. */
603 /* Chars that mean this number is a floating point constant
604 As in 0f12.456
605 or 0d1.2345e12. */
608 /* Tables for lexical analysis. */
613 /* Lexical macros. */
614 #define is_operand_char(x) (operand_chars[(unsigned char) x])
615 #define is_register_char(x) (register_chars[(unsigned char) x])
618 /* All non-digit non-letter characters that may occur in an operand and
619 which aren't already in extra_symbol_chars[]. */
622 /* md_assemble() always leaves the strings it's passed unaltered. To
623 effect this we maintain a stack of saved characters that we've smashed
624 with '\0's (indicating end of strings for various sub-fields of the
625 assembler instruction). */
628 #define END_STRING_AND_SAVE(s) \
630 #define RESTORE_END_STRING(s) \
631 do { *(s) = *--save_stack_p; } while (0)
633 /* The instruction we're assembling. */
636 /* Possible templates for current insn. */
639 /* Per instruction expressionS buffers: max displacements & immediates. */
643 /* Current operand we are working on. */
646 /* Are we processing a .insn directive? */
647 #define dot_insn() (i.tm.mnem_off == MN__insn)
654 /* __tls_get_addr/___tls_get_addr symbol for TLS. */
657 #ifdef OBJ_ELF
659 /* The ELF ABI to use. */
660 enum x86_elf_abi
661 {
662 I386_ABI,
663 X86_64_ABI,
664 X86_64_X32_ABI
665 };
668 #endif
670 #if defined (TE_PE) || defined (TE_PEP)
671 /* Use big object file format. */
673 #endif
675 #ifdef OBJ_ELF
676 /* 1 if generating code for a shared library. */
680 /* The other CFA base register for SFrame stack trace info. */
684 #endif
686 /* 1 for intel syntax,
687 0 if att syntax. */
690 static enum x86_64_isa
691 {
693 intel64 /* Intel64 ISA. */
696 /* 1 for intel mnemonic,
697 0 if att mnemonic. */
700 /* 1 if pseudo registers are permitted. */
703 /* 1 if register prefix % not required. */
706 /* 1 if the assembler should add BND prefix for all control-transferring
707 instructions supporting it, even if this prefix wasn't specified
708 explicitly. */
711 /* 1 if pseudo index register, eiz/riz, is allowed . */
714 /* 1 if the assembler should ignore LOCK prefix, even if it was
715 specified explicitly. */
718 /* 1 if the assembler should encode lfence, mfence, and sfence as
719 "lock addl $0, (%{re}sp)". */
722 /* 1 if lfence should be inserted after every load. */
725 /* Non-zero if lfence should be inserted before indirect branch. */
726 static enum lfence_before_indirect_branch_kind
727 {
729 lfence_branch_register,
730 lfence_branch_memory,
731 lfence_branch_all
732 }
733 lfence_before_indirect_branch;
735 /* Non-zero if lfence should be inserted before ret. */
736 static enum lfence_before_ret_kind
737 {
739 lfence_before_ret_not,
740 lfence_before_ret_or,
741 lfence_before_ret_shl
742 }
743 lfence_before_ret;
745 /* 1 if the assembler should generate relax relocations. */
747 static int generate_relax_relocations
750 /* 1 if the assembler should check tls relocation. */
753 static enum check_kind
754 {
756 check_warning,
757 check_error
758 }
761 /* Non-zero if branches should be aligned within power of 2 boundary. */
764 /* Types of branches to align. */
765 enum align_branch_kind
766 {
774 };
776 /* Type bits of branches to align. */
777 enum align_branch_bit
778 {
785 };
788 | align_branch_fused_bit
791 /* Types of condition jump used by macro-fusion. */
792 enum mf_jcc_kind
793 {
802 };
804 /* Types of compare flag-modifying insntructions used by macro-fusion. */
805 enum mf_cmp_kind
806 {
809 mf_cmp_incdec /* inc/dec */
810 };
812 /* The maximum padding size for fused jcc. CMP like instruction can
813 be 9 bytes and jcc can be 6 bytes. Leave room just in case for
814 prefixes. */
815 #define MAX_FUSED_JCC_PADDING_SIZE 20
817 /* The maximum number of prefixes added for an instruction. */
820 /* Optimization:
821 1. Clear the REX_W bit with register operand if possible.
822 2. Above plus use 128bit vector instruction to clear the full vector
823 register.
824 */
827 /* Optimization:
828 1. Clear the REX_W bit with register operand if possible.
829 2. Above plus use 128bit vector instruction to clear the full vector
830 register.
831 3. Above plus optimize "test{q,l,w} $imm8,%r{64,32,16}" to
832 "testb $imm7,%r8".
833 */
836 /* Register prefix used for error message. */
839 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
840 leave, push, and pop instructions so that gcc has the same stack
841 frame as in 32 bit mode. */
844 /* Non-zero to optimize code alignment. */
847 /* Non-zero to quieten some warnings. */
850 /* Guard to avoid repeated warnings about non-16-bit code on 16-bit CPUs. */
853 /* CPU name. */
857 /* CPU feature flags. */
860 /* ISA extensions available in 64-bit mode only. */
863 /* If we have selected a cpu we are generating instructions for. */
866 /* Cpu we are generating instructions for. */
869 /* CPU instruction set architecture used. */
872 /* CPU feature flags of instruction set architecture used. */
873 i386_cpu_flags cpu_arch_isa_flags;
875 /* If set, conditional jumps are not automatically promoted to handle
876 larger than a byte offset. */
879 /* This will be set from an expression parser hook if there's any
880 applicable operator involved in an expression. */
882 expr_operator_none,
883 expr_operator_present,
884 expr_large_value,
887 /* Encode SSE instructions with VEX prefix. */
890 /* Encode aligned vector move as unaligned vector move. */
893 /* Maximum permitted vector size. */
894 #define VSZ128 0
895 #define VSZ256 1
896 #define VSZ512 2
897 #define VSZ_DEFAULT VSZ512
900 /* Encode scalar AVX instructions with specific vector length. */
901 static enum
902 {
904 vex256
907 /* Encode VEX WIG instructions with specific vex.w. */
908 static enum
909 {
911 vexw1
914 /* Encode scalar EVEX LIG instructions with specific vector length. */
915 static enum
916 {
918 evexl256,
919 evexl512
922 /* Encode EVEX WIG instructions with specific evex.w. */
923 static enum
924 {
926 evexw1
929 /* Value to encode in EVEX RC bits, for SAE-only instructions. */
932 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
935 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
938 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
941 /* Interface to relax_segment.
942 There are 3 major relax states for 386 jump insns because the
943 different types of jumps add different sizes to frags when we're
944 figuring out what sort of jump to choose to reach a given label.
946 BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING are used to align
947 branches which are handled by md_estimate_size_before_relax() and
948 i386_generic_table_relax_frag(). */
950 /* Types. */
951 #define UNCOND_JUMP 0
952 #define COND_JUMP 1
953 #define COND_JUMP86 2
954 #define BRANCH_PADDING 3
955 #define BRANCH_PREFIX 4
956 #define FUSED_JCC_PADDING 5
958 /* Sizes. */
959 #define CODE16 1
960 #define SMALL 0
961 #define SMALL16 (SMALL | CODE16)
962 #define BIG 2
963 #define BIG16 (BIG | CODE16)
965 #ifndef INLINE
966 #ifdef __GNUC__
967 #define INLINE __inline__
968 #else
969 #define INLINE
970 #endif
971 #endif
973 #define ENCODE_RELAX_STATE(type, size) \
974 ((relax_substateT) (((type) << 2) | (size)))
975 #define TYPE_FROM_RELAX_STATE(s) \
976 ((s) >> 2)
977 #define DISP_SIZE_FROM_RELAX_STATE(s) \
978 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
980 /* This table is used by relax_frag to promote short jumps to long
981 ones where necessary. SMALL (short) jumps may be promoted to BIG
982 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
983 don't allow a short jump in a 32 bit code segment to be promoted to
984 a 16 bit offset jump because it's slower (requires data size
985 prefix), and doesn't work, unless the destination is in the bottom
986 64k of the code segment (The top 16 bits of eip are zeroed). */
989 {
990 /* The fields are:
991 1) most positive reach of this state,
992 2) most negative reach of this state,
993 3) how many bytes this mode will have in the variable part of the frag
994 4) which index into the table to try if we can't fit into this one. */
996 /* UNCOND_JUMP states. */
999 /* dword jmp adds 4 bytes to frag:
1000 0 extra opcode bytes, 4 displacement bytes. */
1002 /* word jmp adds 2 byte2 to frag:
1003 0 extra opcode bytes, 2 displacement bytes. */
1006 /* COND_JUMP states. */
1009 /* dword conditionals adds 5 bytes to frag:
1010 1 extra opcode byte, 4 displacement bytes. */
1012 /* word conditionals add 3 bytes to frag:
1013 1 extra opcode byte, 2 displacement bytes. */
1016 /* COND_JUMP86 states. */
1019 /* dword conditionals adds 5 bytes to frag:
1020 1 extra opcode byte, 4 displacement bytes. */
1022 /* word conditionals add 4 bytes to frag:
1023 1 displacement byte and a 3 byte long branch insn. */
1025 };
1027 #define ARCH(n, t, f, s) \
1028 { STRING_COMMA_LEN (#n), s, PROCESSOR_ ## t, vsz_none, CPU_ ## f ## _FLAGS, \
1029 CPU_NONE_FLAGS }
1030 #define SUBARCH(n, e, d, s) \
1031 { STRING_COMMA_LEN (#n), s, PROCESSOR_NONE, vsz_none, CPU_ ## e ## _FLAGS, \
1032 CPU_ ## d ## _FLAGS }
1033 #define VECARCH(n, e, d, v) \
1034 { STRING_COMMA_LEN (#n), false, PROCESSOR_NONE, vsz_ ## v, \
1035 CPU_ ## e ## _FLAGS, CPU_ ## d ## _FLAGS }
1038 {
1039 /* Do not replace the first two entries - i386_target_format() and
1040 set_cpu_arch() rely on them being there in this order. */
1225 };
1227 #undef SUBARCH
1228 #undef ARCH
1230 #ifdef I386COFF
1231 /* Like s_lcomm_internal in gas/read.c but the alignment string
1232 is allowed to be optional. */
1236 {
1243 {
1248 }
1249 else
1250 {
1257 else
1259 }
1263 }
1265 static void
1267 {
1269 }
1270 #endif
1273 {
1274 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
1276 #else
1278 #endif
1280 #ifdef OBJ_AOUT
1282 #endif
1283 #ifdef I386COFF
1285 #endif
1299 #ifdef BFD64
1301 #endif
1310 #ifdef OBJ_ELF
1312 #else
1316 #endif
1317 #ifdef TE_PE
1320 #endif
1322 };
1324 /* For interface with expression (). */
1327 /* Hash table for instruction mnemonic lookup. */
1330 /* Hash table for register lookup. */
1333 #if (defined (OBJ_ELF) || defined (OBJ_MACH_O) || defined (TE_PE))
1334 static const struct
1335 {
1341 }
1342 gotrel[] =
1343 {
1344 #define OPERAND_TYPE_IMM32_32S_DISP32 { .bitfield = \
1345 { .imm32 = 1, .imm32s = 1, .disp32 = 1 } }
1346 #define OPERAND_TYPE_IMM32_32S_64_DISP32 { .bitfield = \
1347 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1 } }
1348 #define OPERAND_TYPE_IMM32_32S_64_DISP32_64 { .bitfield = \
1349 { .imm32 = 1, .imm32s = 1, .imm64 = 1, .disp32 = 1, .disp64 = 1 } }
1350 #define OPERAND_TYPE_IMM64_DISP64 { .bitfield = \
1351 { .imm64 = 1, .disp64 = 1 } }
1353 #ifndef TE_PE
1354 #ifdef OBJ_ELF
1356 BFD_RELOC_SIZE32 },
1358 #endif
1360 BFD_RELOC_X86_64_PLTOFF64 },
1363 BFD_RELOC_X86_64_PLT32 },
1366 BFD_RELOC_X86_64_GOTPLT64 },
1369 BFD_RELOC_X86_64_GOTOFF64 },
1372 BFD_RELOC_X86_64_GOTPCREL },
1375 BFD_RELOC_X86_64_TLSGD },
1378 _dummy_first_bfd_reloc_code_real },
1381 BFD_RELOC_X86_64_TLSLD },
1384 BFD_RELOC_X86_64_GOTTPOFF },
1387 BFD_RELOC_X86_64_TPOFF32 },
1390 _dummy_first_bfd_reloc_code_real },
1393 BFD_RELOC_X86_64_DTPOFF32 },
1396 _dummy_first_bfd_reloc_code_real },
1399 _dummy_first_bfd_reloc_code_real },
1402 BFD_RELOC_X86_64_GOT32 },
1405 BFD_RELOC_X86_64_GOTPC32_TLSDESC },
1408 BFD_RELOC_X86_64_TLSDESC_CALL },
1412 BFD_RELOC_32_SECREL },
1414 #endif
1416 #undef OPERAND_TYPE_IMM32_32S_DISP32
1417 #undef OPERAND_TYPE_IMM32_32S_64_DISP32
1418 #undef OPERAND_TYPE_IMM32_32S_64_DISP32_64
1419 #undef OPERAND_TYPE_IMM64_DISP64
1420 };
1421 #endif
1422 \f
1423 /* Various efficient no-op patterns for aligning code labels.
1424 Note: Don't try to assemble the instructions in the comments.
1425 0L and 0w are not legal. */
1464 /* 32-bit NOPs patterns. */
1467 };
1468 /* 64-bit NOPs patterns. */
1471 };
1472 /* 16-bit NOPs patterns. */
1475 };
1476 /* nopl (%[re]ax) */
1479 /* nopl 0(%[re]ax) */
1482 /* nopl 0(%[re]ax,%[re]ax,1) */
1483 #define alt_5 (alt_6 + 1)
1484 /* nopw 0(%[re]ax,%[re]ax,1) */
1487 /* nopl 0L(%[re]ax) */
1490 /* nopl 0L(%[re]ax,%[re]ax,1) */
1491 #define alt_8 (alt_9 + 1)
1492 /* nopw 0L(%[re]ax,%[re]ax,1) */
1495 /* nopw %cs:0L(%[re]ax,%[re]ax,1) */
1496 #define alt_10 (alt_11 + 1)
1497 /* data16 nopw %cs:0L(%eax,%eax,1) */
1500 /* 32-bit and 64-bit NOPs patterns. */
1504 };
1507 /* data16 cs nopq 0L(%rax,%rax,1) */
1508 #define alt64_11 (alt64_15 + 4)
1509 /* data16 data16 cs nopq 0L(%rax,%rax,1) */
1510 #define alt64_12 (alt64_15 + 3)
1511 /* data16 data16 data16 cs nopq 0L(%rax,%rax,1) */
1512 #define alt64_13 (alt64_15 + 2)
1513 /* data16 data16 data16 data16 cs nopq 0L(%rax,%rax,1) */
1514 #define alt64_14 (alt64_15 + 1)
1515 /* data16 data16 data16 data16 data16 cs nopq 0L(%rax,%rax,1) */
1519 /* Long 64-bit NOPs patterns. */
1523 };
1525 /* Genenerate COUNT bytes of NOPs to WHERE from PATT with the maximum
1526 size of a single NOP instruction MAX_SINGLE_NOP_SIZE. */
1528 static void
1532 {
1533 /* Place the longer NOP first. */
1539 {
1541 max_single_nop_size);
1543 }
1553 {
1556 }
1557 }
1561 {
1563 }
1567 {
1569 }
1571 /* Genenerate COUNT bytes of NOPs to WHERE with the maximum size of a
1572 single NOP instruction LIMIT. */
1574 void
1576 {
1579 /* Maximum number of NOPs before switching to jump over NOPs. */
1583 {
1588 /* Allow NOP padding for jumps and calls. */
1592 /* Fall through. */
1595 }
1597 /* We need to decide which NOP sequence to use for 32bit and
1598 64bit. When -mtune= is used:
1600 1. For PROCESSOR_I?86, PROCESSOR_PENTIUM, PROCESSOR_IAMCU, and
1601 PROCESSOR_GENERIC32, f32_patt will be used.
1602 2. For the rest, alt_patt will be used.
1604 When -mtune= isn't used, alt_patt will be used if
1605 cpu_arch_isa_flags has CpuNop. Otherwise, f32_patt/f64_patt will
1606 be used.
1608 When -march= or .arch is used, we can't use anything beyond
1609 cpu_arch_isa_flags. */
1612 {
1615 /* Limit number of NOPs to 2 in 16-bit mode. */
1617 }
1618 else
1619 {
1622 {
1623 /* PROCESSOR_UNKNOWN means that all ISAs may be used, unless
1624 explicitly disabled. */
1626 {
1628 /* We use cpu_arch_isa_flags to check if we SHOULD
1629 optimize with nops. */
1638 {
1641 else
1643 }
1670 }
1671 }
1672 else
1673 {
1675 {
1677 /* When cpu_arch_isa is set, cpu_arch_tune shouldn't be
1678 PROCESSOR_UNKNOWN. */
1683 /* We use cpu_arch_isa_flags to check if we CAN optimize
1684 with nops. */
1691 }
1692 }
1695 {
1698 /* Limit number of NOPs to 2 for older processors. */
1700 }
1701 else
1702 {
1706 /* Limit number of NOPs to 7 for newer processors. */
1708 }
1709 }
1715 {
1716 /* Output NOPs for .nop directive. */
1718 {
1724 }
1725 }
1729 /* Emit a plain NOP first when the last thing we saw may not have been
1730 a proper instruction (e.g. a stand-alone prefix or .byte). */
1732 {
1735 }
1738 {
1739 /* Generate jump over NOPs. */
1742 {
1743 /* Use "jmp disp8" if possible. */
1748 }
1749 else
1750 {
1754 {
1758 }
1759 else
1760 {
1763 }
1767 {
1771 }
1775 }
1776 }
1778 /* Generate multiple NOPs. */
1780 }
1784 {
1786 {
1790 /* Fall through. */
1794 /* Fall through. */
1799 }
1800 }
1804 {
1806 {
1809 /* Fall through. */
1812 /* Fall through. */
1815 /* Fall through. */
1819 }
1823 }
1828 {
1830 {
1834 /* Fall through. */
1838 /* Fall through. */
1844 }
1845 }
1849 {
1851 {
1865 }
1867 }
1871 {
1873 }
1877 {
1879 }
1882 {
1887 {
1890 #ifndef WORDS_BIGENDIAN
1892 #else
1894 #endif
1897 #ifndef WORDS_BIGENDIAN
1899 #else
1901 #endif
1906 }
1909 #ifndef WORDS_BIGENDIAN
1911 #else
1913 #endif
1916 }
1920 {
1922 {
1926 /* Fall through. */
1930 /* Fall through. */
1934 /* Fall through. */
1938 /* Fall through. */
1943 }
1944 }
1949 {
1951 {
1955 /* Fall through. */
1959 /* Fall through. */
1963 /* Fall through. */
1967 /* Fall through. */
1973 }
1974 }
1978 {
1982 }
1984 static INLINE i386_cpu_flags
1986 {
1988 {
1991 /* Fall through. */
1994 /* Fall through. */
1997 /* Fall through. */
2000 /* Fall through. */
2006 }
2008 }
2010 static INLINE i386_cpu_flags
2012 {
2014 {
2017 /* Fall through. */
2020 /* Fall through. */
2023 /* Fall through. */
2026 /* Fall through. */
2032 }
2034 }
2036 static INLINE i386_cpu_flags
2038 {
2040 {
2043 /* Fall through. */
2046 /* Fall through. */
2049 /* Fall through. */
2052 /* Fall through. */
2058 }
2060 }
2065 {
2071 }
2073 #define CPU_FLAGS_ARCH_MATCH 0x1
2074 #define CPU_FLAGS_64BIT_MATCH 0x2
2076 #define CPU_FLAGS_PERFECT_MATCH \
2077 (CPU_FLAGS_ARCH_MATCH | CPU_FLAGS_64BIT_MATCH)
2080 {
2082 {
2085 }
2088 }
2090 /* Handle SCC OSZC flags. */
2092 static int
2094 {
2098 suffix_string++;
2100 /* If {oszc flags} is absent, just return. */
2104 /* Skip '{'. */
2105 suffix_string++;
2107 /* Parse 'dfv='. */
2109 suffix_string++;
2113 else
2114 {
2117 }
2120 suffix_string++;
2123 suffix_string++;
2124 else
2125 {
2128 }
2130 /* Parse 'of, sf, zf, cf}'. */
2132 {
2134 suffix_string++;
2136 /* Return for '{dfv=}'. */
2141 {
2144 }
2146 {
2149 }
2151 {
2154 }
2156 {
2159 }
2160 else
2161 {
2164 }
2169 suffix_string++;
2176 suffix_string ++;
2177 }
2181 }
2183 /* Return CPU flags match bits. */
2185 static int
2187 {
2198 {
2199 /* This instruction is available on all archs. */
2201 }
2203 /* This instruction is available only on some archs. */
2205 /* Dual VEX/EVEX templates may need stripping of one of the flags. */
2207 {
2208 /* Dual AVX/AVX512 templates need to retain AVX512* only if we already
2209 know that EVEX encoding will be needed. */
2212 {
2214 {
2218 }
2219 /* need_evex_encoding(t) isn't reliable before operands were
2220 parsed. */
2222 {
2225 }
2226 }
2228 /* Dual non-APX/APX templates need massaging from what APX_F() in the
2229 opcode table has produced. While the direct transformation of the
2230 incoming cpuid&(cpuid|APX_F) would be to cpuid&(cpuid) / cpuid&(APX_F)
2231 respectively, it's cheaper to move to just cpuid / cpuid&APX_F
2232 instead. */
2239 {
2240 /* These checks (verifying that APX_F() was properly used in the
2241 opcode table entry) make sure there's no need for an "else" to
2242 the "if()" below. */
2251 }
2252 }
2256 else
2260 {
2261 /* AVX and AVX2 present at the same time express an operand size
2262 dependency - strip AVX2 for the purposes here. The operand size
2263 dependent check occurs in check_vecOperands(). */
2270 }
2272 }
2274 static INLINE i386_operand_type
2276 {
2283 {
2286 /* Fall through. */
2289 /* Fall through. */
2295 }
2297 }
2299 static INLINE i386_operand_type
2301 {
2306 {
2309 /* Fall through. */
2312 /* Fall through. */
2318 }
2320 }
2322 static INLINE i386_operand_type
2324 {
2333 {
2336 /* Fall through. */
2339 /* Fall through. */
2345 }
2347 }
2349 static INLINE i386_operand_type
2351 {
2356 {
2359 /* Fall through. */
2362 /* Fall through. */
2368 }
2370 }
2374 };
2376 enum operand_type
2377 {
2378 reg,
2379 imm,
2380 disp,
2381 anymem
2382 };
2386 {
2388 {
2415 }
2418 }
2420 /* Return 1 if there is no conflict in 8bit/16bit/32bit/64bit/80bit size
2421 between operand GIVEN and opeand WANTED for instruction template T. */
2426 {
2435 /* Don't allow 64-bit (memory) operands outside of 64-bit
2436 mode, when they're used where a 64-bit GPR could also
2437 be used. Checking is needed for Intel Syntax only. */
2438 || (intel_syntax
2445 }
2447 /* Return 1 if there is no conflict in SIMD register between operand
2448 GIVEN and opeand WANTED for instruction template T. */
2453 {
2462 }
2464 /* Return 1 if there is no conflict in any size between operand GIVEN
2465 and opeand WANTED for instruction template T. */
2470 {
2478 /* For scalar opcode templates to allow register and memory
2479 operands at the same time, some special casing is needed
2480 here. Also for v{,p}broadcast*, {,v}pmov{s,z}*, and
2481 down-conversion vpmov*. */
2492 }
2494 /* Return value has MATCH_STRAIGHT set if there is no size conflict on any
2495 operands for instruction template T, and it has MATCH_REVERSE set if there
2496 is no size conflict on any operands for the template with operands reversed
2497 (and the template allows for reversing in the first place). */
2499 #define MATCH_STRAIGHT 1
2500 #define MATCH_REVERSE 2
2504 {
2507 /* Don't check non-absolute jump instructions. */
2512 /* Check memory and accumulator operand size. */
2514 {
2522 {
2525 }
2529 {
2532 }
2536 {
2539 }
2542 {
2545 }
2546 }
2551 /* Check reverse. */
2555 {
2558 /* For FMA4 and XOP insns VEX.W controls just the first two
2559 register operands. And APX_F insns just swap the two source operands,
2560 with the 3rd one being the destination. */
2580 }
2583 }
2587 i386_operand_type given)
2588 {
2608 mismatch:
2611 }
2613 /* If given types g0 and g1 are registers they must be of the same type
2614 unless the expected operand type register overlap is null.
2615 Intel syntax sized memory operands are also checked here. */
2619 i386_operand_type t0,
2620 i386_operand_type g1,
2621 i386_operand_type t1)
2622 {
2644 /* If expectations overlap in no more than a single size, all is fine. */
2658 }
2662 {
2672 }
2676 {
2682 else
2684 }
2688 {
2690 }
2694 {
2696 }
2700 {
2702 }
2706 {
2708 }
2712 {
2713 #ifndef BFD64
2715 #else
2717 #endif
2722 {
2723 #ifndef BFD64
2725 #else
2727 #endif
2731 {
2732 #ifdef BFD64
2738 #endif
2741 }
2745 {
2754 /* Return 0 if NUM isn't properly aligned. */
2758 /* Check if NUM will fit in 8bit after shift. */
2760 }
2764 {
2765 /* Despite the name, check for imm3 if we're dealing with EVEX. */
2768 }
2770 static i386_operand_type
2772 {
2773 i386_operand_type t;
2779 {
2780 /* This code is disabled on the 486 because all the Imm1 forms
2781 in the opcode table are slower on the i486. They're the
2782 versions with the implicitly specified single-position
2783 displacement, which has another syntax if you really want to
2784 use that form. */
2791 }
2793 {
2801 }
2803 {
2808 }
2810 {
2815 }
2817 {
2821 }
2826 }
2828 static offsetT
2830 {
2831 addressT mask;
2834 {
2837 #ifdef BFD64
2839 #endif
2842 }
2849 }
2852 {
2854 }
2856 enum PREFIX_GROUP
2857 {
2859 PREFIX_LOCK,
2860 PREFIX_REP,
2861 PREFIX_DS,
2862 PREFIX_OTHER
2863 };
2865 /* Returns
2866 a. PREFIX_EXIST if attempting to add a prefix where one from the
2867 same class already exists.
2868 b. PREFIX_LOCK if lock prefix is added.
2869 c. PREFIX_REP if rep/repne prefix is added.
2870 d. PREFIX_DS if ds prefix is added.
2871 e. PREFIX_OTHER if other prefix is added.
2872 */
2874 static enum PREFIX_GROUP
2876 {
2882 {
2889 }
2890 else
2891 {
2893 {
2899 /* Fall through. */
2930 }
2933 }
2936 {
2940 }
2941 else
2945 }
2947 static void
2949 {
2953 {
2957 }
2960 {
2964 }
2969 }
2971 static void
2973 {
2975 }
2977 static void
2979 {
2984 }
2986 static void
2988 {
2994 }
2996 static void
2998 {
2999 /* Find out if register prefixing is specified. */
3004 {
3012 else
3015 }
3019 allow_naked_reg = (syntax_flag
3021 else
3025 }
3027 static void
3029 {
3031 }
3033 static void
3035 {
3037 }
3039 static void
3041 {
3046 {
3049 }
3050 else
3051 {
3054 }
3059 {
3069 else
3072 }
3073 else
3077 }
3079 static void
3081 i386_cpu_flags new_flag ATTRIBUTE_UNUSED)
3082 {
3083 /* Intel MCU is only supported on ELF. */
3084 #ifdef OBJ_ELF
3088 {
3089 /* Use cpu_arch_name if it is set in md_parse_option. Otherwise
3090 use default_arch. */
3094 }
3096 /* If we are targeting Intel MCU, we must enable it. */
3102 #endif
3103 }
3105 static void
3107 {
3111 else
3113 }
3116 {
3120 {
3123 }
3126 }
3129 {
3130 i386_cpu_flags flags
3134 {
3137 }
3139 cpu_arch_isa_flags
3141 }
3143 static void
3145 {
3147 {
3151 i386_cpu_flags flags;
3152 i386_cpu_flags isa_flags;
3168 {
3170 input_line_pointer++;
3172 }
3178 {
3184 else
3200 }
3203 {
3207 {
3209 restore_bad:
3213 }
3217 {
3222 };
3228 }
3246 }
3249 {
3252 else
3253 {
3268 }
3269 }
3272 {
3275 {
3277 {
3281 {
3285 }
3288 {
3292 }
3307 }
3317 {
3322 #ifdef SVR4_COMMENT_CHARS
3324 #else
3326 #endif
3327 {
3330 {
3338 }
3340 }
3341 /* Fall through. */
3345 }
3349 }
3350 }
3353 {
3354 /* Disable an ISA extension. */
3358 {
3367 }
3368 }
3371 {
3374 }
3379 {
3387 {
3390 }
3393 }
3396 }
3398 enum bfd_architecture
3400 {
3402 {
3406 }
3407 else
3409 }
3411 unsigned long
3413 {
3415 {
3418 else
3420 }
3423 {
3425 {
3429 }
3430 else
3432 }
3433 else
3435 }
3436 \f
3439 static void
3441 {
3445 {
3448 }
3449 else
3451 }
3453 void
3455 {
3456 /* Make sure possible padding space is clear. */
3459 /* Initialize op_hash hash table. */
3462 {
3469 }
3471 /* Initialize reg_hash hash table. */
3473 {
3478 {
3480 {
3483 {
3486 }
3488 {
3489 /* There's no point inserting st(<N>) in the hash table, as
3490 parentheses aren't included in register_chars[] anyway. */
3494 }
3499 {
3503 }
3510 }
3514 }
3515 }
3517 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
3518 {
3523 {
3525 {
3529 }
3531 {
3535 }
3536 #ifdef SVR4_COMMENT_CHARS
3539 #endif
3543 }
3553 }
3556 {
3557 #if defined (OBJ_COFF) && defined (TE_PE)
3559 #else
3561 #endif
3563 #ifdef OBJ_ELF
3566 #endif
3567 }
3568 else
3569 {
3572 }
3574 /* NB: FUSED_JCC_PADDING frag must have sufficient room so that it
3575 can be turned into BRANCH_PREFIX frag. */
3578 }
3580 void
3582 {
3585 }
3587 void
3589 {
3592 }
3593 \f
3594 #ifdef DEBUG386
3596 /* Debugging routines for md_assemble. */
3602 static void
3604 {
3623 {
3641 }
3642 }
3644 static void
3646 {
3651 };
3668 {
3672 }
3673 }
3675 static void
3677 {
3682 {
3686 }
3688 {
3692 }
3693 }
3695 static void
3697 {
3702 }
3704 static struct type_name
3705 {
3706 i386_operand_type mask;
3708 }
3710 {
3745 };
3747 static void
3749 {
3751 i386_operand_type a;
3754 {
3758 }
3760 }
3763 \f
3764 static bfd_reloc_code_real_type
3768 bfd_reloc_code_real_type other)
3769 {
3771 {
3776 {
3800 }
3802 #ifdef OBJ_ELF
3804 {
3808 {
3811 }
3812 }
3813 #endif
3815 /* Sign-checking 4-byte relocations in 16-/32-bit code is pointless. */
3825 size);
3833 else
3836 }
3839 {
3843 {
3848 }
3850 }
3851 else
3852 {
3855 {
3857 }
3858 else
3860 {
3865 }
3868 }
3871 }
3873 #ifdef OBJ_ELF
3874 /* Here we decide which fixups can be adjusted to make them relative to
3875 the beginning of the section instead of the symbol. Basically we need
3876 to make sure that the dynamic relocations are done correctly, so in
3877 some cases we force the original symbol to be used. */
3879 int
3881 {
3882 /* Don't adjust pc-relative references to merge sections in 64-bit
3883 mode. */
3889 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
3890 and changed later by validate_fix. */
3895 /* Adjust_reloc_syms doesn't know about the GOT. Need to keep symbol
3896 for size relocations. */
3934 /* Resolve PLT32 relocation against local symbol to section only for
3935 PC-relative relocations. */
3940 }
3941 #endif
3945 {
3952 }
3954 static int
3956 {
3957 /* Note that the value returned is meaningful only for opcodes with (memory)
3958 operands, hence the code here is free to improperly handle opcodes that
3959 have no operands (for better performance and smaller code). */
3965 {
3966 /* fclex, fdecstp, fdisi, femms, feni, fincstp, finit, fsetpm, and
3967 the fs segment override prefix not currently handled because no
3968 call path can make opcodes without operands get here */
3987 {
3989 {
3995 }
3996 }
4002 }
4005 }
4009 {
4014 /* Dual VEX/EVEX templates need stripping one of the possible variants. */
4016 {
4020 {
4022 {
4026 }
4027 else
4028 {
4034 else
4036 }
4037 }
4045 {
4048 else
4050 }
4051 }
4053 /* For CCMP and CTEST the template has EVEX.SCC in base_opcode. Move it out of
4054 there, to then adjust base_opcode to obtain its normal meaning. */
4056 {
4057 /* Get EVEX.SCC value from the lower 4 bits of base_opcode. */
4060 }
4062 /* For CMOVcc having undergone NDD-to-legacy optimization with its source
4063 operands being swapped, we need to invert the encoded condition. */
4067 /* Note that for pseudo prefixes this produces a length of 1. But for them
4068 the length isn't interesting at all. */
4074 }
4076 /* Build the VEX prefix. */
4078 static void
4080 {
4085 /* Check register specifier. */
4087 {
4088 register_specifier =
4091 }
4092 else
4095 /* Use 2-byte VEX prefix by swapping destination and source operand
4096 if there are more than 1 register operand. */
4105 {
4122 }
4124 /* Use 2-byte VEX prefix by swapping commutative source operands if there
4125 are no memory operands and at least 3 register ones. */
4131 /* .commutative aliases .staticrounding; disambiguate. */
4138 {
4155 }
4163 else
4164 {
4167 /* Determine vector length from the last multi-length vector
4168 operand. */
4174 {
4177 }
4178 }
4180 /* Check the REX.W bit and VEXW. */
4185 else
4188 /* Use 2-byte VEX prefix if possible. */
4193 {
4194 /* 2-byte VEX prefix. */
4200 /* Check the REX.R bit. */
4206 }
4207 else
4208 {
4209 /* 3-byte VEX prefix. */
4213 {
4227 }
4229 /* The high 3 bits of the second VEX byte are 1's compliment
4230 of RXB bits from REX. */
4239 }
4240 }
4244 {
4246 }
4248 /* We can use this function only when the current encoding is evex. */
4251 {
4255 }
4259 {
4262 }
4264 static unsigned int
4266 {
4283 {
4287 /* Fall through. */
4291 /* Fall through. */
4295 /* Fall through. */
4303 /* Fall through. */
4306 }
4313 {
4316 }
4324 else
4332 }
4334 /* Build the EVEX prefix. */
4336 static void
4338 {
4343 /* Check register specifier. */
4345 {
4351 /* The upper 16 registers are encoded in the fourth byte of the
4352 EVEX prefix. */
4356 }
4357 else
4358 {
4361 /* Encode upper 16 vector index register in the fourth byte of
4362 the EVEX prefix. */
4365 else
4367 }
4369 /* 4 byte EVEX prefix. */
4373 /* The high 3 bits of the second EVEX byte are 1's compliment of RXB
4374 bits from REX. */
4381 /* The fifth bit of the second EVEX byte is 1's compliment of the
4382 REX_R bit in VREX. */
4385 else
4389 {
4390 /* When all operands are registers, the REX_X bit in REX is not
4391 used. We reuse it to encode the upper 16 registers, which is
4392 indicated by the REX_B bit in VREX. The REX_X bit is encoded
4393 as 1's compliment. */
4395 {
4398 }
4399 }
4401 /* EVEX instructions shouldn't need the REX prefix. */
4405 /* Check the REX.W bit and VEXW. */
4410 else
4414 {
4417 /* Determine vector length from the last multi-length vector operand. */
4422 {
4424 {
4427 }
4429 {
4432 }
4434 {
4437 }
4440 {
4442 {
4454 }
4456 }
4457 }
4461 }
4465 /* The third byte of the EVEX prefix. */
4471 /* The fourth byte of the EVEX prefix. */
4472 /* The zeroing-masking bit. */
4476 /* Don't always set the broadcast bit if there is no RC. */
4478 {
4479 /* Encode the vector length. */
4483 {
4498 {
4501 }
4502 /* Fall through. */
4506 }
4508 /* Encode the broadcast bit. */
4511 }
4514 else
4519 }
4521 /* Build (2 bytes) rex2 prefix.
4522 | D5h |
4523 | m | R4 X4 B4 | W R X B |
4525 Rex2 reuses i.vex as they both encode i.tm.opcode_space in their prefixes.
4526 */
4527 static void
4529 {
4532 /* For the W R X B bits, the variables of rex prefix will be reused. */
4536 }
4538 /* Build the EVEX prefix (4-byte) for evex insn
4539 | 62h |
4540 | `R`X`B`R' | B'mmm |
4541 | W | v`v`v`v | `x' | pp |
4542 | z| L'L | b | `v | aaa |
4543 */
4544 static bool
4546 {
4547 /* To mimic behavior for legacy insns, transform use of DATA16 and REX64 into
4548 their embedded-prefix representations. */
4550 {
4552 {
4554 {
4559 }
4562 }
4564 {
4566 {
4569 }
4572 }
4573 }
4581 {
4584 }
4589 /* Encode the NDD bit of the instruction promoted from the legacy
4590 space. ZU shares the same bit with NDD. */
4595 /* Encode SCC and oszc flags bits. */
4597 {
4598 /* The default value of vvvv is 1111 and needs to be cleared. */
4601 /* ND and aaa bits shold be 0. */
4603 /* The default value of V' is 1 and needs to be cleared. */
4605 }
4607 /* Encode the NF bit. */
4612 }
4615 {
4616 /* Note that legacy encodings have at most 2 non-immediate operands. */
4620 /* Respect a user-specified REX prefix. */
4623 /* For 8 bit RegRex64 registers without a prefix, we need an empty rex prefix. */
4631 /* For REX/REX2/EVEX prefix instructions, we need to convert old registers
4632 (AL, CL, DL and BL) to new ones (AXL, CXL, DXL and BXL) and reject AH,
4633 CH, DH and BH. */
4635 {
4637 {
4638 /* Look for 8 bit operand that uses old registers. */
4641 {
4642 /* In case it is "hi" register, give up. */
4649 /* Otherwise it is equivalent to the extended register.
4650 Since the encoding doesn't change this is merely
4651 cosmetic cleanup for debug output. */
4653 }
4654 }
4655 }
4658 {
4659 /* Check if we can add a REX_OPCODE byte. Look for 8 bit operand
4660 that uses legacy register. If it is "hi" register, don't add
4661 rex and rex2 prefix. */
4669 {
4673 }
4677 }
4680 {
4681 /* Most prefixes are not permitted with JMPABS. */
4683 {
4685 {
4690 }
4692 {
4696 }
4697 }
4700 /* The individual REX.RXBW bits got consumed. */
4703 }
4706 }
4708 static void
4710 {
4713 /* These AMD 3DNow! and SSE2 instructions have an opcode suffix
4714 which is coded in the same place as an 8-bit immediate field
4715 would be. Here we fake an 8-bit immediate operand from the
4716 opcode suffix stored in tm.extension_opcode.
4718 AVX instructions also use this encoding, for some of
4719 3 argument instructions. */
4733 }
4736 static int
4738 {
4740 {
4759 {
4763 }
4765 {
4769 }
4771 }
4772 }
4774 /* Helper for optimization (running ahead of process_suffix()), to make sure we
4775 convert only well-formed insns. @OP is the sized operand to cross check
4776 against (typically a register). Checking against a single operand typically
4777 suffices, as match_template() has already honored CheckOperandSize. */
4780 {
4786 }
4788 /* Encode aligned vector move as unaligned vector move. */
4790 static void
4792 {
4794 {
4797 /* movaps/movapd/vmovaps/vmovapd. */
4804 /* movdqa/vmovdqa/vmovdqa64/vmovdqa32. */
4811 }
4812 }
4814 /* Try the shortest encoding by shortening operand size. */
4816 static void
4818 {
4822 {
4823 /* Optimize: -O:
4824 lea symbol, %rN -> mov $symbol, %rN
4825 lea (%rM), %rN -> mov %rM, %rN
4826 lea (,%rM,1), %rN -> mov %rM, %rN
4828 and in 32-bit mode for 16-bit addressing
4830 lea (%rM), %rN -> movzx %rM, %rN
4832 and in 64-bit mode zap 32-bit addressing in favor of using a
4833 32-bit (or less) destination.
4834 */
4836 {
4840 }
4843 {
4844 /* Handle:
4845 lea symbol, %rN -> mov $symbol, %rN
4846 */
4848 {
4849 /* Don't transform a relocation to a 16-bit one. */
4857 {
4862 else
4863 {
4866 }
4867 }
4868 else
4869 {
4870 /* Subject to further optimization below. */
4875 }
4876 }
4877 /* Outside of 64-bit mode address and operand sizes have to match if
4878 a relocation is involved, as otherwise we wouldn't (currently) or
4879 even couldn't express the relocation correctly. */
4887 /* In 16-bit mode converting LEA with 16-bit addressing and a 32-bit
4888 destination is going to grow encoding size. */
4894 else
4895 {
4900 else
4906 /* NB: Add () to !i.prefix[ADDR_PREFIX] to silence
4907 GCC 5. */
4910 }
4915 {
4918 }
4919 }
4924 else
4925 {
4926 /* Handle:
4927 lea (%rM), %rN -> mov %rM, %rN
4928 lea (,%rM,1), %rN -> mov %rM, %rN
4929 lea (%rM), %rN -> movzx %rM, %rN
4930 */
4939 else
4944 {
4949 }
4950 else
4959 }
4966 }
4978 {
4979 /* Optimize: -Os:
4980 test $imm7, %r64/%r32/%r16 -> test $imm7, %r8
4981 ctest<cc> $imm7, %r64/%r32/%r16 -> ctest<cc> $imm7, %r8
4982 */
4988 {
4990 /* Squash the suffix. */
4992 /* Convert to byte registers. 8-bit registers are special,
4993 RegRex64 and non-RegRex* each have 8 registers. */
4995 /* 32 (or 40) 8-bit registers. */
4998 /* 32 (or 40) 8-bit registers + 32 16-bit registers. */
5000 else
5001 /* 32 (or 40) 8-bit registers + 32 16-bit registers
5002 + 32 32-bit registers. */
5005 /* In 64-bit mode, the following byte registers cannot be accessed
5006 if using the Rex and Rex2 prefix: AH, BH, CH, DH */
5010 }
5011 }
5039 {
5040 /* Optimize: -O:
5041 andq $imm31, %r64 -> andl $imm31, %r32
5042 andq $imm7, %r64 -> andl $imm7, %r32
5043 testq $imm31, %r64 -> testl $imm31, %r32
5044 xorq %r64, %r64 -> xorl %r32, %r32
5045 clrq %r64 -> clrl %r32
5046 subq %r64, %r64 -> subl %r32, %r32
5047 movq $imm31, %r64 -> movl $imm31, %r32
5048 movq $imm32, %r64 -> movl $imm32, %r32
5049 */
5052 {
5056 }
5057 else
5058 {
5061 }
5065 {
5066 /* Handle
5067 movq $imm31, %r64 -> movl $imm31, %r32
5068 movq $imm32, %r64 -> movl $imm32, %r32
5069 */
5074 {
5075 /* Handle
5076 movq $imm31, %r64 -> movl $imm31, %r32
5077 */
5082 }
5083 }
5084 }
5090 {
5091 /* Optimize: -O:
5092 xorb %rNb, %rNb, %rMb -> xorl %rMd, %rMd
5093 xorw %rNw, %rNw, %rMw -> xorl %rMd, %rMd
5094 xorl %rNd, %rNd, %rMd -> xorl %rMd, %rMd
5095 xorq %rN, %rN, %rM -> xorl %rMd, %rMd
5096 subb %rNb, %rNb, %rMb -> subl %rMd, %rMd
5097 subw %rNw, %rNw, %rMw -> subl %rMd, %rMd
5098 subl %rNd, %rNd, %rMd -> subl %rMd, %rMd
5099 subq %rN, %rN, %rM -> subl %rMd, %rMd
5100 */
5112 }
5114 && !optimize_for_space
5119 {
5120 /* Optimize: -O2:
5121 andb %rN, %rN -> testb %rN, %rN
5122 andw %rN, %rN -> testw %rN, %rN
5123 andq %rN, %rN -> testq %rN, %rN
5124 orb %rN, %rN -> testb %rN, %rN
5125 orw %rN, %rN -> testw %rN, %rN
5126 orq %rN, %rN -> testq %rN, %rN
5128 and outside of 64-bit mode
5130 andl %rN, %rN -> testl %rN, %rN
5131 orl %rN, %rN -> testl %rN, %rN
5132 */
5134 }
5141 {
5142 /* Optimize: -O:
5143 shlb $1, %rN -> addb %rN, %rN
5144 shlw $1, %rN -> addw %rN, %rN
5145 shll $1, %rN -> addl %rN, %rN
5146 shlq $1, %rN -> addq %rN, %rN
5148 shlb $1, %rN, %rM -> addb %rN, %rN, %rM
5149 shlw $1, %rN, %rM -> addw %rN, %rN, %rM
5150 shll $1, %rN, %rM -> addl %rN, %rN, %rM
5151 shlq $1, %rN, %rM -> addq %rN, %rN, %rM
5152 */
5157 else
5158 {
5159 /* Legacy form with omitted shift count operand. */
5162 }
5165 }
5171 {
5172 /* Optimize: -O:
5173 btw $n, %rN -> btl $n, %rN (outside of 16-bit mode, n < 16)
5174 btq $n, %rN -> btl $n, %rN (in 64-bit mode, n < 32, N < 8)
5175 btl $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
5177 With <BT> one of bts, btr, and bts also:
5178 <BT>w $n, %rN -> btl $n, %rN (in 32-bit mode, n < 16)
5179 <BT>l $n, %rN -> btw $n, %rN (in 16-bit mode, n < 16)
5180 */
5182 {
5190 /* Fall through. */
5200 }
5201 }
5208 {
5209 /* Optimize: -O2:
5210 cfcmov<cc> %rM, %rN, %rN -> cmov<cc> %rM, %rN
5211 cfcmov<cc> %rM, %rN, %rM -> cmov<!cc> %rN, %rM
5212 cfcmov<cc> %rN, %rN, %rN -> nop %rN
5213 */
5215 {
5219 }
5229 /* While at it, convert to NOP if all three regs match. */
5231 {
5235 }
5236 }
5255 {
5256 /* Optimize: -O1:
5257 VOP, one of vandnps, vandnpd, vxorps, vxorpd, vpsubb, vpsubd,
5258 vpsubq and vpsubw:
5259 EVEX VOP %zmmM, %zmmM, %zmmN
5260 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
5261 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
5262 EVEX VOP %ymmM, %ymmM, %ymmN
5263 -> VEX VOP %xmmM, %xmmM, %xmmN (M and N < 16)
5264 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
5265 VEX VOP %ymmM, %ymmM, %ymmN
5266 -> VEX VOP %xmmM, %xmmM, %xmmN
5267 VOP, one of vpandn and vpxor:
5268 VEX VOP %ymmM, %ymmM, %ymmN
5269 -> VEX VOP %xmmM, %xmmM, %xmmN
5270 VOP, one of vpandnd and vpandnq:
5271 EVEX VOP %zmmM, %zmmM, %zmmN
5272 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
5273 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
5274 EVEX VOP %ymmM, %ymmM, %ymmN
5275 -> VEX vpandn %xmmM, %xmmM, %xmmN (M and N < 16)
5276 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
5277 VOP, one of vpxord and vpxorq:
5278 EVEX VOP %zmmM, %zmmM, %zmmN
5279 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
5280 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
5281 EVEX VOP %ymmM, %ymmM, %ymmN
5282 -> VEX vpxor %xmmM, %xmmM, %xmmN (M and N < 16)
5283 -> EVEX VOP %xmmM, %xmmM, %xmmN (M || N >= 16) (-O2)
5284 VOP, one of kxord and kxorq:
5285 VEX VOP %kM, %kM, %kN
5286 -> VEX kxorw %kM, %kM, %kN
5287 VOP, one of kandnd and kandnq:
5288 VEX VOP %kM, %kM, %kN
5289 -> VEX kandnw %kM, %kM, %kN
5290 */
5292 {
5294 {
5300 }
5303 else
5305 }
5307 {
5310 }
5311 else
5316 {
5319 }
5320 }
5333 {
5334 /* Optimize: -O1:
5335 VOP, one of vmovdqa32, vmovdqa64, vmovdqu8, vmovdqu16,
5336 vmovdqu32 and vmovdqu64:
5337 EVEX VOP %xmmM, %xmmN
5338 -> VEX vmovdqa|vmovdqu %xmmM, %xmmN (M and N < 16)
5339 EVEX VOP %ymmM, %ymmN
5340 -> VEX vmovdqa|vmovdqu %ymmM, %ymmN (M and N < 16)
5341 EVEX VOP %xmmM, mem
5342 -> VEX vmovdqa|vmovdqu %xmmM, mem (M < 16)
5343 EVEX VOP %ymmM, mem
5344 -> VEX vmovdqa|vmovdqu %ymmM, mem (M < 16)
5345 EVEX VOP mem, %xmmN
5346 -> VEX mvmovdqa|vmovdquem, %xmmN (N < 16)
5347 EVEX VOP mem, %ymmN
5348 -> VEX vmovdqa|vmovdqu mem, %ymmN (N < 16)
5349 VOP, one of vpand, vpandn, vpor, vpxor:
5350 EVEX VOP{d,q} %xmmL, %xmmM, %xmmN
5351 -> VEX VOP %xmmL, %xmmM, %xmmN (L, M, and N < 16)
5352 EVEX VOP{d,q} %ymmL, %ymmM, %ymmN
5353 -> VEX VOP %ymmL, %ymmM, %ymmN (L, M, and N < 16)
5354 EVEX VOP{d,q} mem, %xmmM, %xmmN
5355 -> VEX VOP mem, %xmmM, %xmmN (M and N < 16)
5356 EVEX VOP{d,q} mem, %ymmM, %ymmN
5357 -> VEX VOP mem, %ymmM, %ymmN (M and N < 16)
5358 */
5362 {
5363 /* Since the VEX prefix has 2 or 3 bytes, the EVEX prefix
5364 has 4 bytes, EVEX Disp8 has 1 byte and VEX Disp32 has 4
5365 bytes, we choose EVEX Disp8 over VEX Disp32. */
5374 {
5377 }
5381 }
5388 /* VPAND, VPOR, and VPXOR are commutative. */
5399 }
5408 {
5409 /* Optimize: -Os:
5410 pcmpeqq %xmmN, %xmmN -> pcmpeqd %xmmN, %xmmN
5411 vpcmpeqq %xmmN, %xmmN, %xmmM -> vpcmpeqd %xmmN, %xmmN, %xmmM (N < 8)
5412 vpcmpeqq %ymmN, %ymmN, %ymmM -> vpcmpeqd %ymmN, %ymmN, %ymmM (N < 8)
5413 */
5416 }
5425 {
5426 /* Optimize: -O:
5427 pcmpgt[bwd] %mmN, %mmN -> pxor %mmN, %mmN
5428 pcmpgt[bwdq] %xmmN, %xmmN -> pxor %xmmN, %xmmN
5429 vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmmN, %xmmN, %xmmM (N < 8)
5430 vpcmpgt[bwdq] %xmmN, %xmmN, %xmmM -> vpxor %xmm0, %xmm0, %xmmM (N > 7)
5431 vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymmN, %ymmN, %ymmM (N < 8)
5432 vpcmpgt[bwdq] %ymmN, %ymmN, %ymmM -> vpxor %ymm0, %ymm0, %ymmM (N > 7)
5433 */
5437 {
5439 {
5449 }
5452 }
5453 }
5461 {
5462 /* Optimize: -O:
5463 psllw $1, %mmxN -> paddw %mmxN, %mmxN
5464 psllw $1, %xmmN -> paddw %xmmN, %xmmN
5465 vpsllw $1, %xmmN, %xmmM -> vpaddw %xmmN, %xmmN, %xmmM
5466 vpsllw $1, %ymmN, %ymmM -> vpaddw %ymmN, %ymmN, %ymmM
5467 vpsllw $1, %zmmN, %zmmM -> vpaddw %zmmN, %zmmN, %zmmM
5469 pslld $1, %mmxN -> paddd %mmxN, %mmxN
5470 pslld $1, %xmmN -> paddd %xmmN, %xmmN
5471 vpslld $1, %xmmN, %xmmM -> vpaddd %xmmN, %xmmN, %xmmM
5472 vpslld $1, %ymmN, %ymmM -> vpaddd %ymmN, %ymmN, %ymmM
5473 vpslld $1, %zmmN, %zmmM -> vpaddd %zmmN, %zmmN, %zmmM
5475 psllq $1, %xmmN -> paddq %xmmN, %xmmN
5476 vpsllq $1, %xmmN, %xmmM -> vpaddq %xmmN, %xmmN, %xmmM
5477 vpsllq $1, %ymmN, %ymmM -> vpaddq %ymmN, %ymmN, %ymmM
5478 vpsllq $1, %zmmN, %zmmM -> vpaddq %zmmN, %zmmN, %zmmM
5479 */
5482 else
5483 {
5486 }
5493 }
5502 {
5503 /* Optimize: -Os:
5504 vpbroadcastq %xmmN, %xmmM -> vpunpcklqdq %xmmN, %xmmN, %xmmM (N < 8)
5505 */
5516 }
5521 {
5522 /* Optimize: -O:
5523 pextrd $0, %xmmN, ... -> movd %xmmN, ...
5524 pextrq $0, %xmmN, ... -> movq %xmmN, ...
5525 vpextrd $0, %xmmN, ... -> vmovd %xmmN, ...
5526 vpextrq $0, %xmmN, ... -> vmovq %xmmN, ...
5527 */
5534 else
5535 {
5540 }
5547 }
5552 {
5553 /* Optimize: -O:
5554 extractps $0, %xmmN, %rM -> movd %xmmN, %rM
5555 extractps $0, %xmmN, mem -> movss %xmmN, mem
5556 vextractps $0, %xmmN, %rM -> vmovd %xmmN, %rM
5557 vextractps $0, %xmmN, mem -> vmovss %xmmN, mem
5558 */
5564 else
5565 {
5568 }
5575 }
5580 {
5581 /* Optimize: -O:
5582 vextractf128 $0, %ymmN, %xmmM -> vmovaps %xmmN, %xmmM
5583 vextractf128 $0, %ymmN, mem -> vmovups %xmmN, mem
5584 vextractf32x4 $0, %[yz]mmN, %xmmM -> vmovaps %xmmN, %xmmM
5585 vextractf32x4 $0, %[yz]mmN, mem -> vmovups %xmmN, mem
5586 vextractf64x2 $0, %[yz]mmN, %xmmM -> vmovapd %xmmN, %xmmM
5587 vextractf64x2 $0, %[yz]mmN, mem -> vmovupd %xmmN, mem
5588 vextractf32x8 $0, %zmmN, %ymmM -> vmovaps %ymmN, %ymmM
5589 vextractf32x8 $0, %zmmN, mem -> vmovups %ymmN, mem
5590 vextractf64x4 $0, %zmmN, %ymmM -> vmovapd %ymmN, %ymmM
5591 vextractf64x4 $0, %zmmN, mem -> vmovupd %ymmN, mem
5592 vextracti128 $0, %ymmN, %xmmM -> vmovdqa %xmmN, %xmmM
5593 vextracti128 $0, %ymmN, mem -> vmovdqu %xmmN, mem
5594 vextracti32x4 $0, %[yz]mmN, %xmmM -> vmovdqa{,32} %xmmN, %xmmM
5595 vextracti32x4 $0, %[yz]mmN, mem -> vmovdqu{,32} %xmmN, mem
5596 vextracti64x2 $0, %[yz]mmN, %xmmM -> vmovdqa{,64} %xmmN, %xmmM
5597 vextracti64x2 $0, %[yz]mmN, mem -> vmovdqu{,64} %xmmN, mem
5598 vextracti32x8 $0, %zmmN, %ymmM -> vmovdqa{,32} %ymmN, %ymmM
5599 vextracti32x8 $0, %zmmN, mem -> vmovdqu{,32} %ymmN, mem
5600 vextracti64x4 $0, %zmmN, %ymmM -> vmovdqa{,64} %ymmN, %ymmM
5601 vextracti64x4 $0, %zmmN, mem -> vmovdqu{,64} %ymmN, mem
5602 */
5610 {
5613 }
5614 else
5618 {
5622 }
5623 else
5624 {
5627 else
5631 }
5641 }
5650 {
5651 /* Optimize: -O:
5652 insertps $0b....1111, %xmmN, %xmmM -> xorps %xmmM, %xmmM
5653 insertps $0b00000000, %xmmN, %xmmM -> movss %xmmN, %xmmM
5654 insertps $0b..001110, mem, %xmmN -> movss mem, %xmmN
5655 vinsertps $0b....1111, %xmmN, %xmmM, %xmmK -> vxorps %xmm?, %xmm?, %xmmK
5656 vinsertps $0b00000000, %xmmN, %xmmM, %xmmK -> vmovss %xmmN, %xmmM, %xmmK
5657 vinsertps $0b..001110, mem, %xmmN, %xmmN -> vmovss mem, %xmmN
5658 */
5661 {
5671 /* Switch from EVEX to VEX encoding if possible. Sadly we can't
5672 (always) tell use of the {evex} pseudo-prefix (which otherwise
5673 we'd like to respect) from use of %xmm16-%xmm31. */
5679 {
5682 }
5684 /* Switch from VEX3 to VEX2 encoding if possible. */
5688 {
5691 }
5692 }
5693 else
5694 {
5700 else
5701 {
5704 }
5708 }
5711 }
5712 }
5714 /* Check whether the promoted (to address size) register is usable as index
5715 register in ModR/M SIB addressing. */
5718 {
5722 {
5724 {
5728 }
5730 }
5733 /* No need to further check .dword here. */
5736 }
5738 /* Try to shorten {nf} encodings, by shortening operand size or switching to
5739 functionally identical encodings. */
5741 static void
5743 {
5751 {
5752 /* Optimize: -O:
5753 {nf} addw $0x80, ... -> {nf} subw $-0x80, ...
5754 {nf} addl $0x80, ... -> {nf} subl $-0x80, ...
5755 {nf} addq $0x80, ... -> {nf} subq $-0x80, ...
5757 {nf} subw $0x80, ... -> {nf} addw $-0x80, ...
5758 {nf} subl $0x80, ... -> {nf} addl $-0x80, ...
5759 {nf} subq $0x80, ... -> {nf} addq $-0x80, ...
5760 */
5773 }
5779 /* While for wider than byte operations immediates were suitably
5780 adjusted earlier on, 0xff in the byte case needs covering
5781 explicitly. */
5785 {
5786 /* Optimize: -O:
5787 {nf} add $1, ... -> {nf} inc ...
5788 {nf} add $-1, ... -> {nf} dec ...
5789 {nf} add $0xf...f, ... -> {nf} dec ...
5791 {nf} sub $1, ... -> {nf} dec ...
5792 {nf} sub $-1, ... -> {nf} inc ...
5793 {nf} sub $0xf...f, ... -> {nf} inc ...
5794 */
5805 }
5815 {
5816 /* Optimize: -O:
5817 {nf} rol $osz-1, ... -> {nf} ror $1, ...
5818 {nf} ror $osz-1, ... -> {nf} rol $1, ...
5819 */
5825 }
5830 /* optimize_imm() converts to sign-extended representation where
5831 possible (and input can also come with these specific numbers). */
5836 /* 16-bit 3-operand non-ZU forms need leaviong alone, to prevent
5837 zero-extension of the result. Unless, of course, both non-
5838 immediate operands match (which can be converted to the non-NDD
5839 form). */
5844 /* When merely optimizing for size, exclude cases where we'd convert
5845 from Imm8S to Imm8 encoding, thus not actually reducing size. */
5846 && (!optimize_for_space
5849 {
5850 /* Optimize: -O:
5851 {nf} imul $1<<N, ... -> {nf} shl $N, ...
5852 {nf} imulzu $1<<N, ... -> {nf} shl $N, ...
5853 */
5855 {
5862 }
5863 else
5864 {
5867 }
5873 {
5875 {
5876 /* Convert to non-NDD form. This is required for 16-bit insns
5877 (to prevent zero-extension) and benign for others. */
5880 }
5881 else
5883 }
5885 {
5886 /* Convert to NDD form, to effect zero-extension of the result. */
5891 }
5892 }
5900 /* 16-bit operand size has extra restrictions: If REX2 was needed,
5901 no size reduction would be possible. Plus 3-operand forms zero-
5902 extend the result, which can't be expressed with LEA. */
5906 /* %rsp can't be the index. */
5909 /* While %rbp, %r13, %r21, and %r29 can be made the index in order to
5910 avoid the otherwise necessary Disp8, if the other operand is also
5911 from that set and REX2 would be required to encode the insn, the
5912 resulting encoding would be no smaller than the EVEX one. */
5917 {
5918 /* Optimize: -Os:
5919 {nf} addw %N, %M -> leaw (%rM,%rN), %M
5920 {nf} addl %eN, %eM -> leal (%rM,%rN), %eM
5921 {nf} addq %rN, %rM -> leaq (%rM,%rN), %rM
5923 {nf} shlw $1, %N -> leaw (%rN,%rN), %N
5924 {nf} shll $1, %eN -> leal (%rN,%rN), %eN
5925 {nf} shlq $1, %rN -> leaq (%rN,%rN), %rN
5927 {nf} addl %eK, %eN, %eM -> leal (%rN,%rK), %eM
5928 {nf} addq %rK, %rN, %rM -> leaq (%rN,%rK), %rM
5930 {nf} shll $1, %eN, %eM -> leal (%rN,%rN), %eM
5931 {nf} shlq $1, %rN, %rM -> leaq (%rN,%rN), %rM
5932 */
5943 {
5946 }
5947 else
5948 {
5951 }
5953 {
5954 /* NB: No similar adjustment is needed when operand size is 32-bit. */
5957 }
5970 }
5977 /* Subtraction of -0x80 will end up smaller only if neither
5978 operand size nor REX/REX2 prefixes are needed. */
5986 /* 16-bit operand size has extra restrictions: If REX2 was needed,
5987 no size reduction would be possible. Plus 3-operand forms zero-
5988 extend the result, which can't be expressed with LEA. */
5992 {
5993 /* Optimize: -Os:
5994 {nf} addw $N, %M -> leaw N(%rM), %M
5995 {nf} addl $N, %eM -> leal N(%rM), %eM
5996 {nf} addq $N, %rM -> leaq N(%rM), %rM
5998 {nf} subw $N, %M -> leaw -N(%rM), %M
5999 {nf} subl $N, %eM -> leal -N(%rM), %eM
6000 {nf} subq $N, %rM -> leaq -N(%rM), %rM
6002 {nf} addl $N, %eK, %eM -> leal N(%rK), %eM
6003 {nf} addq $N, %rK, %rM -> leaq N(%rK), %rM
6005 {nf} subl $N, %eK, %eM -> leal -N(%rK), %eM
6006 {nf} subq $N, %rK, %rM -> leaq -N(%rK), %rM
6007 */
6017 {
6018 /* NB: No similar adjustment is needed when operand size is 32-bit. */
6020 }
6035 }
6041 /* %rsp can't be the index. */
6043 /* There's no reduction in size for 16-bit forms requiring Disp8 and
6044 REX2. */
6045 && (!optimize_for_space
6053 {
6054 /* Optimize: -O:
6055 For n one of 3, 5, or 9
6056 {nf} imulw $n, %N, %M -> leaw (%rN,%rN,n-1), %M
6057 {nf} imull $n, %eN, %eM -> leal (%rN,%rN,n-1), %eM
6058 {nf} imulq $n, %rN, %rM -> leaq (%rN,%rN,n-1), %rM
6060 {nf} imulw $n, %N -> leaw (%rN,%rN,s), %N
6061 {nf} imull $n, %eN -> leal (%rN,%rN,s), %eN
6062 {nf} imulq $n, %rN -> leaq (%rN,%rN,s), %rN
6063 */
6069 /* NB: No similar adjustment is needed when operand size is 32 bits. */
6088 }
6094 {
6096 {
6097 /* Optimize: -O:
6098 <OP> one of sal, sar, shl, shr:
6099 {nf} <OP> %cl, %rN -> <OP>x %{e,r}cx, %rN, %rN (N < 16)
6100 {nf} <OP> %cl, ..., %rN -> <OP>x %{e,r}cx, ..., %rN (no eGPR used)
6101 */
6104 /* NB: i.op[0].regs specifying %cl is good enough. */
6107 {
6113 }
6128 }
6132 {
6133 /* Optimize: -O:
6134 {nf} rol $I, %rN -> rorx $osz-I, %rN, %rN (I != osz-1, N < 16)
6135 {nf} rol $I, ..., %rN -> rorx $osz-I, ..., %rN (I != osz-1, no eGPR used)
6136 {nf} ror $I, %rN -> rorx $I, %rN, %rN (I != 1, N < 16)
6137 {nf} ror $I, ..., %rN -> rorx $I,..., %rN (I != 1, no eGPR used)
6138 NB: rol -> ror transformation for I == osz-1 was already handled above.
6139 NB2: ror with an immediate of 1 uses a different base opcode.
6140 */
6142 {
6147 }
6163 }
6169 {
6170 /* Optimize: -O:
6171 {nf} mul %edx -> mulx %eax, %eax, %edx
6172 {nf} mul %rdx -> mulx %rax, %rax, %rdx
6173 */
6178 /* NB: %eax is good enough also for 64-bit operand size. */
6192 }
6193 }
6194 }
6196 static void
6198 {
6206 }
6208 /* Return non-zero for load instruction. */
6210 static int
6212 {
6218 {
6219 /* Anysize insns: lea, invlpg, clflush, prefetch*, bndmk, bndcl, bndcu,
6220 bndcn, bndstx, bndldx, clflushopt, clwb, cldemote. */
6224 /* pop. */
6227 }
6230 {
6231 /* popf, popa. */
6236 /* movs, cmps, lods, scas. */
6240 /* outs, xlatb. */
6244 /* NB: For AMD-specific insns with implicit memory operands,
6245 they're intentionally not covered. */
6246 }
6248 /* No memory operand. */
6253 {
6256 }
6258 {
6259 /* test, not, neg, mul, imul, div, idiv. */
6263 /* inc, dec. */
6267 /* add, or, adc, sbb, and, sub, xor, cmp. */
6271 /* rol, ror, rcl, rcr, shl/sal, shr, sar. */
6276 /* Check for x87 instructions. */
6278 {
6279 /* Skip fst, fstp, fstenv, fstcw. */
6287 /* Skip fisttp, fist, fistp, fstp. */
6295 /* Skip fisttp, fst, fstp, fsave, fstsw. */
6304 /* Skip fisttp, fist, fistp, fbstp, fistp. */
6314 }
6315 }
6317 {
6318 /* bt, bts, btr, btc. */
6323 /* cmpxchg8b, cmpxchg16b, xrstors, vmptrld. */
6330 /* fxrstor, ldmxcsr, xrstor. */
6337 /* lgdt, lidt, lmsw. */
6343 }
6347 /* Check fake imm8 operand and 3 source operands. */
6351 dest--;
6353 /* add, or, adc, sbb, and, sub, xor, cmp, test, xchg. */
6362 /* Check for load instruction. */
6365 }
6367 /* Output lfence, 0xfaee8, after instruction. */
6369 static void
6371 {
6373 {
6374 /* There are also two REP string instructions that require
6375 special treatment. Specifically, the compare string (CMPS)
6376 and scan string (SCAS) instructions set EFLAGS in a manner
6377 that depends on the data being compared/scanned. When used
6378 with a REP prefix, the number of iterations may therefore
6379 vary depending on this data. If the data is a program secret
6380 chosen by the adversary using an LVI method,
6381 then this data-dependent behavior may leak some aspect
6382 of the secret. */
6385 {
6388 }
6393 }
6394 }
6396 /* Output lfence, 0xfaee8, before instruction. */
6398 static void
6400 {
6408 {
6409 /* Insert lfence before indirect branch if needed. */
6418 {
6419 /* Indirect branch via register. Don't insert lfence with
6420 -mlfence-after-load=yes. */
6424 }
6427 {
6431 }
6432 else
6436 {
6441 }
6448 }
6450 /* Output or/not/shl and lfence before near ret. */
6453 {
6455 {
6460 }
6462 /* Near ret ingore operand size override under CPU64. */
6468 {
6469 /* not: 0xf71424, may add prefix
6470 for operand size override or 64-bit code. */
6482 }
6483 else
6484 {
6489 {
6490 /* or: 0x830c2400, may add prefix
6491 for operand size override or 64-bit code. */
6494 }
6495 else
6496 {
6497 /* shl: 0xc1242400, may add prefix
6498 for operand size override or 64-bit code. */
6501 }
6505 }
6510 }
6511 }
6513 /* Shared helper for md_assemble() and s_insn(). */
6515 {
6525 }
6527 /* Helper for md_assemble() to decide whether to prepare for a possible 2nd
6528 parsing pass. Instead of introducing a rarely used new insn attribute this
6529 utilizes a common pattern between affected templates. It is deemed
6530 acceptable that this will lead to unnecessary pass 2 preparations in a
6531 limited set of cases. */
6533 {
6535 /* Note that all SSE2AVX templates have at least one operand. */
6544 }
6546 #ifdef OBJ_ELF
6547 static enum x86_tls_error_type
6549 {
6551 {
6553 /* Check GDesc access model:
6555 leal x@tlsdesc(%ebx), %reg32 --> Memory reg must be %ebx and
6556 SIB is not supported.
6557 */
6571 /* Check GD access model:
6573 leal foo@tlsgd(,%ebx,1), %eax --> Only this fixed format is supported.
6574 leal foo@tlsgd(%reg32), %eax --> Dest reg must be '%eax'
6575 Memory reg can't be %eax.
6576 */
6584 {
6591 }
6592 else
6593 {
6598 }
6602 /* Check LDM access model:
6604 leal foo@tlsldm(%reg32), %eax --> Dest reg must be '%eax'
6605 Memory reg can't be %eax and SIB
6606 is not supported.
6607 */
6623 /* Check GOTPC32 TLSDESC access model:
6625 --- LP64 mode ---
6626 leaq x@tlsdesc(%rip), %reg64 --> Memory reg must be %rip.
6628 --- X32 mode ---
6629 rex/rex2 leal x@tlsdesc(%rip), %reg32 --> Memory reg must be %rip.
6631 In X32 mode, gas will add rex/rex2 for it later, no need to check
6632 here.
6633 */
6642 {
6645 }
6652 /* Check GD access model:
6654 leaq foo@tlsgd(%rip), %rdi --> Only this fixed format is supported.
6655 */
6657 /* Check LD access model:
6659 leaq foo@tlsld(%rip), %rdi --> Only this fixed format is supported.
6660 */
6675 /* Check GOTIE access model:
6677 subl foo@gotntpoff(%reg1), %reg2
6678 movl foo@gotntpoff(%reg1), %reg2
6679 addl foo@gotntpoff(%reg1), %reg2
6681 Memory operand: SIB is not supported.
6682 */
6684 /* Check IE_32 access model:
6686 subl foo@gottpoff(%reg1), %reg2
6687 movl foo@gottpoff(%reg1), %reg2
6688 addl foo@gottpoff(%reg1), %reg2
6690 Memory operand: SIB is not supported.
6691 */
6712 /* Check IE access model:
6714 movl foo@indntpoff, %reg32 --> Mod == 00 && r/m == 5
6715 addl foo@indntpoff, %reg32 --> Mod == 00 && r/m == 5
6716 */
6731 /* Check GOTTPOFF access model:
6733 mov foo@gottpoff(%rip), %reg --> Memory Reg must be %rip.
6734 add foo@gottpoff(%rip), %reg --> Memory Reg must be %rip.
6735 add %reg1, foo@gottpoff(%rip), %reg2 --> Memory Reg must be %rip.
6736 add foo@gottpoff(%rip), %reg1, %reg2 --> Memory Reg must be %rip.
6737 */
6750 {
6753 }
6760 /* Check GDesc access model:
6762 call *x@tlscall(%eax) --> Memory reg must be %eax and
6763 SIB is not supported.
6764 */
6766 /* Check GDesc access model:
6768 call *x@tlscall(%rax) <--- LP64 mode.
6769 call *x@tlscall(%eax) <--- X32 mode.
6771 Only these fixed formats are supported.
6772 */
6784 /* This isn't a relocation. */
6789 }
6791 /* This relocation is OK. */
6793 }
6795 static void
6798 {
6805 {
6895 }
6896 }
6897 #endif
6899 /* This is the guts of the machine-dependent assembler. LINE points to a
6900 machine dependent instruction. This function is supposed to emit
6901 the frags/bytes it assembles to. */
6903 static void
6905 {
6916 /* Initialize globals. */
6918 retry:
6921 /* Suppress optimization when the last thing we saw may not have been
6922 a proper instruction (e.g. a stand-alone prefix or .byte). */
6926 /* First parse an instruction mnemonic & call i386_operand for the operands.
6927 We assume that the scrubber has arranged it so that line[0] is the valid
6928 start of a (possibly prefixed) mnemonic. */
6932 {
6936 {
6940 /* No point in trying a 2nd pass - it'll only find the same suffix
6941 again. */
6944 }
6946 }
6948 /* NB: LINE may be change to be the same as XSTRDUP_COPY. */
6950 {
6951 /* Make a copy of the full line in case we need to retry. */
6954 }
6961 {
6964 }
6966 /* Now we've parsed the mnemonic into a set of templates, and have the
6967 operands at hand. */
6969 /* All Intel opcodes have reversed operands except for "bound", "enter",
6970 "invlpg*", "monitor*", "mwait*", "tpause", "umwait", "pvalidate",
6971 "rmpadjust", "rmpupdate", and "rmpquery". We also don't reverse
6972 intersegment "jmp" and "call" instructions with 2 immediate operands so
6973 that the immediate segment precedes the offset consistently in Intel and
6974 AT&T modes. */
6990 /* The order of the immediates should be reversed for 2-immediates EXTRQ
6991 and INSERTQ instructions. Also UWRMSR wants its immediate to be in the
6992 "canonical" place (first), despite it appearing last (in AT&T syntax, or
6993 because of the swapping above) in the incoming set of operands. */
7001 {
7002 /* For USER_MSR and MSR_IMM instructions, imm32 stands for the name of a
7003 model specific register (MSR). That's an unsigned quantity, whereas all
7004 other insns with 32-bit immediate and 64-bit operand size use
7005 sign-extended immediates (imm32s). Therefore these insns are
7006 special-cased, bypassing the normal handling of immediates here. */
7010 {
7012 {
7015 }
7016 }
7017 else
7019 }
7024 /* Next, we find a template that matches the given insn,
7025 making sure the overlap of the given operands types is consistent
7026 with the template operand types. */
7029 {
7033 {
7036 no_match:
7041 }
7043 /* If a non-/only-64bit template (group) was found in pass 1, and if
7044 _some_ template (group) was found in pass 2, squash pass 1's
7045 error. */
7049 match_error:
7053 {
7098 {
7102 mnem_suffix);
7103 else
7106 mnem_suffix);
7107 }
7108 else
7109 {
7113 else
7116 }
7176 }
7180 }
7185 /* The opcode space check isn't strictly needed; it's there only to
7186 bypass the logic below when easily possible. */
7191 {
7192 /* Some KL and all WideKL insns have only implicit %xmm operands. */
7196 {
7201 }
7205 ? as_warn
7207 }
7213 /* Check if REP prefix is OK. */
7215 {
7219 }
7221 /* Check for lock without a lockable instruction. Destination operand
7222 must be memory unless it is xchg (0x86). */
7224 {
7229 {
7232 }
7234 /* Zap the redundant prefix from XCHG when optimizing. */
7237 }
7239 #ifdef OBJ_ELF
7241 {
7244 {
7252 }
7253 }
7254 #endif
7259 {
7260 /* Check for data size prefix on VEX/XOP/EVEX encoded and SIMD insns. */
7262 {
7265 }
7266 }
7268 /* Check if HLE prefix is OK. */
7272 /* Check BND prefix. */
7276 /* Check NOTRACK prefix. */
7281 {
7288 }
7290 /* Insert BND prefix. */
7292 {
7296 {
7299 }
7300 }
7302 /* Check string instruction segment overrides. */
7304 {
7309 }
7311 /* The memory operand of (%dx) should be only used with input/output
7312 instructions (base opcodes: 0x6c, 0x6e, 0xec, 0xee). */
7316 {
7320 }
7323 {
7327 }
7329 /* Past optimization there's no need to distinguish encoding_evex,
7330 encoding_evex512, and encoding_egpr anymore. */
7337 /* Similarly {nf} can now be taken to imply {evex}. */
7347 /* Check if IP-relative addressing requirements can be satisfied. */
7352 /* Update operand types and check extended states. */
7354 {
7357 {
7379 }
7380 }
7382 /* Make still unresolved immediate matches conform to size of immediate
7383 given in i.suffix. */
7390 /* For insns with operands there are more diddles to do to the opcode. */
7392 {
7395 }
7397 {
7398 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
7400 }
7403 {
7405 {
7409 }
7411 /* Check for explicit REX prefix. */
7414 /* To mimic behavior for legacy insns, permit use of REX64 for promoted
7415 legacy instructions. */
7418 {
7421 }
7423 /* Check for explicit REX2 prefix. */
7425 {
7428 }
7431 {
7434 }
7437 else
7440 /* The individual REX.RXBW bits got consumed. */
7443 /* The rex2 bits got consumed. */
7445 }
7447 /* Handle conversion of 'int $3' --> special int3 insn. */
7450 {
7453 }
7459 {
7460 /* Convert "jmp constant" (and "call constant") to a jump (call) to
7461 the absolute address given by the constant. Since ix86 jumps and
7462 calls are pc relative, we need to generate a reloc. */
7465 }
7471 /* We are ready to output the insn. */
7474 #ifdef OBJ_ELF
7475 /* PS: SCFI is enabled only for System V AMD64 ABI. The ABI check has been
7476 performed in i386_target_format. */
7478 {
7482 }
7483 #endif
7488 {
7492 }
7493 else
7495 }
7497 void
7499 {
7503 }
7505 /* The Q suffix is generally valid only in 64-bit mode, with very few
7506 exceptions: fild, fistp, fisttp, and cmpxchg8b. Note that for fild
7507 and fisttp only one of their two templates is matched below: That's
7508 sufficient since other relevant attributes are the same between both
7509 respective templates. */
7511 {
7517 }
7521 {
7530 {
7534 /* Pseudo-prefixes start with an opening figure brace. */
7536 {
7541 }
7545 {
7548 mnem_p++;
7550 {
7551 too_long:
7554 }
7555 l++;
7556 }
7560 /* Pseudo-prefixes end with a closing figure brace. */
7562 {
7570 }
7573 && (intel_syntax
7575 {
7581 }
7583 {
7586 else
7589 }
7591 /* Look up instruction (or prefix) via hash table. */
7597 {
7600 {
7606 }
7608 {
7614 }
7615 /* If we are in 16-bit mode, do not allow addr16 or data16.
7616 Similarly, in 32-bit mode, do not allow addr32 or data32. */
7622 {
7626 }
7629 {
7630 /* Handle pseudo prefixes. */
7632 {
7634 /* {disp8} */
7638 /* {disp16} */
7642 /* {disp32} */
7646 /* {load} */
7650 /* {store} */
7654 /* {vex} */
7658 /* {vex3} */
7662 /* {evex} */
7666 /* {rex} */
7670 /* {rex2} */
7674 /* {nf} */
7678 /* {nooptimize} */
7683 }
7687 {
7690 }
7691 }
7692 else
7693 {
7694 /* Add prefix, checking for repeated prefixes. */
7696 {
7708 else
7713 }
7714 }
7715 /* Skip past PREFIX_SEPARATOR and reset token_start. */
7720 }
7721 else
7723 }
7729 {
7730 /* Deprecated functionality (new code should use pseudo-prefixes instead):
7731 Check if we should swap operand or force 32bit displacement in
7732 encoding. */
7734 {
7737 else
7740 }
7744 {
7749 }
7754 {
7759 }
7760 else
7765 }
7768 {
7771 check_suffix:
7773 {
7774 /* See if we can get a match by trimming off a suffix. */
7776 {
7780 else
7781 /* Fall through. */
7791 {
7795 }
7798 /* Intel Syntax. */
7801 {
7804 else
7808 }
7809 /* For compatibility reasons accept MOVSD and CMPSD without
7810 operands even in AT&T mode. */
7812 {
7816 /* MOVS or CMPS */
7819 == SPACE_BASE
7821 {
7825 }
7826 else
7827 {
7830 }
7831 }
7833 }
7834 }
7837 {
7841 }
7842 }
7844 /* Handle SCC OSZC flgs. */
7846 {
7851 }
7856 {
7857 /* Check for a branch hint. We allow ",pt" and ",pn" for
7858 predict taken and predict not taken respectively.
7859 I'm not sure that branch hints actually do anything on loop
7860 and jcxz insns (JumpByte) for current Pentium4 chips. They
7861 may work in the future and it doesn't hurt to accept them
7862 now. */
7868 {
7870 {
7874 }
7876 {
7880 }
7881 else
7883 }
7884 else
7886 }
7887 /* Any other comma loses. */
7889 {
7893 }
7895 /* Check if instruction is supported on specified architecture. */
7898 {
7906 }
7909 {
7912 else
7914 }
7917 }
7921 {
7924 /* 1 if operand is pending after ','. */
7928 {
7929 /* Non-zero if operand parens not balanced. */
7931 /* True if inside double quotes. */
7934 /* Skip optional white space before operand. */
7938 {
7943 }
7946 {
7948 {
7950 {
7954 }
7956 {
7961 }
7962 else
7964 }
7970 {
7975 }
7977 {
7982 }
7983 l++;
7984 }
7990 {
7992 MAX_OPERANDS);
7994 }
7996 /* Now parse operand adding info to 'i' as we go along. */
8000 {
8002 mnemonic);
8004 }
8007 operand_ok =
8010 else
8016 }
8017 else
8018 {
8020 {
8021 expecting_operand_after_comma:
8024 }
8026 {
8029 }
8030 }
8032 /* Now *l must be either ',' or END_OF_INSN. */
8034 {
8036 {
8037 /* Just skip it, if it's \n complain. */
8039 }
8041 }
8042 }
8044 }
8046 static void
8048 {
8055 /* Note: i.mask and i.broadcast aren't handled here, as what (if
8056 anything) to do there depends on context. */
8057 }
8059 static void
8061 {
8063 i386_operand_type temp_type;
8088 {
8093 }
8095 {
8100 }
8101 }
8103 static void
8105 {
8107 {
8111 /* Fall through. */
8118 }
8121 {
8126 }
8127 }
8129 /* Try to ensure constant immediates are represented in the smallest
8130 opcode possible. */
8131 static void
8133 {
8140 {
8141 /* Figure out a suffix from the last register operand specified.
8142 We can't do this properly yet, i.e. excluding special register
8143 instances, but the following works for instructions with
8144 immediates. In any case, we can't set i.suffix yet. */
8149 {
8152 }
8154 {
8157 }
8159 {
8162 }
8164 {
8167 }
8168 }
8174 /* A more generic (but also more involved) way of dealing
8175 with the special case(s) would be to go look for
8176 DefaultSize attributes on any of the templates. */
8183 {
8185 {
8187 /* If a suffix is given, this operand may be shortened. */
8189 {
8208 }
8210 /* If this operand is at most 16 bits, convert it
8211 to a signed 16 bit number before trying to see
8212 whether it will fit in an even smaller size.
8213 This allows a 16-bit operand such as $0xffe0 to
8214 be recognised as within Imm8S range. */
8217 {
8220 }
8221 #ifdef BFD64
8222 /* Store 32-bit immediate in 64-bit for 64-bit BFD. */
8225 {
8229 }
8230 #endif
8235 /* We must avoid matching of Imm32 templates when 64bit
8236 only immediate is available. */
8245 /* Symbols and expressions. */
8247 /* Convert symbolic operand to proper sizes for matching, but don't
8248 prevent matching a set of insns that only supports sizes other
8249 than those matching the insn suffix. */
8250 {
8256 {
8272 }
8276 {
8279 }
8283 }
8285 }
8286 }
8287 }
8289 /* Try to use the smallest displacement type too. */
8290 static bool
8292 {
8298 {
8300 {
8309 /* Since displacement is signed extended to 64bit, don't allow
8310 disp32 if it is out of range. */
8316 {
8320 }
8321 }
8322 }
8324 /* Don't optimize displacement for movabs / jmpabs since they only take
8325 64-bit displacement. */
8332 {
8334 {
8338 {
8343 }
8347 {
8348 /* If this operand is at most 16 bits, convert
8349 to a signed 16 bit number and don't use 64bit
8350 displacement. */
8353 }
8355 #ifdef BFD64
8356 /* Optimize 64-bit displacement to 32-bit for 64-bit BFD. */
8363 {
8364 /* If this operand is at most 32 bits, convert
8365 to a signed 32 bit number and don't use 64bit
8366 displacement. */
8370 }
8373 {
8376 }
8377 #endif
8384 }
8387 {
8391 }
8392 else
8393 /* We only support 64bit displacement on constants. */
8395 }
8398 }
8400 /* Return 1 if there is a match in broadcast bytes between operand
8401 GIVEN and instruction template T. */
8405 {
8414 }
8416 /* Check if operands are valid for the instruction. */
8418 static int
8420 {
8422 i386_cpu_flags cpu;
8424 /* Templates allowing for ZMMword as well as YMMword and/or XMMword for
8425 any one operand are implicity requiring AVX512VL support if the actual
8426 operand size is YMMword or XMMword. Since this function runs after
8427 template matching, there's no need to check for YMMword/XMMword in
8428 the template. */
8434 {
8436 {
8440 {
8443 }
8444 }
8445 }
8447 /* Somewhat similarly, templates specifying both AVX and AVX2 are
8448 requiring AVX2 support if the actual operand size is YMMword. */
8451 {
8453 {
8456 {
8459 }
8460 }
8461 }
8463 /* Without VSIB byte, we can't have a vector register for index. */
8469 {
8472 }
8474 /* Check if default mask is allowed. */
8477 {
8480 }
8482 /* For VSIB byte, we need a vector register for index, and all vector
8483 registers must be distinct. */
8485 {
8493 {
8496 }
8500 {
8517 {
8520 }
8522 }
8524 {
8531 {
8533 {
8536 }
8539 }
8540 }
8541 }
8543 /* For AMX instructions with 3 TMM register operands, all operands
8544 must be distinct. */
8550 {
8553 }
8555 /* For some special instructions require that destination must be distinct
8556 from source registers. */
8558 {
8563 /* #UD if dest_reg == src1_reg or dest_reg == src2_reg. */
8567 {
8570 }
8571 }
8573 /* Check if broadcast is supported by the instruction and is applied
8574 to the memory operand. */
8576 {
8579 /* Check if specified broadcast is supported in this instruction,
8580 and its broadcast bytes match the memory operand. */
8586 {
8587 bad_broadcast:
8590 }
8594 {
8619 }
8627 {
8631 }
8636 {
8641 {
8645 type,
8648 }
8649 }
8650 }
8651 /* If broadcast is supported in this instruction, we need to check if
8652 operand of one-element size isn't specified without broadcast. */
8654 {
8655 /* Find memory operand. */
8660 /* Check size of the memory operand. */
8662 {
8665 }
8666 }
8667 else
8670 /* Check if requested masking is supported. */
8672 {
8674 {
8677 }
8679 /* Common rules for masking:
8680 - mask register destinations permit only zeroing-masking, without
8681 that actually being expressed by a {z} operand suffix or EVEX.z,
8682 - memory destinations allow only merging-masking,
8683 - scatter/gather insns (i.e. ones using vSIB) only allow merging-
8684 masking. */
8689 {
8692 }
8693 }
8695 /* Check if masking is applied to dest operand. */
8697 {
8700 }
8702 /* Check RC/SAE. */
8704 {
8708 {
8711 }
8713 /* Non-EVEX.{LIG,512,256} forms need to have a ZMM or YMM register as at
8714 least one operand. For YMM register or EVEX256, we will need AVX10.2
8715 enabled. There's no need to check all operands, though: Either of the
8716 last two operands will be of the right size in all relevant templates. */
8726 {
8729 }
8730 }
8732 /* Check the special Imm4 cases; must be the first operand. */
8742 {
8745 {
8748 }
8750 /* Turn off Imm<N> so that update_imm won't complain. */
8753 }
8755 /* Check vector Disp8 operand. */
8760 {
8765 else
8766 {
8772 {
8783 }
8786 {
8793 }
8798 {
8805 }
8807 /* For the check in fits_in_disp8(). */
8810 }
8815 {
8816 /* Make sure to leave i.types[op].bitfield.disp8 alone upon
8817 secondary invocations of match_template(). */
8819 {
8823 }
8826 }
8827 }
8832 }
8834 /* Check if encoding requirements are met by the instruction. */
8836 static int
8838 {
8840 {
8843 }
8845 /* Vector size restrictions. */
8851 {
8854 }
8857 {
8860 /* This instruction must be encoded with VEX prefix. */
8862 {
8865 }
8871 /* Fall through. */
8874 /* This instruction must be encoded with EVEX prefix. */
8876 {
8879 }
8883 /* This instruction must be encoded with REX2 or EVEX prefix. */
8885 {
8888 }
8893 }
8896 }
8898 /* Check if Egprs operands are valid for the instruction. */
8900 static bool
8902 {
8907 {
8912 {
8915 }
8916 }
8920 {
8923 }
8925 /* Check if pseudo prefix {rex2} is valid. */
8927 {
8930 }
8933 }
8935 /* Check if APX operands are valid for the instruction. */
8936 static bool
8938 {
8939 /* Push2* and Pop2* cannot use RSP and Pop2* cannot pop two same registers.
8940 */
8942 {
8946 {
8949 }
8950 /* fall through */
8955 {
8958 }
8960 }
8962 }
8964 /* Check if the instruction use the REX registers or REX prefix. */
8965 static bool
8967 {
8969 {
8975 }
8981 /* Check pseudo prefix {rex} are valid. */
8983 }
8985 /* Optimize APX NDD insns to legacy insns. */
8986 static unsigned int
8988 {
8992 {
9000 /* If the first operand is the same as the third operand,
9001 these instructions need to support the ability to commutative
9002 the first two operands and still not change the semantics in order
9003 to be optimized. */
9009 }
9011 }
9013 /* Helper function for the progress() macro in match_template(). */
9017 {
9022 }
9026 {
9027 /* Points to template once we've found it. */
9030 i386_operand_type overlap4;
9036 #define progress(err) progress (err, specific_error, __LINE__, &errline)
9038 #if MAX_OPERANDS != 5
9040 #endif
9046 {
9050 /* Must have right number of operands. */
9054 /* Skip SSE2AVX templates when inapplicable. */
9057 {
9058 /* Another non-SSE2AVX template has to follow. */
9061 }
9063 /* Check processor support. */
9068 /* Check AT&T mnemonic. */
9074 /* Check AT&T/Intel syntax. */
9081 /* Check NF support. */
9086 /* Check Intel64/AMD64 ISA. */
9088 {
9090 /* Default: Don't accept Intel64. */
9095 /* -mamd64: Don't accept Intel64 and Intel64 only. */
9100 /* -mintel64: Don't accept AMD64. */
9104 }
9106 /* Check the suffix. */
9120 /* This is intentionally not
9122 if (i.jumpabsolute != (t->opcode_modifier.jump == JUMP_ABSOLUTE))
9124 as the case of a missing * on the operand is accepted (perhaps with
9125 a warning, issued further down). */
9130 /* In Intel syntax, normally we can check for memory operand size when
9131 there is no mnemonic suffix. But jmp and call have 2 different
9132 encodings with Dword memory operand size. Skip the "near" one
9133 (permitting a register operand) when "far" was requested. */
9142 /* In general, don't allow 32-bit operands on pre-386. */
9148 && (intel_syntax
9162 /* Do not verify operands when there are none. */
9164 {
9166 {
9169 }
9171 /* Check if pseudo prefix {rex2} is valid. */
9173 {
9176 }
9178 /* We've found a match; break out of loop. */
9180 }
9184 {
9185 /* There should be only one Disp operand. */
9190 {
9195 /* Address size prefix will turn Disp64 operand into Disp32 and
9196 Disp32/Disp16 one into Disp16/Disp32 respectively. */
9198 {
9201 /* Fall through. */
9205 {
9208 }
9214 {
9218 }
9221 }
9222 }
9223 }
9225 /* We check register size if needed. */
9227 {
9231 }
9232 else
9237 {
9242 /* Allow the ModR/M encoding to be requested by using the {load} or
9243 {store} pseudo prefix on an applicable insn. */
9250 /* Avoid BSWAP. */
9256 /* xchg %eax, %eax is a special case. It is an alias for nop
9257 only in 32bit mode and we can use opcode 0x90. In 64bit
9258 mode, we can't use 0x90 for xchg %eax, %eax since it should
9259 zero-extend %eax to %rax. */
9262 {
9269 /* Allow the ModR/M encoding to be requested by using the
9270 {load} or {store} pseudo prefix. */
9274 }
9279 {
9280 /* Force 0x8b encoding for "mov foo@GOT, %eax". */
9284 /* xrelease mov %eax, <disp> is another special case. It must not
9285 match the accumulator-only encoding of mov. */
9289 /* Allow the ModR/M encoding to be requested by using a suitable
9290 {load} or {store} pseudo prefix. */
9292 ? dir_encoding_store
9297 }
9299 /* Allow the ModR/M encoding to be requested by using the {load} or
9300 {store} pseudo prefix on an applicable insn. */
9307 {
9320 }
9321 /* Fall through. */
9326 /* Reverse direction of operands if swapping is possible in the first
9327 place (operands need to be symmetric) and
9328 - the load form is requested, and the template is a store form,
9329 - the store form is requested, and the template is a load form,
9330 - the non-default (swapped) form is requested. */
9339 {
9357 }
9359 /* If we want store form, we skip the current load. */
9365 /* Fall through. */
9376 {
9379 /* Check if other direction is valid ... */
9383 check_reverse:
9386 /* Try reversing direction of operands. */
9399 || (check_register
9404 {
9405 /* Does not match either direction. */
9408 }
9409 /* found_reverse_match holds which variant of D
9410 we've found. */
9414 {
9417 else
9419 /* FSUB{,R} and FDIV{,R} may need a 2nd bit flipped. */
9423 }
9425 {
9428 }
9431 {
9434 }
9436 /* CFCMOVcc also wants its major opcode unaltered. */
9442 /* MOVBE, originating from SPACE_0F38, also
9443 belongs here. */
9446 /* MOV to/from CR/DR/TR, as an exception, follow
9447 the base opcode space encoding model. */
9451 else
9453 }
9454 else
9455 {
9456 /* Found a forward 2 operand match here. */
9457 check_operands_345:
9459 {
9467 {
9470 }
9471 /* Fall through. */
9485 {
9488 }
9489 /* Fall through. */
9503 {
9506 }
9508 }
9509 }
9510 /* Found either forward/reverse 2, 3 or 4 operand match here:
9511 slip through to break. */
9512 }
9514 /* Check if VEX/EVEX encoding requirements can be satisfied. */
9516 {
9519 }
9521 /* Check if EGPR operands(r16-r31) are valid. */
9523 {
9526 }
9528 /* Check if vector operands are valid. */
9530 {
9533 }
9535 /* Check if APX operands are valid. */
9537 {
9540 }
9542 /* Check whether to use the shorter VEX encoding for certain insns where
9543 the EVEX encoding comes first in the table. This requires the respective
9544 AVX-* feature to be explicitly enabled.
9546 Most of the respective insns have just a single EVEX and a single VEX
9547 template. The one that's presently different is generated using the
9548 Vxy / Exy constructs: There are 3 suffix-less EVEX forms, the latter
9549 two of which may fall back to their two corresponding VEX forms. */
9557 {
9558 i386_cpu_flags cpu;
9563 cpu_arch_isa_flags);
9569 {
9573 }
9575 }
9577 /* If we can optimize a NDD insn to legacy insn, like
9578 add %r16, %r8, %r8 -> add %r16, %r8,
9579 add %r8, %r16, %r8 -> add %r16, %r8, then rematch template.
9580 Note that the semantics have not been changed. */
9591 {
9595 {
9597 /* We ensure that the next template has the same input
9598 operands as the original matching template by the first
9599 opernd (ATT). To avoid someone support new NDD insns and
9600 put it in the wrong position. */
9613 /* Some non-legacy-map0/1 insns can be shorter when
9614 legacy-encoded and when no REX prefix is required. */
9618 {
9620 {
9623 /* CMOVcc is marked commutative, but then also needs its
9624 encoded condition inverted. */
9627 }
9633 {
9636 }
9640 }
9642 }
9643 }
9645 /* We've found a match; break out of loop. */
9647 }
9649 #undef progress
9652 {
9653 /* We found no match. */
9656 }
9658 /* Don't emit diagnostics or install the template when one was already
9659 installed, i.e. when called from process_suffix(). */
9664 {
9671 {
9672 /* Warn them that a data or address size prefix doesn't
9673 affect assembly of the next line of code. */
9675 }
9678 {
9683 {
9687 }
9688 }
9689 }
9691 /* Copy the template we found. */
9698 /* APX insns acting on byte operands are WIG, yet that can't be expressed
9699 in the templates (they're also covering word/dword/qword operands). */
9702 {
9705 }
9708 {
9717 /* Fall through. */
9719 /* If we found a reverse match we must alter the opcode direction
9720 bit and clear/flip the regmem modifier one. found_reverse_match
9721 holds bits to change (different for int & float insns). */
9728 /* Certain SIMD insns have their load forms specified in the opcode
9729 table, and hence we need to _set_ RegMem instead of clearing it.
9730 We need to avoid setting the bit though on insns like KMOVW. */
9736 /* Fall through. */
9746 /* Only the first two register operands need reversing, alongside
9747 flipping VEX.W. */
9750 /* In 3-operand insns XOP.W changes which operand goes into XOP.vvvv. */
9753 swap_first_2:
9758 }
9761 }
9763 static int
9765 {
9770 {
9774 register_prefix);
9776 }
9778 /* There's only ever one segment override allowed per instruction.
9779 This instruction possibly has a legal segment override on the
9780 second operand, so copy the segment to where non-string
9781 instructions store it, allowing common code. */
9785 }
9787 static int
9789 {
9792 /* If matched instruction specifies an explicit instruction mnemonic
9793 suffix, use it. */
9803 {
9806 /* MOVSX/MOVZX */
9813 /* movsx/movzx want only their source operand considered here, for the
9814 ambiguity checking below. The suffix will be replaced afterwards
9815 to represent the destination (register). */
9819 /* crc32 needs REX.W set regardless of suffix / source operand size. */
9823 /* If there's no instruction mnemonic suffix we try to invent one
9824 based on GPR operands. */
9826 {
9827 /* We take i.suffix from the last register operand specified,
9828 Destination register type is more significant than source
9829 register type. crc32 in SSE4.2 prefers source register
9830 type. */
9836 {
9847 else
9850 }
9852 /* As an exception, movsx/movzx silently default to a byte source
9853 in AT&T mode. */
9856 }
9858 {
9861 }
9863 {
9866 }
9868 {
9871 }
9873 {
9876 }
9879 /* Do nothing if the instruction is going to ignore the prefix. */
9880 ;
9881 else
9884 /* Undo the movsx/movzx change done above. */
9886 }
9889 {
9892 {
9893 /* stackop_size is set to LONG_MNEM_SUFFIX for the
9894 .code16gcc directive to support 16-bit mode with
9895 32-bit address. For IRET without a suffix, generate
9896 16-bit IRET (opcode 0xcf) to return from an interrupt
9897 handler. */
9899 {
9902 }
9903 /* Warn about changed behavior for segment register push/pop. */
9907 }
9908 }
9916 {
9918 {
9921 {
9926 }
9927 /* Fall through. */
9936 }
9937 }
9941 /* Also cover lret/retf/iret in 64-bit mode. */
9946 /* Explicit sizing prefixes are assumed to disambiguate insns. */
9948 /* Accept FLDENV et al without suffix. */
9950 {
9963 /* Operand size may be ambiguous only across multiple templates. Avoid
9964 the extra effort though if we already know that multiple suffixes /
9965 operand sizes are allowed. Also limit this to non-SIMD operand sizes
9966 (i.e. ones expressable via suffixes) for now.
9967 There's one special case though that needs excluding: Insns taking
9968 Disp<N> operands also match templates permitting BaseIndex. JMP in
9969 particular would thus wrongly trigger the check further down. Cover
9970 JUMP_DWORD insns here as well, just in case. */
9974 {
9975 /* Sadly check_VecOperands(), running ahead of install_template(),
9976 may update i.memshift. Save and restore the value here. */
9994 }
9996 /* For [XYZ]MMWORD operands inspect operand sizes. While generally
9997 also suitable for AT&T syntax mode, it was requested that this be
9998 restricted to just Intel syntax. */
10001 {
10005 {
10007 {
10010 {
10015 }
10020 }
10023 {
10030 }
10037 /* Any properly sized operand disambiguates the insn. */
10041 {
10045 }
10049 {
10058 }
10059 }
10060 }
10062 /* Are multiple suffixes / operand sizes allowed? */
10064 {
10068 {
10071 }
10073 {
10077 }
10080 intel_syntax
10096 else
10098 }
10099 }
10102 {
10103 /* In Intel syntax, movsx/movzx must have a "suffix" (checked above).
10104 In AT&T syntax, if there is no suffix (warned about above), the default
10105 will be byte extension. */
10109 /* For further processing, the suffix should represent the destination
10110 (register). This is already the case when one was used with
10111 mov[sz][bw]*, but we need to replace it for mov[sz]x, or if there was
10112 no suffix to begin with. */
10114 {
10119 else
10123 }
10124 }
10130 /* Change the opcode based on the operand size given by i.suffix. */
10132 {
10133 /* Size floating point instruction. */
10136 {
10139 }
10140 /* fall through */
10143 /* It's not a byte, select word/dword operation. */
10145 {
10148 else
10150 }
10152 /* Set mode64 for an operand. */
10154 {
10158 /* Special case for xchg %rax,%rax. It is NOP and doesn't
10159 need rex64. */
10168 }
10170 /* fall through */
10172 /* Now select between word & dword operations via the operand
10173 size prefix, except for instructions that will ignore this
10174 prefix anyway. */
10182 {
10188 /* The DATA PREFIX of EVEX promoted from legacy APX instructions
10189 needs to be adjusted. */
10191 {
10194 }
10197 }
10202 /* Select word/dword/qword operation with explicit data sizing prefix
10203 when there are no suitable register operands. */
10208 /* ShiftCount */
10210 /* InOutPortReg */
10216 }
10219 {
10225 {
10226 /* The address size override prefix changes the size of the
10227 first operand. */
10230 {
10234 }
10241 }
10242 else
10243 {
10244 /* Check invalid register operand when the address size override
10245 prefix changes the size of register operands. */
10249 /* Check the register operand for the address size prefix if
10250 the memory operand has no real registers, like symbol, DISP
10251 or bogus (x32-only) symbol(%rip) when symbol(%eip) is meant. */
10260 #ifdef OBJ_ELF
10265 #else
10267 #endif
10275 else
10279 {
10284 {
10297 }
10302 }
10303 }
10304 }
10307 }
10309 static int
10311 {
10315 {
10316 /* Skip non-register operands. */
10320 /* If this is an eight bit register, it's OK. */
10322 {
10326 }
10328 /* I/O port address operands are OK too. */
10333 /* crc32 only wants its source operand checked here. */
10337 /* Any other register is bad. */
10342 }
10344 }
10346 static int
10348 {
10352 /* Skip non-register operands. */
10355 /* Reject eight bit registers, except where the template requires
10356 them. (eg. movzb) */
10361 {
10363 register_prefix,
10368 }
10369 /* Error if the e prefix on a general reg is missing, or if the r
10370 prefix on a general reg is present. */
10374 {
10379 }
10384 }
10386 static int
10388 {
10392 /* Skip non-register operands. */
10395 /* Reject eight bit registers, except where the template requires
10396 them. (eg. movzb) */
10401 {
10403 register_prefix,
10408 }
10409 /* Error if the r prefix on a general reg is missing. */
10413 {
10417 }
10422 }
10424 static int
10426 {
10429 /* Skip non-register operands. */
10432 /* Reject eight bit registers, except where the template requires
10433 them. (eg. movzb) */
10438 {
10440 register_prefix,
10445 }
10446 /* Error if the e or r prefix on a general reg is present. */
10450 {
10455 }
10460 }
10462 static int
10464 {
10470 {
10471 /* This combination is used on 8-bit immediates where e.g. $~0 is
10472 desirable to permit. We're past operand type matching, so simply
10473 put things back in the shape they were before introducing the
10474 distinction between Imm8, Imm8S, and Imm8|Imm8S. */
10476 }
10484 {
10490 };
10493 };
10496 };
10499 {
10500 i386_operand_type temp;
10504 {
10507 }
10511 {
10514 }
10515 else
10518 }
10522 {
10526 else
10528 }
10540 {
10544 }
10545 }
10549 }
10551 static int
10553 {
10556 /* Update the first 2 immediate operands. */
10559 {
10564 /* The 3rd operand can't be immediate operand. */
10566 }
10569 }
10573 {
10575 {
10579 }
10581 {
10584 }
10591 }
10595 {
10600 }
10602 static int
10604 {
10605 /* Default segment register this instruction will use for memory
10606 accesses. 0 means unknown. This is only for optimizing out
10607 unnecessary segment overrides. */
10615 {
10616 /* Legacy encoded insns allow explicit REX prefixes, so these prefixes
10617 need converting. */
10622 }
10623 /* ImmExt should be processed after SSE2AVX. */
10627 /* TILEZERO is unusual in that it has a single operand encoded in ModR/M.reg,
10628 not ModR/M.rm. To avoid special casing this in build_modrm_byte(), fake a
10629 new destination operand here, while converting the source one to register
10630 number 0. */
10632 {
10638 }
10641 {
10644 };
10649 /* The destination must be an xmm register. */
10656 {
10657 /* Keep xmm0 for instructions with VEX prefix and 3
10658 sources. */
10663 }
10666 {
10669 /* Add the implicit xmm0 for instructions with VEX prefix
10670 and 3 sources. */
10682 dupl++;
10683 dest++;
10684 }
10685 else
10686 {
10687 duplicate:
10691 }
10697 }
10700 {
10706 /* No adjustment to i.reg_operands: This was already done at the top
10707 of the function. */
10710 }
10712 {
10716 /* The second operand must be {x,y,z}mmN. */
10720 {
10722 /* AVX512-{4FMAPS,4VNNIW} operand 2: N must be a multiple of 4. */
10728 /* AVX512-VP2INTERSECT operand 3: N must be a multiple of 2. */
10735 }
10746 }
10748 {
10749 /* The imul $imm, %reg instruction is converted into
10750 imul $imm, %reg, %reg, and the clr %reg instruction
10751 is converted into xor %reg, %reg. */
10757 else
10759 /* Pretend we saw the extra register operand. */
10767 /* For IMULZU switch around the constraint. */
10770 }
10773 {
10774 /* The opcode is completed (modulo i.tm.extension_opcode which
10775 must be put into the modrm byte). Now, we make the modrm and
10776 index base bytes based on all the info we've collected. */
10781 {
10782 /* Warn about some common errors, but press on regardless. */
10784 {
10785 /* Reversed arguments on faddp or fmulp. */
10789 }
10791 {
10792 /* Extraneous `l' suffix on fp insn. */
10795 }
10796 }
10797 }
10799 {
10805 {
10809 }
10812 {
10815 }
10817 }
10820 {
10822 }
10824 {
10825 /* For the string instructions that allow a segment override
10826 on one of their operands, the default segment is ds. */
10828 }
10830 {
10831 /* The register operand is in the 1st or 2nd non-immediate operand. */
10838 /* Register goes in low 3 bits of opcode. */
10843 {
10847 }
10848 }
10853 {
10857 }
10861 {
10865 {
10868 }
10869 }
10871 /* If a segment was explicitly specified, and the specified segment
10872 is neither the default nor the one already recorded from a prefix,
10873 use an opcode prefix to select it. If we never figured out what
10874 the default segment is, then default_seg will be zero at this
10875 point, and the specified segment prefix will always be used. */
10879 {
10882 }
10884 }
10888 {
10891 /* Compensate for kludge in md_assemble(). */
10896 /* Accumulator (in particular %st), shift count (%cl), and alike need
10897 to be skipped just like immediate operands do. */
10908 {
10911 /* There are 2 kinds of instructions:
10912 1. 5 operands: 4 register operands or 3 register operands
10913 plus 1 memory operand plus one Imm4 operand, VexXDS, and
10914 VexW0 or VexW1. The destination must be either XMM, YMM or
10915 ZMM register.
10916 2. 4 operands: 4 register operands or 3 register operands
10917 plus 1 memory operand, with VexXDS.
10918 3. Other equivalent combinations when coming from s_insn(). */
10924 /* Of the first two non-immediate operands the one with the template
10925 not allowing for a memory one is encoded in the immediate operand. */
10928 else
10932 {
10935 }
10936 else
10940 {
10941 /* When there is no immediate operand, generate an 8bit
10942 immediate operand to encode the first operand. */
10949 }
10950 else
10951 {
10956 /* Turn on Imm8 again so that output_imm will generate it. */
10960 }
10964 }
10967 {
10968 /* VEX.vvvv encodes the last source register operand. */
10972 /* VEX.vvvv encodes the first source register operand. */
10976 /* VEX.vvvv encodes the destination register operand. */
10983 }
10991 {
10994 }
10997 {
10999 {
11005 {
11006 /* The index register of VSIB shouldn't be RegIZ. */
11013 {
11018 }
11020 /* Since the mandatory SIB always has index register, so
11021 the code logic remains unchanged. The non-mandatory SIB
11022 without index register is allowed and will be handled
11023 later. */
11025 {
11028 else
11031 }
11032 }
11037 {
11042 {
11043 /* Both check for VSIB and mandatory non-vector SIB. */
11046 /* Operand is just <disp> */
11049 {
11050 /* 64bit mode overwrites the 32bit absolute
11051 addressing by RIP relative addressing and
11052 absolute addressing is encoded by one of the
11053 redundant SIB forms. */
11058 }
11061 {
11064 }
11065 else
11066 {
11069 }
11070 }
11072 {
11073 /* !i.base_reg && i.index_reg */
11076 else
11084 }
11085 }
11086 /* RIP addressing for 64bit mode. */
11088 {
11098 }
11100 {
11103 {
11113 {
11116 {
11117 /* fake (%bp) into 0(%bp) */
11120 else
11123 }
11124 }
11130 }
11134 {
11138 else
11140 }
11142 }
11144 {
11146 {
11150 }
11156 /* x86-64 ignores REX prefix bit here to avoid decoder
11157 complications. */
11163 {
11167 else
11169 }
11172 {
11173 /* Only check for VSIB. */
11178 /* <disp>(%esp) becomes two byte modrm with no index
11179 register. We've already stored the code for esp
11180 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
11181 Any base register besides %esp will not use the
11182 extra modrm byte. */
11184 }
11186 {
11189 else
11193 }
11199 else
11200 {
11204 {
11208 else
11210 }
11212 }
11213 }
11216 {
11217 /* Fakes a zero displacement assuming that i.types[op]
11218 holds the correct displacement size. */
11228 }
11229 }
11230 else
11231 {
11235 }
11241 }
11242 else
11243 {
11246 {
11252 }
11253 else
11254 {
11259 }
11260 }
11262 /* Fill in i.rm.reg field with extension opcode (if any) or the
11263 appropriate register. */
11267 {
11270 }
11271 else
11272 {
11276 }
11279 {
11283 }
11286 }
11290 {
11293 else
11295 }
11297 static unsigned int
11299 {
11306 }
11308 static void
11310 {
11315 relax_substateT subtype;
11317 offsetT off;
11320 {
11323 }
11330 {
11334 }
11335 /* Pentium4 branch hints. */
11338 {
11339 prefix++;
11341 }
11343 {
11344 prefix++;
11346 }
11348 /* BND prefixed jump. */
11350 {
11351 prefix++;
11353 }
11358 /* It's always a symbol; End frag & setup for relax.
11359 Make sure there is enough room in this frag for the largest
11360 instruction we may generate in md_convert_frag. This is 2
11361 bytes for the opcode and room for the prefix and largest
11362 displacement. */
11364 /* Prefix and 1 opcode byte go in fr_fix. */
11381 else
11390 {
11391 /* Handle complex expressions. */
11394 }
11396 /* 1 possible extra opcode + 4 byte displacement go in var part.
11397 Pass reloc in fr_var. */
11399 }
11401 /* PLT32 relocation is ELF only. */
11402 #ifdef OBJ_ELF
11403 /* Return TRUE iff PLT32 relocation should be used for branching to
11404 symbol S. */
11406 static bool
11408 {
11409 #ifdef TE_SOLARIS
11410 /* Don't emit PLT32 relocation on Solaris: neither native linker nor
11411 krtld support it. */
11413 #endif
11415 /* Since there is no need to prepare for PLT branch on x86-64, we
11416 can generate R_X86_64_PLT32, instead of R_X86_64_PC32, which can
11417 be used as a marker for 32-bit PC-relative branches. */
11424 /* Weak or undefined symbol need PLT32 relocation. */
11428 /* Non-global symbol doesn't need PLT32 relocation. */
11432 /* Other global symbols need PLT32 relocation. NB: Symbol with
11433 non-default visibilities are treated as normal global symbol
11434 so that PLT32 relocation can be used as a marker for 32-bit
11435 PC-relative branches. It is useful for linker relaxation. */
11437 }
11438 #endif
11440 static void
11442 {
11449 {
11450 /* This is a loop or jecxz type instruction. */
11453 {
11456 }
11457 /* Pentium4 branch hints. */
11460 {
11463 }
11464 }
11465 else
11466 {
11474 {
11478 }
11483 }
11485 /* BND prefixed jump. */
11487 {
11490 }
11493 {
11496 }
11502 {
11505 }
11509 {
11512 /* Fall through. */
11518 }
11520 #ifdef OBJ_ELF
11525 #endif
11532 /* All jumps handled here are signed, but don't unconditionally use a
11533 signed limit check for 32 and 16 bit jumps as we want to allow wrap
11534 around at 4G (outside of 64-bit mode) and 64k (except for XBEGIN)
11535 respectively. */
11537 {
11551 }
11552 }
11554 static void
11556 {
11568 {
11572 }
11584 {
11587 }
11589 /* 1 opcode; 2 segment; offset */
11600 {
11606 {
11609 }
11611 }
11612 else
11619 else
11622 }
11624 /* Hook used to reject pseudo-prefixes misplaced at the start of a line. */
11627 {
11635 }
11637 /* Hook used to warn about pseudo-prefixes ahead of a label. */
11640 {
11648 }
11650 /* Hook used to parse pseudo-prefixes off of the start of a line. */
11652 int
11654 {
11666 {
11667 /* Diagnostic was already issued. */
11671 }
11674 {
11677 }
11681 }
11683 #ifdef OBJ_ELF
11684 void
11686 {
11701 /* The .note.gnu.property section layout:
11703 Field Length Contents
11704 ---- ---- ----
11705 n_namsz 4 4
11706 n_descsz 4 The note descriptor size
11707 n_type 4 NT_GNU_PROPERTY_TYPE_0
11708 n_name 4 "GNU"
11709 n_desc n_descsz The program property array
11710 .... .... ....
11711 */
11713 /* Create the .note.gnu.property section. */
11716 (SEC_ALLOC
11717 | SEC_LOAD
11718 | SEC_DATA
11719 | SEC_HAS_CONTENTS
11723 {
11726 }
11727 else
11728 {
11731 }
11736 /* GNU_PROPERTY_X86_ISA_1_USED: 4-byte type + 4-byte data size
11737 + 4-byte data */
11739 /* Align GNU_PROPERTY_X86_ISA_1_USED. */
11743 /* GNU_PROPERTY_X86_FEATURE_2_USED: 4-byte type + 4-byte data size
11744 + 4-byte data */
11746 /* Align GNU_PROPERTY_X86_FEATURE_2_USED. */
11751 /* Section size: n_namsz + n_descsz + n_type + n_name + n_descsz. */
11754 /* Write n_namsz. */
11757 /* Write n_descsz. */
11760 /* Write n_type. */
11763 /* Write n_name. */
11766 /* Write 4-byte type. */
11770 /* Write 4-byte data size. */
11773 /* Write 4-byte data. */
11776 /* Zero out paddings. */
11781 /* Write 4-byte type. */
11785 /* Write 4-byte data size. */
11788 /* Write 4-byte data. */
11792 /* Zero out paddings. */
11797 /* We probably can't restore the current segment, for there likely
11798 isn't one yet... */
11801 }
11805 /* Whether SFrame stack trace info is supported. */
11806 bool
11808 {
11809 /* At this time, SFrame stack trace is supported for AMD64 ABI only. */
11811 }
11813 /* Whether SFrame return address tracking is needed. */
11814 bool
11816 {
11817 /* In AMD64, return address is always stored on the stack at a fixed offset
11818 from the CFA (provided via x86_sframe_cfa_ra_offset ()).
11819 Do not track explicitly via an SFrame Frame Row Entry. */
11821 }
11823 /* The fixed offset from CFA for SFrame to recover the return address.
11824 (useful only when SFrame RA tracking is not needed). */
11825 offsetT
11827 {
11830 }
11832 /* The abi/arch indentifier for SFrame. */
11833 unsigned char
11835 {
11839 {
11842 }
11845 }
11847 #endif
11849 static unsigned int
11852 {
11856 {
11863 }
11866 }
11868 /* Return 1 for test, and, cmp, add, sub, inc and dec which may
11869 be macro-fused with conditional jumps.
11870 NB: If TEST/AND/CMP/ADD/SUB/INC/DEC is of RIP relative address,
11871 or is one of the following format:
11873 cmp m, imm
11874 add m, imm
11875 sub m, imm
11876 test m, imm
11877 and m, imm
11878 inc m
11879 dec m
11881 it is unfusible. */
11883 static int
11885 {
11886 /* No RIP address. */
11890 /* No opcodes outside of base encoding space. */
11894 /* add, sub without add/sub m, imm. */
11900 {
11903 }
11905 /* and without and m, imm. */
11909 {
11912 }
11914 /* test without test m imm. */
11919 {
11922 }
11924 /* cmp without cmp m, imm. */
11928 {
11931 }
11933 /* inc, dec without inc/dec m. */
11938 {
11941 }
11944 }
11946 /* Return 1 if a FUSED_JCC_PADDING frag should be generated. */
11948 static int
11951 {
11952 /* NB: Don't work with COND_JUMP86 without i386. */
11960 {
11967 }
11970 }
11972 /* Return 1 if a BRANCH_PREFIX frag should be generated. */
11974 static int
11976 {
11977 /* NB: Don't work with COND_JUMP86 without i386. Don't add prefix
11978 to PadLock instructions since they include prefixes in opcode. */
11980 || !align_branch_prefix_size
11986 /* Don't add prefix if it is a prefix or there is no operand in case
11987 that segment prefix is special. */
12000 }
12002 /* Return 1 if a BRANCH_PADDING frag should be generated. */
12004 static int
12008 {
12011 /* NB: Don't work with COND_JUMP86 without i386. */
12020 /* Check for jcc and direct jmp. */
12022 {
12024 {
12027 }
12028 else
12029 {
12030 /* Because J<cc> and JN<cc> share same group in macro-fusible table,
12031 igore the lowest bit. */
12036 }
12037 }
12039 {
12040 /* Near ret. */
12044 }
12045 else
12046 {
12047 /* Check for indirect jmp, direct and indirect calls. */
12049 {
12050 /* Direct call. */
12054 }
12058 {
12059 /* Indirect call and jmp. */
12063 }
12067 && tls_get_addr
12071 {
12073 /* No padding to call to global or undefined tls_get_addr. */
12077 }
12078 }
12082 {
12088 }
12091 }
12093 static void
12095 {
12097 offsetT insn_start_off;
12100 /* The initializer is arbitrary just to avoid uninitialized error.
12101 it's actually either assigned in add_branch_padding_frag_p
12102 or never be used. */
12105 #ifdef OBJ_ELF
12107 {
12125 {
12132 }
12134 /* vzeroall / vzeroupper */
12139 /* ldmxcsr / stmxcsr / vldmxcsr / vstmxcsr */
12173 /* LAHF-SAHF insns in 64-bit mode. */
12180 /* Any VEX encoded insns execpt for AVX512F, AVX512BW, AVX512DQ,
12181 XOP, FMA4, LPW, TBM, and AMX. */
12196 || (x86_feature_2_used
12197 & (GNU_PROPERTY_X86_FEATURE_2_XSAVE
12198 | GNU_PROPERTY_X86_FEATURE_2_XSAVEOPT
12205 /* Any EVEX encoded insns except for AVX512ER, AVX512PF,
12206 AVX512-4FMAPS, and AVX512-4VNNIW. */
12213 }
12214 #endif
12216 /* Tie dwarf2 debug info to the address at the start of the insn.
12217 We can't do this after the insn has been output as the current
12218 frag may have been closed off. eg. by frag_var. */
12225 {
12227 /* Branch can be 8 bytes. Leave some room for prefixes. */
12230 /* Align section to boundary. */
12233 /* Make room for padding. */
12236 /* Start of the padding. */
12248 }
12252 {
12255 }
12257 /* Output jumps. */
12265 else
12266 {
12267 /* Output normal instructions here. */
12277 {
12278 /* Encode lfence, mfence, and sfence as
12279 f0 83 04 24 00 lock addl $0x0, (%{re}sp). */
12286 {
12291 }
12292 else
12295 }
12297 /* Some processors fail on LOCK prefix. This options makes
12298 assembler ignore LOCK prefix and serves as a workaround. */
12300 {
12305 }
12308 /* Skip if this is a branch. */
12309 ;
12311 {
12312 /* Make room for padding. */
12325 }
12327 {
12330 /* Make room for padding. */
12341 }
12343 /* Since the VEX/EVEX prefix contains the implicit prefix, we
12344 don't need the explicit prefix. */
12346 {
12348 {
12362 {
12366 /* Check for pseudo prefixes. */
12375 }
12379 }
12381 #ifdef OBJ_ELF
12382 /* For x32, add a dummy REX_OPCODE prefix for mov/add with
12383 R_X86_64_GOTTPOFF relocation so that linker can safely
12384 perform IE->LE optimization. A dummy REX_OPCODE prefix
12385 is also needed for lea with R_X86_64_GOTPC32_TLSDESC
12386 relocation for GDesc -> IE/LE optimization. */
12394 #endif
12396 /* The prefix bytes. */
12402 {
12405 }
12406 }
12407 else
12408 {
12412 {
12418 /* There should be no other prefixes for instructions
12419 with VEX prefix. */
12421 }
12423 /* For EVEX instructions i.vrex should become 0 after
12424 build_evex_prefix. For VEX instructions upper 16 registers
12425 aren't available, so VREX should be 0. */
12428 /* Now the VEX prefix. */
12430 {
12434 }
12435 else
12437 }
12439 /* Now the opcode; be careful about word order here! */
12443 {
12455 }
12460 {
12462 }
12463 else
12464 {
12468 {
12473 }
12476 {
12478 /* Put out high byte first: can't use md_number_to_chars! */
12480 /* Fall through. */
12487 }
12489 }
12491 /* Now the modrm byte and sib byte (if present). */
12493 {
12497 /* If i.rm.regmem == ESP (4)
12498 && i.rm.mode != (Register mode)
12499 && not 16 bit
12500 ==> need second modrm byte. */
12507 }
12515 /*
12516 * frag_now_fix () returning plain abs_section_offset when we're in the
12517 * absolute section, and abs_section_offset not getting updated as data
12518 * gets added to the frag breaks the logic below.
12519 */
12521 {
12524 {
12527 j);
12528 else
12530 j);
12531 }
12533 {
12534 /* NB: Don't add prefix with GOTPC relocation since
12535 output_disp() above depends on the fixed encoding
12536 length. Can't add prefix with TLS relocation since
12537 it breaks TLS linker optimization. */
12539 /* Prefix count on the current instruction. */
12543 /* REX byte is encoded in VEX/EVEX prefix. */
12545 count++;
12547 /* Count prefixes for extended opcode maps. */
12550 {
12554 count++;
12562 }
12566 {
12567 /* Set the maximum prefix size in BRANCH_PREFIX
12568 frag. */
12573 else
12575 }
12576 else
12577 {
12578 /* Remember the maximum prefix size in FUSED_JCC_PADDING
12579 frag. */
12583 else
12588 }
12590 /* Use existing segment prefix if possible. Use CS
12591 segment prefix in 64-bit mode. In 32-bit mode, use SS
12592 segment prefix with ESP/EBP base register and use DS
12593 segment prefix without ESP/EBP base register. */
12602 else
12604 }
12605 }
12606 }
12608 /* NB: Don't work with COND_JUMP86 without i386. */
12612 {
12613 /* Terminate each frag so that we can add prefix and check for
12614 fused jcc. */
12617 }
12619 #ifdef DEBUG386
12621 {
12623 }
12625 }
12627 /* Return the size of the displacement operand N. */
12629 static int
12631 {
12641 }
12643 /* Return the size of the immediate operand N. */
12645 static int
12647 {
12656 }
12658 static void
12660 {
12665 {
12667 {
12673 {
12677 size);
12680 }
12681 else
12682 {
12692 /* We can't have 8 bit displacement here. */
12695 /* The PC relative address is computed relative
12696 to the instruction boundary, so in case immediate
12697 fields follows, we need to adjust the value. */
12699 {
12705 {
12706 /* Only one immediate is allowed for PC
12707 relative address, except with .insn. */
12710 }
12711 /* We should find at least one immediate. */
12714 }
12726 && ((symbol_get_value_expression
12730 {
12732 {
12737 }
12740 else
12741 /* Don't do the adjustment for x86-64, as there
12742 the pcrel addressing is relative to the _next_
12743 insn, and that is taken care of in other code. */
12745 }
12747 {
12749 {
12768 }
12769 }
12772 reloc_type);
12780 {
12781 /* Only "add %reg1, foo@gottpoff(%rip), %reg2" is
12782 allowed in md_assemble. Set fx_tcbit2 for EVEX
12783 prefix. */
12786 }
12789 {
12791 {
12792 /* Set fx_tcbit for REX2 prefix. */
12796 }
12797 }
12798 /* In 64-bit, i386_validate_fix updates only (%rip)
12799 relocations. */
12803 /* Check for "call/jmp *mem", "mov mem, %reg",
12804 "test %reg, mem" and "binop mem, %reg" where binop
12805 is one of adc, add, and, cmp, or, sbb, sub, xor
12806 instructions without data prefix. Always generate
12807 R_386_GOT32X for "sym*GOT" operand in 32-bit mode. */
12819 {
12821 {
12823 {
12824 /* Set fx_tcbit for REX2 prefix. */
12827 }
12829 {
12830 /* Set fx_tcbit3 for REX2 prefix. */
12835 else
12837 }
12838 }
12842 }
12843 }
12844 }
12845 }
12846 }
12848 static void
12850 {
12855 {
12857 {
12863 {
12864 offsetT val;
12867 size);
12870 }
12871 else
12872 {
12873 /* Not absolute_section.
12874 Need a 32-bit fixup (don't support 8bit
12875 non-absolute imms). Try to support other
12876 sizes ... */
12886 else
12892 /* This is tough to explain. We end up with this one if we
12893 * have operands that look like
12894 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
12895 * obtain the absolute address of the GOT, and it is strongly
12896 * preferable from a performance point of view to avoid using
12897 * a runtime relocation for this. The actual sequence of
12898 * instructions often look something like:
12899 *
12900 * call .L66
12901 * .L66:
12902 * popl %ebx
12903 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
12904 *
12905 * The call and pop essentially return the absolute address
12906 * of the label .L66 and store it in %ebx. The linker itself
12907 * will ultimately change the first operand of the addl so
12908 * that %ebx points to the GOT, but to keep things simple, the
12909 * .o file must have this operand set so that it generates not
12910 * the absolute address of .L66, but the absolute address of
12911 * itself. This allows the linker itself simply treat a GOTPC
12912 * relocation as asking for a pcrel offset to the GOT to be
12913 * added in, and the addend of the relocation is stored in the
12914 * operand field for the instruction itself.
12915 *
12916 * Our job here is to fix the operand so that it would add
12917 * the correct offset so that %ebx would point to itself. The
12918 * thing that is tricky is that .-.L66 will point to the
12919 * beginning of the instruction, so we need to further modify
12920 * the operand so that it will point to itself. There are
12921 * other cases where you have something like:
12922 *
12923 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
12924 *
12925 * and here no correction would be required. Internally in
12926 * the assembler we treat operands of this form as not being
12927 * pcrel since the '.' is explicitly mentioned, and I wonder
12928 * whether it would simplify matters to do it this way. Who
12929 * knows. In earlier versions of the PIC patches, the
12930 * pcrel_adjust field was used to store the correction, but
12931 * since the expression is not pcrel, I felt it would be
12932 * confusing to do it this way. */
12937 && GOT_symbol
12941 && ((symbol_get_value_expression
12944 {
12954 }
12957 }
12958 }
12959 }
12960 }
12961 \f
12962 /* x86_cons_fix_new is called via the expression parsing code when a
12963 reloc is needed. We use this hook to get the correct .got reloc. */
12966 void
12969 {
12972 #ifdef TE_PE
12974 {
12977 }
12980 #endif
12983 }
12985 /* Export the ABI address size for use by TC_ADDRESS_BYTES for the
12986 purpose of the `.dc.a' internal pseudo-op. */
12988 int
12990 {
12994 }
12996 #if (defined (OBJ_ELF) || defined (OBJ_MACH_O) || defined (TE_PE))
12997 /* Parse operands of the form
12998 <symbol>@GOTOFF+<nnn>
12999 and similar .plt or .got references.
13001 If we find one, set up the correct relocation in RELOC and copy the
13002 input string, minus the `@GOTOFF' into a malloc'd buffer for
13003 parsing by the calling routine. Return this buffer, and if ADJUST
13004 is non-null set it to the length of the string we removed from the
13005 input line. Otherwise return NULL. */
13010 {
13011 /* Some of the relocations depend on the size of what field is to
13012 be relocated. But in our callers i386_immediate and i386_displacement
13013 we don't yet know the operand size (this will be set by insn
13014 matching). Hence we record the word32 relocation here,
13015 and adjust the reloc according to the real size in reloc(). */
13024 {
13027 {
13029 {
13037 {
13039 {
13042 }
13043 else
13045 }
13050 /* The length of the first part of our input line. */
13053 /* The second part goes from after the reloc token until
13054 (and including) an end_of_line char or comma. */
13061 /* Allocate and copy string. The trailing NUL shouldn't
13062 be necessary, but be safe. */
13066 /* Replace the relocation token with ' ', so that
13067 errors like foo@GOTOFF1 will be detected. */
13069 else
13070 /* Increment length by 1 if the relocation token is
13071 removed. */
13072 len++;
13078 }
13083 }
13084 }
13086 /* Might be a symbol version string. Don't as_bad here. */
13088 }
13089 #else
13090 # define lex_got(reloc, adjust, types) NULL
13091 #endif
13093 bfd_reloc_code_real_type
13095 {
13102 #if defined (OBJ_ELF) || defined (TE_PE)
13104 {
13105 /* Handle @GOTOFF and the like in an expression. */
13118 {
13119 /* expression () has merrily parsed up to the end of line,
13120 or a comma - in the wrong buffer. Transfer how far
13121 input_line_pointer has moved to the right buffer. */
13122 input_line_pointer = (save
13131 {
13136 }
13140 {
13145 }
13146 }
13147 }
13148 else
13149 #endif
13157 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
13163 }
13165 static void
13167 {
13172 }
13174 static void
13176 {
13181 valueT val;
13192 {
13193 bad:
13199 }
13209 {
13212 }
13214 {
13220 {
13222 /* Arrange for build_vex_prefix() to emit 0x8f. */
13226 }
13227 }
13230 {
13233 }
13237 : evex
13241 {
13244 }
13250 {
13251 /* Only address size and segment override prefixes are permitted with
13252 VEX/XOP/EVEX encodings. */
13256 {
13261 {
13268 }
13269 }
13270 }
13273 {
13274 /* Length specifier (VEX.L, XOP.L, EVEX.L'L). */
13276 {
13279 {
13283 else
13290 else
13306 {
13309 else
13312 }
13314 }
13322 {
13325 else
13328 }
13333 {
13336 else
13339 }
13344 {
13347 }
13349 }
13350 }
13353 {
13354 /* embedded prefix (VEX.pp, XOP.pp, EVEX.pp). */
13356 {
13364 {
13367 }
13372 {
13375 }
13377 {
13380 }
13382 }
13383 }
13386 {
13387 /* Encoding space (VEX.mmmmm, EVEX.mmmm). */
13389 {
13394 {
13397 }
13401 {
13404 }
13409 {
13415 {
13418 }
13419 }
13421 }
13422 }
13425 {
13426 /* VEX.W, XOP.W, EVEX.W */
13428 {
13439 {
13442 }
13444 }
13448 }
13451 {
13452 /* Improve diagnostic a little. */
13456 }
13458 /* Before processing the opcode expression, find trailing "+r" or
13459 "/<digit>" specifiers. */
13461 {
13471 {
13476 }
13482 {
13488 }
13489 }
13502 /* Trim off a prefix if present. */
13504 {
13508 {
13516 }
13517 }
13519 /* Parse operands, if any, before evaluating encoding space. */
13521 {
13531 {
13534 }
13537 {
13541 }
13543 /* No need to distinguish encoding_evex and encoding_evex512. */
13546 }
13548 /* Trim off encoding space. */
13550 {
13556 {
13565 }
13568 }
13570 /* Arrange for build_vex_prefix() to properly emit 0xC4/0xC5.
13571 Also avoid hitting abort() there or in build_evex_prefix(). */
13576 {
13579 }
13582 /* Handle operands, if any. */
13584 {
13585 i386_operand_type combined;
13590 {
13592 {
13595 }
13598 else
13600 }
13602 /* Are we to emit ModR/M encoding? */
13613 {
13616 }
13618 /* Enforce certain constraints on operands. */
13621 {
13624 {
13627 }
13628 /* Fall through. */
13631 {
13634 }
13644 {
13647 }
13648 /* Fall through. */
13651 {
13655 }
13656 /* Fall through. */
13660 }
13662 /* Bring operands into canonical order (imm, mem, reg). */
13663 do
13664 {
13668 {
13673 {
13676 }
13677 }
13678 }
13681 /* For Intel syntax swap the order of register operands. */
13684 {
13691 /* Fall through. */
13699 }
13701 /* Enforce constraints when using VSIB. */
13706 {
13708 {
13711 }
13715 {
13716 /* We could allow two register operands, encoding the 2nd one in
13717 an 8-bit immediate like for 4-register-operand insns, but that
13718 would require ugly fiddling with process_operands() and/or
13719 build_modrm_byte(). */
13722 }
13725 }
13727 /* Establish operand size encoding. */
13731 {
13732 /* Look for 8-bit operands that use old registers. */
13745 {
13748 }
13751 {
13772 }
13780 }
13784 {
13790 }
13793 {
13800 }
13802 {
13804 {
13809 }
13813 }
13816 {
13818 {
13823 }
13824 }
13826 {
13828 {
13829 /* Do _not_ consider AVX512VL here. */
13836 }
13839 {
13843 {
13847 }
13858 {
13862 }
13863 }
13864 }
13874 /* Establish size for immediate operands. */
13876 {
13885 {
13888 else
13890 }
13894 {
13897 else
13899 }
13901 {
13904 /* Oddly enough imm_size() checks imm64 first, so the bit needs
13905 zapping since smallest_imm_type() sets it unconditionally. */
13907 {
13911 }
13914 }
13915 else
13916 /* Non-constant expressions are sized heuristically. */
13918 {
13922 }
13923 }
13929 }
13931 /* Don't set opcode until after processing operands, to avoid any
13932 potential special casing there. */
13943 {
13946 }
13949 {
13955 }
13957 {
13963 }
13964 else
13973 #ifdef OBJ_ELF
13974 /* PS: SCFI is enabled only for System V AMD64 ABI. The ABI check has been
13975 performed in i386_target_format. */
13978 #endif
13980 done:
13986 /* Make sure dot_insn() won't yield "true" anymore. */
13991 }
13993 #ifdef TE_PE
13994 static void
13996 {
13997 expressionS exp;
13999 do
14000 {
14006 }
14009 input_line_pointer--;
14011 }
14013 static void
14015 {
14016 expressionS exp;
14018 do
14019 {
14025 }
14028 input_line_pointer--;
14030 }
14031 #endif
14033 /* Handle Rounding Control / SAE specifiers. */
14037 {
14041 {
14043 {
14045 {
14048 }
14051 {
14061 }
14066 }
14067 }
14070 }
14072 /* Handle Vector operations. */
14076 {
14082 {
14085 {
14086 op_string++;
14088 op_string++;
14090 /* Check broadcasts. */
14092 {
14107 {
14109 op_string++;
14110 }
14113 {
14115 op_string++;
14116 }
14117 else
14118 {
14121 }
14122 op_string++;
14125 {
14135 }
14140 /* For .insn a data size specifier may be appended. */
14143 }
14144 /* Check .insn special cases. */
14146 {
14147 dot_insn_modifier:
14149 {
14165 /* This isn't really a "vector" operation, but a sign/size
14166 specifier for immediate operands of .insn. Note that AT&T
14167 syntax handles the same in i386_immediate(). */
14176 {
14181 }
14183 }
14184 }
14185 /* Check masking operation. */
14187 {
14191 /* k0 can't be used for write mask. */
14193 {
14197 }
14200 {
14203 }
14206 else
14207 {
14210 /* Only "{z}" is allowed here. No need to check
14211 zeroing mask explicitly. */
14213 {
14216 }
14217 }
14220 }
14221 /* Check zeroing-flag for masking operation. */
14223 {
14225 {
14229 }
14230 else
14231 {
14233 {
14234 duplicated_vec_op:
14237 }
14241 /* Only "{%k}" is allowed here. No need to check mask
14242 register explicitly. */
14244 {
14246 saved);
14248 }
14249 }
14251 op_string++;
14252 }
14256 else
14260 op_string++;
14262 {
14265 }
14266 op_string++;
14272 }
14273 unknown_vec_op:
14274 /* We don't know this one. */
14277 }
14280 {
14283 }
14286 }
14288 static int
14290 {
14295 i386_operand_type types;
14300 {
14302 MAX_IMMEDIATE_OPERANDS);
14304 }
14322 /* For .insn immediates there may be a size specifier. */
14325 {
14330 {
14335 }
14336 }
14344 {
14349 }
14352 {
14355 }
14358 }
14360 static int
14363 {
14365 {
14368 imm_start);
14370 }
14372 {
14373 /* Size it properly later. */
14376 /* If not 64bit, sign/zero extend val, to account for wraparound
14377 when !BFD64. */
14381 }
14382 #ifdef OBJ_AOUT
14389 {
14392 }
14393 #endif
14394 else
14395 {
14396 /* This is an address. The size of the address will be
14397 determined later, depending on destination register,
14398 suffix, or the default for the section. */
14405 types);
14406 }
14409 }
14413 {
14414 offsetT val;
14421 {
14435 {
14440 scale);
14444 }
14445 }
14447 {
14451 }
14455 }
14457 static int
14459 {
14469 {
14471 MAX_MEMORY_OPERANDS);
14473 }
14480 {
14484 {
14488 }
14491 else
14493 }
14494 else
14495 {
14496 /* For PC-relative branches, the width of the displacement may be
14497 dependent upon data size, but is never dependent upon address size.
14498 Also make sure to not unintentionally match against a non-PC-relative
14499 branch template. */
14504 {
14510 }
14515 {
14519 else
14521 }
14522 else
14523 {
14526 ? WORD_MNEM_SUFFIX
14530 {
14533 }
14534 }
14535 }
14537 bigdisp);
14546 #ifndef GCC_ASM_O_HACK
14547 #define GCC_ASM_O_HACK 0
14548 #endif
14549 #if GCC_ASM_O_HACK
14553 {
14554 /* This hack is to avoid a warning when using the "o"
14555 constraint within gcc asm statements.
14556 For instance:
14558 #define _set_tssldt_desc(n,addr,limit,type) \
14559 __asm__ __volatile__ ( \
14560 "movw %w2,%0\n\t" \
14561 "movw %w1,2+%0\n\t" \
14562 "rorl $16,%1\n\t" \
14563 "movb %b1,4+%0\n\t" \
14564 "movb %4,5+%0\n\t" \
14565 "movb $0,6+%0\n\t" \
14566 "movb %h1,7+%0\n\t" \
14567 "rorl $16,%1" \
14568 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
14570 This works great except that the output assembler ends
14571 up looking a bit weird if it turns out that there is
14572 no offset. You end up producing code that looks like:
14574 #APP
14575 movw $235,(%eax)
14576 movw %dx,2+(%eax)
14577 rorl $16,%edx
14578 movb %dl,4+(%eax)
14579 movb $137,5+(%eax)
14580 movb $0,6+(%eax)
14581 movb %dh,7+(%eax)
14582 rorl $16,%edx
14583 #NO_APP
14585 So here we provide the missing zero. */
14588 }
14589 #endif
14600 #if GCC_ASM_O_HACK
14602 #endif
14605 {
14610 }
14617 }
14619 static int
14622 {
14625 /* We do this to make sure that the section symbol is in
14626 the symbol table. We will ultimately change the relocation
14627 to be relative to the beginning of the section. */
14631 {
14645 else
14647 }
14652 {
14653 inv_disp:
14655 disp_start);
14657 }
14660 {
14661 /* Sizing gets taken care of by optimize_disp().
14663 If not 64bit, sign/zero extend val, to account for wraparound
14664 when !BFD64. */
14668 }
14670 #ifdef OBJ_AOUT
14677 {
14680 }
14681 #endif
14686 /* Check if this is a displacement only operand. */
14693 }
14695 /* Return the active addressing mode, taking address override and
14696 registers forming the address into consideration. Update the
14697 address override prefix if necessary. */
14699 static enum flag_code
14701 {
14708 /* Avoid replacing the "16-bit addressing not allowed" diagnostic
14709 from md_assemble() by "is not a valid base/index expression"
14710 when there is a base and/or index. */
14712 {
14713 /* MPX insn memory operands with neither base nor index must be forced
14714 to use 32-bit addressing in 16-bit mode. */
14720 }
14721 else
14722 {
14725 #if INFER_ADDR_PREFIX
14727 {
14728 /* Infer address prefix from the first memory operand. */
14735 {
14743 {
14746 /* Change the size of any displacement too. At most one
14747 of Disp16 or Disp32 is set.
14748 FIXME. There doesn't seem to be any real need for
14749 separate Disp16 and Disp32 flags. The same goes for
14750 Imm16 and Imm32. Removing them would probably clean
14751 up the code quite a lot. */
14755 {
14758 };
14762 }
14763 }
14764 }
14765 }
14766 #endif
14767 }
14770 }
14772 /* Make sure the memory operand we've been dealt is valid.
14773 Return 1 on success, 0 on a failure. */
14775 static int
14777 {
14783 {
14784 /* Memory operands of string insns are special in that they only allow
14785 a single register (rDI, rSI, or rBX) as their memory address. */
14788 {
14792 };
14798 {
14806 expected_reg
14809 }
14810 else
14811 expected_reg
14817 {
14818 /* The second memory operand must have the same size as
14819 the first one. */
14830 operand_string,
14832 register_prefix,
14836 }
14837 else
14840 bad_address:
14844 }
14845 else
14846 {
14850 {
14851 /* 32-bit/64-bit checks. */
14853 {
14854 bad_disp:
14858 }
14876 /* bndmk, bndldx, bndstx and mandatory non-vector SIB have special restrictions. */
14881 {
14882 /* They cannot use RIP-relative addressing. */
14884 {
14887 }
14889 /* bndldx and bndstx ignore their scale factor. */
14893 }
14894 }
14895 else
14896 {
14897 /* 16-bit checks. */
14912 }
14913 }
14915 }
14917 /* Handle vector immediates. */
14919 static int
14921 {
14927 pstr++;
14929 pstr++;
14936 pstr++;
14939 {
14942 }
14945 {
14948 }
14950 /* Internally this doesn't count as an operand. */
14954 }
14957 {
14961 }
14963 /* Parse OPERAND_STRING into the i386_insn structure I. Returns zero
14964 on error. */
14966 static int
14968 {
14976 /* We check for an absolute prefix (differentiating,
14977 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
14980 {
14985 }
14987 /* Check if operand is a register. */
14989 {
14990 i386_operand_type temp;
14995 /* Check for a segment override by searching for ':' after a
14996 segment register. */
15001 {
15004 /* Skip the ':' and whitespace. */
15009 /* Handle case of %es:*foo. */
15012 {
15017 }
15020 {
15023 }
15025 }
15027 /* Handle vector operations. */
15029 {
15033 }
15036 {
15039 }
15041 /* Reject pseudo registers for .insn. */
15043 {
15047 }
15052 temp);
15057 /* A GPR may follow an RC or SAE immediate only if a (vector) register
15058 operand was also present earlier on. */
15061 {
15070 }
15071 }
15073 {
15076 }
15078 {
15081 {
15084 }
15088 {
15092 }
15093 }
15095 {
15096 /* If it is a RC or SAE immediate, do the necessary placement check:
15097 Only another immediate or a GPR may precede it. */
15101 {
15105 }
15106 }
15108 {
15109 /* This is a memory reference of some sort. */
15112 /* Start and end of displacement string expression (if found). */
15116 do_memory_reference:
15117 /* Check for base index form. We detect the base index form by
15118 looking for an ')' at the end of the operand, searching
15119 for the '(' matching it, and finding a REGISTER_PREFIX or ','
15120 after the '('. */
15123 /* Handle vector operations. */
15129 {
15133 {
15149 }
15152 {
15155 }
15159 }
15161 /* If we only have a displacement, set-up for it to be parsed later. */
15166 {
15171 /* We've already checked that the number of left & right ()'s are
15172 equal, and that there's a matching set of double quotes. */
15175 {
15181 {
15186 }
15187 }
15191 /* Skip past '(' and whitespace. */
15200 {
15206 {
15212 }
15214 /* There may be an index reg or scale factor here. */
15216 {
15223 {
15230 {
15234 }
15236 {
15239 operand_string);
15241 }
15242 }
15244 {
15250 }
15252 /* Check for scale factor. */
15254 {
15264 {
15267 operand_string);
15269 }
15270 }
15272 {
15277 }
15278 }
15280 {
15283 operand_string);
15285 }
15286 }
15288 {
15294 }
15295 }
15297 /* If there's an expression beginning the operand, parse it,
15298 assuming displacement_string_start and
15299 displacement_string_end are meaningful. */
15301 {
15303 displacement_string_end))
15305 }
15307 /* Special case for (%dx) while doing input/output op. */
15315 {
15321 }
15327 }
15328 else
15329 {
15330 /* It's not a memory operand; argh! */
15334 op_string);
15336 }
15338 }
15339 \f
15340 /* Calculate the maximum variable size (i.e., excluding fr_fix)
15341 that an rs_machine_dependent frag may reach. */
15343 unsigned int
15345 {
15346 /* The only relaxable frags are for jumps.
15347 Unconditional jumps can grow by 4 bytes and others by 5 bytes. */
15350 }
15352 #ifdef OBJ_ELF
15353 static int
15355 {
15356 /* STT_GNU_IFUNC symbol must go through PLT. */
15362 /* Symbol may be weak or local. */
15365 /* Global symbols with non-default visibility can't be preempted. */
15371 {
15374 /* Symbol with PLT relocation may be preempted. */
15378 }
15380 /* Global symbols with default visibility in a shared library may be
15381 preempted by another definition. */
15383 }
15384 #endif
15386 /* Table 3-2. Macro-Fusible Instructions in Haswell Microarchitecture
15387 Note also work for Skylake and Cascadelake.
15388 ---------------------------------------------------------------------
15389 | JCC | ADD/SUB/CMP | INC/DEC | TEST/AND |
15390 | ------ | ----------- | ------- | -------- |
15391 | Jo | N | N | Y |
15392 | Jno | N | N | Y |
15393 | Jc/Jb | Y | N | Y |
15394 | Jae/Jnb | Y | N | Y |
15395 | Je/Jz | Y | Y | Y |
15396 | Jne/Jnz | Y | Y | Y |
15397 | Jna/Jbe | Y | N | Y |
15398 | Ja/Jnbe | Y | N | Y |
15399 | Js | N | N | Y |
15400 | Jns | N | N | Y |
15401 | Jp/Jpe | N | N | Y |
15402 | Jnp/Jpo | N | N | Y |
15403 | Jl/Jnge | Y | Y | Y |
15404 | Jge/Jnl | Y | Y | Y |
15405 | Jle/Jng | Y | Y | Y |
15406 | Jg/Jnle | Y | Y | Y |
15407 --------------------------------------------------------------------- */
15408 static int
15410 {
15420 }
15422 /* Return the next non-empty frag. */
15426 {
15427 /* There may be a frag with a ".fill 0" when there is no room in
15428 the current frag for frag_grow in output_insn. */
15434 ;
15436 }
15438 /* Return the next jcc frag after BRANCH_PADDING. */
15442 {
15450 {
15458 }
15461 }
15463 /* Classify BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags. */
15465 static void
15467 {
15477 /* First scan for BRANCH_PADDING and FUSED_JCC_PADDING. Convert
15478 FUSED_JCC_PADDING and merge BRANCH_PADDING. */
15482 {
15486 {
15488 /* The BRANCH_PADDING frag must be followed by a branch
15489 frag. */
15494 /* Check if this is a fused jcc:
15495 FUSED_JCC_PADDING
15496 CMP like instruction
15497 BRANCH_PADDING
15498 COND_JUMP
15499 */
15504 {
15505 /* The BRANCH_PADDING frag is merged with the
15506 FUSED_JCC_PADDING frag. */
15508 /* CMP like instruction size. */
15511 /* Skip to branch_fragP. */
15513 }
15515 {
15516 /* Turn FUSED_JCC_PADDING into BRANCH_PREFIX if it isn't
15517 a fused jcc. */
15518 next_fragP->fr_subtype
15522 /* This will be updated in the BRANCH_PREFIX scan. */
15524 }
15525 else
15528 }
15529 }
15531 /* Stop if there is no BRANCH_PREFIX. */
15535 /* Scan for BRANCH_PREFIX. */
15537 {
15543 /* Count all BRANCH_PREFIX frags before BRANCH_PADDING and
15544 COND_JUMP_PREFIX. */
15549 {
15551 /* Skip rs_fill frags. */
15554 /* Stop for all other frags. */
15557 /* rs_machine_dependent frags. */
15560 {
15561 /* Count BRANCH_PREFIX frags. */
15563 {
15566 }
15567 else
15568 max_prefix_length
15570 }
15575 {
15576 /* Stop at BRANCH_PADDING and FUSED_JCC_PADDING. */
15579 }
15580 else
15581 /* Stop for other rs_machine_dependent frags. */
15583 }
15587 /* Skip to the next frag. */
15589 }
15590 }
15592 /* Compute padding size for
15594 FUSED_JCC_PADDING
15595 CMP like instruction
15596 BRANCH_PADDING
15597 COND_JUMP/UNCOND_JUMP
15599 or
15601 BRANCH_PADDING
15602 COND_JUMP/UNCOND_JUMP
15603 */
15605 static int
15607 {
15611 /* The start address of the BRANCH_PADDING or FUSED_JCC_PADDING frag. */
15616 /* CMP like instrunction size. */
15619 /* The base size of the branch frag. */
15622 /* Add opcode and displacement bytes for the rs_machine_dependent
15623 branch frag. */
15627 /* Check if branch is within boundary and doesn't end at the last
15628 byte. */
15631 /* Padding needed to avoid crossing boundary. */
15633 else
15634 /* No padding needed. */
15637 /* The return value may be saved in tc_frag_data.length which is
15638 unsigned byte. */
15643 }
15645 /* i386_generic_table_relax_frag()
15647 Handle BRANCH_PADDING, BRANCH_PREFIX and FUSED_JCC_PADDING frags to
15648 grow/shrink padding to align branch frags. Hand others to
15649 relax_frag(). */
15651 long
15653 {
15656 {
15660 /* When the BRANCH_PREFIX frag is used, the computed address
15661 must match the actual address and there should be no padding. */
15667 /* Update the padding size. */
15672 }
15674 {
15680 /* Use the padding set by the leading BRANCH_PREFIX frag. */
15684 /* Compute the relative address of the padding frag in the very
15685 first time where the BRANCH_PREFIX frag sizes are zero. */
15690 /* First update the last length from the previous interation. */
15698 {
15700 {
15703 {
15707 else
15711 }
15712 }
15713 else
15715 }
15717 /* Check the padding size for the padding frag. */
15718 padding_size = i386_branch_padding_size
15723 /* Check if there is change from the last interation. */
15725 {
15726 /* Update the expected address of the padding frag. */
15731 }
15734 {
15735 /* No padding if there is no sufficient room. Clear the
15736 expected address of the padding frag. */
15739 }
15740 else
15741 /* Store the expected address of the padding frag. */
15748 /* Update the length for the current interation. */
15756 {
15758 {
15761 {
15765 else
15769 }
15770 }
15771 else
15773 }
15777 }
15779 }
15781 /* md_estimate_size_before_relax()
15783 Called just before relax() for rs_machine_dependent frags. The x86
15784 assembler uses these frags to handle variable size jump
15785 instructions.
15787 Any symbol that is now undefined will not become defined.
15788 Return the correct fr_subtype in the frag.
15789 Return the initial "guess for variable size of frag" to caller.
15790 The guess is actually the growth beyond the fixed part. Whatever
15791 we do to grow the fixed or variable part contributes to our
15792 returned value. */
15794 int
15796 {
15800 {
15803 }
15805 /* We've already got fragP->fr_subtype right; all we have to do is
15806 check for un-relaxable symbols. On an ELF system, we can't relax
15807 an externally visible symbol, because it may be overridden by a
15808 shared library. */
15810 #ifdef OBJ_ELF
15813 #endif
15814 #if defined (OBJ_COFF) && defined (TE_PE)
15816 #endif
15817 )
15818 {
15819 /* Symbol is undefined in this segment, or we need to keep a
15820 reloc so that weak symbols can be overridden. */
15831 #ifdef OBJ_ELF
15836 #endif
15837 else
15844 {
15846 /* Make jmp (0xeb) a (d)word displacement jump. */
15852 reloc_type);
15858 {
15859 /* Negate the condition, and branch past an
15860 unconditional jump. */
15863 /* Insert an unconditional jump. */
15865 /* We added two extra opcode bytes, and have a two byte
15866 offset. */
15871 reloc_type);
15873 }
15874 /* Fall through. */
15878 {
15883 BFD_RELOC_8_PCREL);
15886 }
15888 /* This changes the byte-displacement jump 0x7N
15889 to the (d)word-displacement jump 0x0f,0x8N. */
15892 /* We've added an opcode byte. */
15897 reloc_type);
15903 }
15905 /* All jumps handled here are signed, but don't unconditionally use a
15906 signed limit check for 32 and 16 bit jumps as we want to allow wrap
15907 around at 4G (outside of 64-bit mode) and 64k. */
15913 }
15915 /* Guess size depending on current relax state. Initially the relax
15916 state will correspond to a short jump and we return 1, because
15917 the variable part of the frag (the branch offset) is one byte
15918 long. However, we can relax a section more than once and in that
15919 case we must either set fr_subtype back to the unrelaxed state,
15920 or return the value for the appropriate branch. */
15922 }
15924 /* Called after relax() is finished.
15926 In: Address of frag.
15927 fr_type == rs_machine_dependent.
15928 fr_subtype is what the address relaxed to.
15930 Out: Any fixSs and constants are set up.
15931 Caller will turn frag into a ".space 0". */
15933 void
15936 {
15939 offsetT target_address;
15940 offsetT opcode_address;
15942 offsetT displacement_from_opcode_start;
15947 {
15948 /* Generate nop padding. */
15951 {
15956 {
15963 {
15966 {
15988 }
15992 else
15995 }
15996 else
15997 {
16001 }
16005 {
16026 }
16032 }
16036 else
16040 }
16042 }
16046 /* Address we want to reach in file space. */
16049 /* Address opcode resides at in file space. */
16052 /* Displacement from opcode start to fill into instruction. */
16056 {
16057 /* Don't have to change opcode. */
16060 }
16061 else
16062 {
16069 {
16108 }
16109 }
16111 /* If size if less then four we are sure that the operand fits,
16112 but if it's 4, then it could be that the displacement is larger
16113 then -/+ 2GB. */
16115 && object_64bit
16119 {
16122 /* Make us emit 0. */
16124 }
16125 /* Now put displacement after opcode. */
16130 }
16131 \f
16132 /* Apply a fixup (fixP) to segment data, once it has been determined
16133 by our caller that we have all the info we need to fix it up.
16135 Parameter valP is the pointer to the value of the bits.
16137 On the 386, immediates, displacements, and data pointers are all in
16138 the same (little-endian) format, so we don't need to care about which
16139 we are handling. */
16141 void
16143 {
16147 #if !defined (TE_Mach)
16149 {
16151 {
16168 }
16169 }
16177 {
16178 /* This is a hack. There should be a better way to handle this.
16179 This covers for the fact that bfd_install_relocation will
16180 subtract the current location (for partial_inplace, PC relative
16181 relocations); see more below. */
16182 #if defined (OBJ_ELF) || defined (TE_PE)
16184 #endif
16185 #ifdef OBJ_ELF
16192 {
16193 /* Yes, we add the values in twice. This is because
16194 bfd_install_relocation subtracts them out again. I think
16195 bfd_install_relocation is broken, but I don't dare change
16196 it. FIXME. */
16198 }
16199 #endif
16200 #if defined (OBJ_COFF) && defined (TE_PE)
16201 /* For some reason, the PE format does not store a
16202 section address offset for a PC relative symbol. */
16206 #endif
16207 }
16208 #if defined (OBJ_COFF) && defined (TE_PE)
16211 /* PR 16858: Do not modify weak function references. */
16213 {
16214 #if !defined (TE_PEP)
16215 /* For x86 PE weak function symbols are neither PC-relative
16216 nor do they set S_IS_FUNCTION. So the only reliable way
16217 to detect them is to check the flags of their containing
16218 section. */
16221 ;
16222 else
16223 #endif
16225 }
16226 #endif
16228 /* Fix a few things - the dynamic linker expects certain values here,
16229 and we must not disappoint it. */
16230 #ifdef OBJ_ELF
16233 {
16236 /* Make the jump instruction point to the address of the operand.
16237 At runtime we merely add the offset to the actual PLT entry.
16238 NB: Subtract the offset size only for jump instructions. */
16257 /* Fallthrough */
16282 }
16285 /* If not 64bit, massage value, to account for wraparound when !BFD64. */
16292 /* Are we finished with this relocation now? */
16294 {
16297 {
16304 }
16305 }
16306 #if defined (OBJ_COFF) && defined (TE_PE)
16308 {
16310 /* Remember value for tc_gen_reloc. */
16312 /* Clear out the frag for now. */
16314 }
16315 #endif
16317 {
16320 /* Remember value for tc_gen_reloc. */
16323 }
16326 }
16327 \f
16330 {
16331 /* This outputs the LITTLENUMs in REVERSE order;
16332 in accord with the bigendian 386. */
16334 }
16335 \f
16340 {
16344 else
16348 }
16350 /* Verify that @r can be used in the current context. */
16353 {
16378 {
16384 {
16390 }
16391 }
16394 {
16398 /* Don't update pp when not dealing with insn operands. */
16400 {
16411 }
16412 }
16425 /* Don't allow fake index register unless allow_index_reg isn't 0. */
16429 /* Upper 16 vector registers are only available with VREX in 64bit
16430 mode, and require EVEX encoding. */
16432 {
16437 /* Don't update pp when not dealing with insn operands. */
16439 {
16450 }
16451 }
16454 {
16459 /* Don't update pp when not dealing with insn operands. */
16461 {
16472 }
16473 }
16487 }
16489 /* REG_STRING starts *before* REGISTER_PREFIX. */
16493 {
16499 /* Skip possible REGISTER_PREFIX and possible whitespace. */
16508 {
16511 s++;
16512 }
16521 /* Handle floating point regs, allowing spaces in the (i) part. */
16523 {
16533 {
16538 {
16544 {
16548 }
16549 }
16550 /* We have "%st(" then garbage. */
16552 }
16553 }
16556 }
16558 /* REG_STRING starts *before* REGISTER_PREFIX. */
16562 {
16567 else
16570 {
16579 {
16585 }
16587 {
16591 {
16596 }
16598 {
16602 }
16603 }
16606 }
16608 }
16610 int
16612 {
16616 /* We only know the terminating character here. It being double quote could
16617 be the closing one of a quoted symbol name, or an opening one from a
16618 following string (or another quoted symbol name). Since the latter can't
16619 be valid syntax for anything, bailing in either case is good enough. */
16627 {
16633 }
16637 }
16639 void
16641 {
16646 {
16650 {
16654 }
16662 {
16668 }
16669 else
16670 {
16673 }
16675 }
16676 }
16678 #ifdef BFD64
16679 /* To maintain consistency with !BFD64 builds of gas record, whether any
16680 (binary) operator was involved in an expression. As expressions are
16681 evaluated in only 32 bits when !BFD64, we use this to decide whether to
16682 truncate results. */
16686 {
16691 {
16692 /* Since the expression parser applies unary operators fine to bignum
16693 operands, we don't need to be concerned of respective operands not
16694 fitting in 32 bits. */
16698 }
16699 /* This isn't entirely right: The pattern can also result when constant
16700 expressions are folded (e.g. 0xffffffff + 1). */
16711 }
16712 #endif
16713 \f
16714 #ifdef OBJ_ELF
16716 #else
16718 #endif
16720 #define OPTION_32 (OPTION_MD_BASE + 0)
16721 #define OPTION_64 (OPTION_MD_BASE + 1)
16722 #define OPTION_DIVIDE (OPTION_MD_BASE + 2)
16723 #define OPTION_MARCH (OPTION_MD_BASE + 3)
16724 #define OPTION_MTUNE (OPTION_MD_BASE + 4)
16725 #define OPTION_MMNEMONIC (OPTION_MD_BASE + 5)
16726 #define OPTION_MSYNTAX (OPTION_MD_BASE + 6)
16727 #define OPTION_MINDEX_REG (OPTION_MD_BASE + 7)
16728 #define OPTION_MNAKED_REG (OPTION_MD_BASE + 8)
16729 #define OPTION_MRELAX_RELOCATIONS (OPTION_MD_BASE + 9)
16730 #define OPTION_MSSE2AVX (OPTION_MD_BASE + 10)
16731 #define OPTION_MSSE_CHECK (OPTION_MD_BASE + 11)
16732 #define OPTION_MOPERAND_CHECK (OPTION_MD_BASE + 12)
16733 #define OPTION_MAVXSCALAR (OPTION_MD_BASE + 13)
16734 #define OPTION_X32 (OPTION_MD_BASE + 14)
16735 #define OPTION_MADD_BND_PREFIX (OPTION_MD_BASE + 15)
16736 #define OPTION_MEVEXLIG (OPTION_MD_BASE + 16)
16737 #define OPTION_MEVEXWIG (OPTION_MD_BASE + 17)
16738 #define OPTION_MBIG_OBJ (OPTION_MD_BASE + 18)
16739 #define OPTION_MOMIT_LOCK_PREFIX (OPTION_MD_BASE + 19)
16740 #define OPTION_MEVEXRCIG (OPTION_MD_BASE + 20)
16741 #define OPTION_MSHARED (OPTION_MD_BASE + 21)
16742 #define OPTION_MAMD64 (OPTION_MD_BASE + 22)
16743 #define OPTION_MINTEL64 (OPTION_MD_BASE + 23)
16744 #define OPTION_MFENCE_AS_LOCK_ADD (OPTION_MD_BASE + 24)
16745 #define OPTION_X86_USED_NOTE (OPTION_MD_BASE + 25)
16746 #define OPTION_MVEXWIG (OPTION_MD_BASE + 26)
16747 #define OPTION_MALIGN_BRANCH_BOUNDARY (OPTION_MD_BASE + 27)
16748 #define OPTION_MALIGN_BRANCH_PREFIX_SIZE (OPTION_MD_BASE + 28)
16749 #define OPTION_MALIGN_BRANCH (OPTION_MD_BASE + 29)
16750 #define OPTION_MBRANCHES_WITH_32B_BOUNDARIES (OPTION_MD_BASE + 30)
16751 #define OPTION_MLFENCE_AFTER_LOAD (OPTION_MD_BASE + 31)
16752 #define OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH (OPTION_MD_BASE + 32)
16753 #define OPTION_MLFENCE_BEFORE_RET (OPTION_MD_BASE + 33)
16754 #define OPTION_MUSE_UNALIGNED_VECTOR_MOVE (OPTION_MD_BASE + 34)
16755 #define OPTION_MTLS_CHECK (OPTION_MD_BASE + 35)
16758 {
16760 #if (defined (OBJ_ELF) || defined (TE_PE) || defined (OBJ_MACH_O)) \
16761 && defined (BFD64)
16763 #endif
16764 #ifdef OBJ_ELF
16765 # ifdef BFD64
16767 # endif
16770 #endif
16787 # if defined (TE_PE) || defined (TE_PEP)
16789 #endif
16800 OPTION_MLFENCE_BEFORE_INDIRECT_BRANCH},
16806 };
16809 int
16811 {
16816 {
16825 #ifdef OBJ_ELF
16826 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
16827 should be emitted or not. FIXME: Not implemented. */
16833 /* -V: SVR4 argument to print version ID. */
16838 /* -k: Ignore for FreeBSD compatibility. */
16843 /* -s: On i386 Solaris, this tells the native assembler to use
16844 .stab instead of .stab.excl. We always use .stab anyhow. */
16856 else
16859 #endif
16861 #ifdef BFD64
16863 #if (defined (OBJ_ELF) || defined (TE_PE) || defined (OBJ_MACH_O))
16865 {
16875 {
16878 }
16882 }
16884 #endif
16886 #ifdef OBJ_ELF
16888 {
16894 {
16897 }
16901 }
16903 #endif
16908 {
16915 {
16918 }
16922 }
16926 #ifdef SVR4_COMMENT_CHARS
16927 {
16938 }
16939 #endif
16945 /* Allow -march=+nosse. */
16947 arch++;
16948 do
16949 {
16961 {
16967 {
16968 /* Processor. */
16982 }
16986 {
16987 /* ISA extension. */
16991 {
16997 {
17004 {
17011 }
17013 }
17014 /* Fall through. */
17018 }
17021 }
17022 }
17025 {
17026 /* Disable an ISA extension. */
17030 {
17035 }
17036 }
17042 }
17051 {
17054 {
17058 }
17059 }
17069 else
17078 else
17106 else
17117 else
17126 else
17135 else
17150 else
17163 else
17172 else
17176 # if defined (TE_PE) || defined (TE_PEP)
17180 #endif
17187 else
17196 else
17205 else
17211 {
17215 }
17222 else
17224 arg);
17236 else
17238 arg);
17246 else
17251 {
17255 {
17257 {
17260 }
17262 {
17268 /* Limit alignment power to 31. */
17270 {
17273 }
17274 }
17275 }
17277 }
17281 {
17284 /* Some processors only support 5 prefixes. */
17286 {
17289 }
17291 arg);
17292 }
17299 do
17300 {
17316 else
17319 }
17327 align_branch = (align_branch_jcc_bit
17328 | align_branch_fused_bit
17342 {
17344 /* Turn off -Os. */
17346 }
17348 {
17350 /* Turn on all encoding optimizations. */
17352 }
17353 else
17354 {
17356 /* Turn off -Os. */
17358 }
17365 else
17371 }
17373 }
17375 #define MESSAGE_TEMPLATE \
17376 " "
17381 {
17385 /* Reserve 2 spaces for ", " or ",\0" */
17388 /* Check if there is any room. */
17390 {
17392 {
17395 }
17397 }
17398 else
17399 {
17400 /* Output the current message now and start a new one. */
17410 }
17414 }
17416 static void
17418 {
17432 {
17439 }
17442 {
17443 /* Should it be skipped? */
17450 {
17451 /* It is an extension. Skip if we aren't asked to show it. */
17454 }
17456 {
17457 /* It is an processor. Skip if we show only extension. */
17459 }
17461 {
17462 /* It is an impossible processor - skip. */
17464 }
17467 }
17469 /* Display disabled extensions. */
17472 {
17482 }
17486 }
17488 void
17490 {
17491 #ifdef OBJ_ELF
17496 #endif
17501 #ifdef OBJ_ELF
17504 #endif
17505 #ifdef BFD64
17506 # ifdef OBJ_ELF
17509 # elif defined (TE_PE) || defined (TE_PEP) || defined (OBJ_MACH_O)
17512 # endif
17513 #endif
17514 #ifdef SVR4_COMMENT_CHARS
17517 #else
17520 #endif
17566 else
17579 #ifdef OBJ_ELF
17586 else
17590 #endif
17591 #if defined (TE_PE) || defined (TE_PEP)
17594 #endif
17606 else
17610 #ifdef OBJ_ELF
17615 else
17619 #endif
17647 }
17649 #if (defined (OBJ_ELF) || defined (TE_PE) || defined (OBJ_MACH_O))
17651 /* Pick the target format to use. */
17655 {
17657 {
17659 #ifdef OBJ_ELF
17662 else
17664 #endif
17665 }
17669 {
17672 {
17682 }
17685 cpu_arch_name);
17686 }
17687 else
17690 #ifdef OBJ_ELF
17693 #endif
17699 {
17700 #ifdef TE_PE
17703 {
17706 }
17708 #endif
17709 #ifdef OBJ_ELF
17711 {
17715 {
17718 #ifndef TE_SOLARIS
17720 #endif
17725 #ifndef TE_SOLARIS
17727 #endif
17733 #ifndef TE_SOLARIS
17735 #endif
17739 }
17741 {
17745 }
17746 else
17748 }
17749 #endif
17750 #if defined (OBJ_MACH_O)
17753 {
17757 }
17758 else
17760 #endif
17764 }
17765 }
17768 \f
17769 symbolS *
17771 {
17776 {
17778 {
17783 };
17785 }
17787 }
17789 #ifdef OBJ_AOUT
17790 /* Round up a section size to the appropriate boundary. */
17792 valueT
17794 {
17795 /* For a.out, force the section size to be aligned. If we don't do
17796 this, BFD will align it for us, but it will not write out the
17797 final bytes of the section. This may be a bug in BFD, but it is
17798 easier to fix it here since that is how the other a.out targets
17799 work. */
17803 }
17804 #endif
17806 /* On the i386, PC-relative offsets are relative to the start of the
17807 next instruction. That is, the address of the offset, plus its
17808 size, since the offset is always the last part of the insn. */
17810 long
17812 {
17814 }
17816 #ifdef OBJ_AOUT
17818 static void
17820 {
17826 }
17828 #endif
17830 /* Remember constant directive. */
17832 void
17834 {
17839 {
17843 }
17844 }
17846 int
17848 {
17850 {
17858 }
17860 #ifdef OBJ_ELF
17867 /* BFD_RELOC_X86_64_GOTTPOFF:
17868 1. fx_tcbit -> BFD_RELOC_X86_64_CODE_4_GOTTPOFF
17869 2. fx_tcbit2 -> BFD_RELOC_X86_64_CODE_6_GOTTPOFF
17870 BFD_RELOC_X86_64_GOTPC32_TLSDESC:
17871 1. fx_tcbit -> BFD_RELOC_X86_64_CODE_4_GOTPC32_TLSDESC
17872 BFD_RELOC_32_PCREL:
17873 1. fx_tcbit -> BFD_RELOC_X86_64_GOTPCRELX
17874 2. fx_tcbit2 -> BFD_RELOC_X86_64_REX_GOTPCRELX
17875 3. fx_tcbit3 -> BFD_RELOC_X86_64_CODE_4_GOTPCRELX
17876 4. else -> BFD_RELOC_X86_64_GOTPCREL
17877 */
17879 {
17884 }
17888 #endif
17891 {
17893 {
17895 {
17898 #ifdef OBJ_ELF
17905 else
17906 #endif
17908 }
17909 else
17910 {
17913 else
17915 }
17917 }
17918 }
17919 #ifdef OBJ_ELF
17920 else
17921 {
17922 /* NB: Commit 292676c1 resolved PLT32 reloc aganst local symbol
17923 to section. Since PLT32 relocation must be against symbols,
17924 turn such PLT32 relocation into PC32 relocation. NB: We can
17925 turn PLT32 relocation into PC32 relocation only for PC-relative
17926 relocations since non-PC-relative relocations need PLT entries.
17927 */
17935 {
17939 }
17940 }
17941 #endif
17944 }
17946 arelent *
17948 {
17950 bfd_reloc_code_real_type code;
17953 {
17954 #ifdef OBJ_ELF
17969 else
17972 {
17973 /* Resolve size relocation against local symbol to size of
17974 the symbol plus addend. */
17980 {
17984 }
17989 && object_64bit
17997 }
17999 {
18003 }
18004 #endif
18005 /* Fall through. */
18050 #ifdef TE_PE
18053 #endif
18058 {
18059 /* Don't turn BFD_RELOC_X86_64_32S into BFD_RELOC_32. */
18062 }
18063 /* Fall through. */
18066 {
18068 {
18078 #ifdef BFD64
18080 #endif
18081 }
18082 }
18083 else
18084 {
18086 {
18096 #ifdef BFD64
18098 #endif
18099 }
18100 }
18102 }
18107 && GOT_symbol
18109 {
18112 else
18114 }
18116 && GOT_symbol
18118 {
18120 }
18129 {
18130 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
18131 vtable entry to be used in the relocation's section offset. */
18134 #if defined (OBJ_COFF) && defined (TE_PE)
18137 else
18138 #endif
18140 }
18141 /* Use the rela in 64bit mode. */
18142 else
18143 {
18146 {
18162 }
18166 else
18168 {
18191 }
18192 }
18196 {
18200 /* Set howto to a garbage value so that we can keep going. */
18203 }
18206 }
18210 void
18212 {
18227 {
18230 {
18235 }
18236 }
18237 }
18239 void
18241 {
18244 }
18246 int
18248 {
18249 #ifdef OBJ_ELF
18252 #endif
18254 }
18256 #ifdef TE_PE
18257 void
18259 {
18260 expressionS exp;
18266 }
18267 #endif
18269 #ifdef OBJ_ELF
18270 int
18272 {
18279 }
18281 void
18283 {
18290 /* Find the (or make a) list entry to save state into. */
18295 {
18300 }
18303 /* Find the list entry to load state from. */
18309 else
18312 }
18314 #ifdef TE_SOLARIS
18315 void
18317 {
18320 }
18321 #endif
18323 /* For ELF on x86-64, add support for SHF_X86_64_LARGE. */
18325 bfd_vma
18327 {
18329 {
18334 }
18335 else
18338 }
18340 static void
18342 {
18344 {
18347 }
18348 else
18349 {
18355 {
18356 flagword applicable;
18360 /* The .lbss section is for local .largecomm symbols. */
18367 }
18376 }
18377 }