1 @c Copyright (C) 1991-2024 Free Software Foundation, Inc.
2 @c This is part of the GAS manual.
3 @c For copying conditions, see the file as.texinfo.
9 @chapter 80386 Dependent Features
12 @node Machine Dependencies
13 @chapter 80386 Dependent Features
17 @cindex i80386 support
18 @cindex x86-64 support
20 The i386 version @code{@value{AS}} supports both the original Intel 386
21 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture
22 extending the Intel architecture to 64-bits.
25 * i386-Options:: Options
26 * i386-Directives:: X86 specific directives
27 * i386-Syntax:: Syntactical considerations
28 * i386-Mnemonics:: Instruction Naming
29 * i386-Regs:: Register Naming
30 * i386-Prefixes:: Instruction Prefixes
31 * i386-Memory:: Memory References
32 * i386-Jumps:: Handling of Jump Instructions
33 * i386-Float:: Floating Point
34 * i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations
35 * i386-LWP:: AMD's Lightweight Profiling Instructions
36 * i386-BMI:: Bit Manipulation Instruction
37 * i386-TBM:: AMD's Trailing Bit Manipulation Instructions
38 * i386-16bit:: Writing 16-bit Code
39 * i386-Arch:: Specifying an x86 CPU architecture
40 * i386-ISA:: AMD64 ISA vs. Intel64 ISA
41 * i386-Bugs:: AT&T Syntax bugs
48 @cindex options for i386
49 @cindex options for x86-64
51 @cindex x86-64 options
53 The i386 version of @code{@value{AS}} has a few machine
58 @cindex @samp{--32} option, i386
59 @cindex @samp{--32} option, x86-64
60 @cindex @samp{--x32} option, i386
61 @cindex @samp{--x32} option, x86-64
62 @cindex @samp{--64} option, i386
63 @cindex @samp{--64} option, x86-64
64 @item --32 | --x32 | --64
65 Select the word size, either 32 bits or 64 bits. @samp{--32}
66 implies Intel i386 architecture, while @samp{--x32} and @samp{--64}
67 imply AMD x86-64 architecture with 32-bit or 64-bit word-size
70 These options are only available with the ELF object file format, and
71 require that the necessary BFD support has been included (on a 32-bit
72 platform you have to add --enable-64-bit-bfd to configure enable 64-bit
73 usage and use x86-64 as target platform).
76 By default, x86 GAS replaces multiple nop instructions used for
77 alignment within code sections with multi-byte nop instructions such
78 as leal 0(%esi,1),%esi. This switch disables the optimization if a single
79 byte nop (0x90) is explicitly specified as the fill byte for alignment.
81 @cindex @samp{--divide} option, i386
83 On SVR4-derived platforms, the character @samp{/} is treated as a comment
84 character, which means that it cannot be used in expressions. The
85 @samp{--divide} option turns @samp{/} into a normal character. This does
86 not disable @samp{/} at the beginning of a line starting a comment, or
87 affect using @samp{#} for starting a comment.
89 @cindex @samp{-march=} option, i386
90 @cindex @samp{-march=} option, x86-64
91 @item -march=@var{CPU}[+@var{EXTENSION}@dots{}]
92 This option specifies the target processor. The assembler will
93 issue an error message if an attempt is made to assemble an instruction
94 which will not execute on the target processor. The following
95 processor names are recognized:
134 In addition to the basic instruction set, the assembler can be told to
135 accept various extension mnemonics. For example,
136 @code{-march=i686+sse4+vmx} extends @var{i686} with @var{sse4} and
137 @var{vmx}. The following extensions are currently supported:
190 @code{avx512_4fmaps},
191 @code{avx512_4vnniw},
192 @code{avx512_vpopcntdq},
195 @code{avx512_bitalg},
196 @code{avx512_vp2intersect},
203 @code{avx_vnni_int8},
207 @code{avx_ne_convert},
211 @code{avx_vnni_int16},
281 Note that these extension mnemonics can be prefixed with @code{no} to revoke
282 the respective (and any dependent) functionality. Note further that the
283 suffixes permitted on @code{-march=avx10.<N>} enforce a vector length
284 restriction, i.e. despite these otherwise being "enabling" options, using
285 these suffixes will disable all insns with wider vector or mask register
288 When the @code{.arch} directive is used with @option{-march}, the
289 @code{.arch} directive will take precedent.
291 @cindex @samp{-mtune=} option, i386
292 @cindex @samp{-mtune=} option, x86-64
293 @item -mtune=@var{CPU}
294 This option specifies a processor to optimize for. When used in
295 conjunction with the @option{-march} option, only instructions
296 of the processor specified by the @option{-march} option will be
299 Valid @var{CPU} values are identical to the processor list of
300 @option{-march=@var{CPU}}.
302 @cindex @samp{-moperand-check=} option, i386
303 @cindex @samp{-moperand-check=} option, x86-64
304 @item -moperand-check=@var{none}
305 @itemx -moperand-check=@var{warning}
306 @itemx -moperand-check=@var{error}
307 These options control if the assembler should check certain instruction
308 operands or operand combinations. An example instructions where operand size
309 cannot be inferred from its operands and also hasn't been specified by way of
310 an instruction suffix.
311 @option{-moperand-check=@var{none}} will make the assembler not perform
312 these checks. @option{-moperand-check=@var{warning}} will make the assembler
313 issue a warning when respective checks fail, which is the default.
314 @option{-moperand-check=@var{error}} will make the assembler issue an error
315 when respective checks fail.
317 @cindex @samp{-msse2avx} option, i386
318 @cindex @samp{-msse2avx} option, x86-64
320 This option specifies that the assembler should encode SSE instructions
321 with VEX prefix, requiring AVX to be available. SSE instructions using
322 extended GPRs will be encoded with EVEX prefix, requiring AVX512 or AVX10 to
325 @cindex @samp{-muse-unaligned-vector-move} option, i386
326 @cindex @samp{-muse-unaligned-vector-move} option, x86-64
327 @item -muse-unaligned-vector-move
328 This option specifies that the assembler should encode aligned vector
329 move as unaligned vector move.
331 @cindex @samp{-msse-check=} option, i386
332 @cindex @samp{-msse-check=} option, x86-64
333 @item -msse-check=@var{none}
334 @itemx -msse-check=@var{warning}
335 @itemx -msse-check=@var{error}
336 These options control if the assembler should check SSE instructions.
337 @option{-msse-check=@var{none}} will make the assembler not to check SSE
338 instructions, which is the default. @option{-msse-check=@var{warning}}
339 will make the assembler issue a warning for any SSE instruction.
340 @option{-msse-check=@var{error}} will make the assembler issue an error
341 for any SSE instruction.
343 @cindex @samp{-mavxscalar=} option, i386
344 @cindex @samp{-mavxscalar=} option, x86-64
345 @item -mavxscalar=@var{128}
346 @itemx -mavxscalar=@var{256}
347 These options control how the assembler should encode scalar AVX
348 instructions. @option{-mavxscalar=@var{128}} will encode scalar
349 AVX instructions with 128bit vector length, which is the default.
350 @option{-mavxscalar=@var{256}} will encode scalar AVX instructions
351 with 256bit vector length.
353 WARNING: Don't use this for production code - due to CPU errata the
354 resulting code may not work on certain models.
356 @cindex @samp{-mvexwig=} option, i386
357 @cindex @samp{-mvexwig=} option, x86-64
358 @item -mvexwig=@var{0}
359 @itemx -mvexwig=@var{1}
360 These options control how the assembler should encode VEX.W-ignored (WIG)
361 VEX instructions. @option{-mvexwig=@var{0}} will encode WIG VEX
362 instructions with vex.w = 0, which is the default.
363 @option{-mvexwig=@var{1}} will encode WIG EVEX instructions with
366 WARNING: Don't use this for production code - due to CPU errata the
367 resulting code may not work on certain models.
369 @cindex @samp{-mevexlig=} option, i386
370 @cindex @samp{-mevexlig=} option, x86-64
371 @item -mevexlig=@var{128}
372 @itemx -mevexlig=@var{256}
373 @itemx -mevexlig=@var{512}
374 These options control how the assembler should encode length-ignored
375 (LIG) EVEX instructions. @option{-mevexlig=@var{128}} will encode LIG
376 EVEX instructions with 128bit vector length, which is the default.
377 @option{-mevexlig=@var{256}} and @option{-mevexlig=@var{512}} will
378 encode LIG EVEX instructions with 256bit and 512bit vector length,
381 @cindex @samp{-mevexwig=} option, i386
382 @cindex @samp{-mevexwig=} option, x86-64
383 @item -mevexwig=@var{0}
384 @itemx -mevexwig=@var{1}
385 These options control how the assembler should encode w-ignored (WIG)
386 EVEX instructions. @option{-mevexwig=@var{0}} will encode WIG
387 EVEX instructions with evex.w = 0, which is the default.
388 @option{-mevexwig=@var{1}} will encode WIG EVEX instructions with
391 @cindex @samp{-mmnemonic=} option, i386
392 @cindex @samp{-mmnemonic=} option, x86-64
393 @item -mmnemonic=@var{att}
394 @itemx -mmnemonic=@var{intel}
395 This option specifies instruction mnemonic for matching instructions.
396 The @code{.att_mnemonic} and @code{.intel_mnemonic} directives will
399 @cindex @samp{-msyntax=} option, i386
400 @cindex @samp{-msyntax=} option, x86-64
401 @item -msyntax=@var{att}
402 @itemx -msyntax=@var{intel}
403 This option specifies instruction syntax when processing instructions.
404 The @code{.att_syntax} and @code{.intel_syntax} directives will
407 @cindex @samp{-mnaked-reg} option, i386
408 @cindex @samp{-mnaked-reg} option, x86-64
410 This option specifies that registers don't require a @samp{%} prefix.
411 The @code{.att_syntax} and @code{.intel_syntax} directives will take precedent.
413 @cindex @samp{-madd-bnd-prefix} option, i386
414 @cindex @samp{-madd-bnd-prefix} option, x86-64
415 @item -madd-bnd-prefix
416 This option forces the assembler to add BND prefix to all branches, even
417 if such prefix was not explicitly specified in the source code.
419 @cindex @samp{-mshared} option, i386
420 @cindex @samp{-mshared} option, x86-64
422 On ELF target, the assembler normally optimizes out non-PLT relocations
423 against defined non-weak global branch targets with default visibility.
424 The @samp{-mshared} option tells the assembler to generate code which
425 may go into a shared library where all non-weak global branch targets
426 with default visibility can be preempted. The resulting code is
427 slightly bigger. This option only affects the handling of branch
430 @cindex @samp{-mbig-obj} option, i386
431 @cindex @samp{-mbig-obj} option, x86-64
433 On PE/COFF target this option forces the use of big object file
434 format, which allows more than 32768 sections.
436 @cindex @samp{-momit-lock-prefix=} option, i386
437 @cindex @samp{-momit-lock-prefix=} option, x86-64
438 @item -momit-lock-prefix=@var{no}
439 @itemx -momit-lock-prefix=@var{yes}
440 These options control how the assembler should encode lock prefix.
441 This option is intended as a workaround for processors, that fail on
442 lock prefix. This option can only be safely used with single-core,
443 single-thread computers
444 @option{-momit-lock-prefix=@var{yes}} will omit all lock prefixes.
445 @option{-momit-lock-prefix=@var{no}} will encode lock prefix as usual,
446 which is the default.
448 @cindex @samp{-mfence-as-lock-add=} option, i386
449 @cindex @samp{-mfence-as-lock-add=} option, x86-64
450 @item -mfence-as-lock-add=@var{no}
451 @itemx -mfence-as-lock-add=@var{yes}
452 These options control how the assembler should encode lfence, mfence and
454 @option{-mfence-as-lock-add=@var{yes}} will encode lfence, mfence and
455 sfence as @samp{lock addl $0x0, (%rsp)} in 64-bit mode and
456 @samp{lock addl $0x0, (%esp)} in 32-bit mode.
457 @option{-mfence-as-lock-add=@var{no}} will encode lfence, mfence and
458 sfence as usual, which is the default.
460 @cindex @samp{-mrelax-relocations=} option, i386
461 @cindex @samp{-mrelax-relocations=} option, x86-64
462 @item -mrelax-relocations=@var{no}
463 @itemx -mrelax-relocations=@var{yes}
464 These options control whether the assembler should generate relax
465 relocations, R_386_GOT32X, in 32-bit mode, or R_X86_64_GOTPCRELX and
466 R_X86_64_REX_GOTPCRELX, in 64-bit mode.
467 @option{-mrelax-relocations=@var{yes}} will generate relax relocations.
468 @option{-mrelax-relocations=@var{no}} will not generate relax
469 relocations. The default can be controlled by a configure option
470 @option{--enable-x86-relax-relocations}.
472 @cindex @samp{-mtls-check=} option, i386
473 @cindex @samp{-mtls-check=} option, x86-64
474 @item -mtls-check=@var{no}
475 @itemx -mtls-check=@var{yes}
476 These options control whether the assembler check tls relocation.
477 @option{-mtls-check=@var{yes}} will check tls relocation.
478 @option{-mtls-check=@var{no}} will not check tls relocation
479 The default can be controlled by a configure option
480 @option{--enable-x86-tls-check}.
482 @cindex @samp{-malign-branch-boundary=} option, i386
483 @cindex @samp{-malign-branch-boundary=} option, x86-64
484 @item -malign-branch-boundary=@var{NUM}
485 This option controls how the assembler should align branches with segment
486 prefixes or NOP. @var{NUM} must be a power of 2. It should be 0 or
487 no less than 16. Branches will be aligned within @var{NUM} byte
488 boundary. @option{-malign-branch-boundary=0}, which is the default,
489 doesn't align branches.
491 @cindex @samp{-malign-branch=} option, i386
492 @cindex @samp{-malign-branch=} option, x86-64
493 @item -malign-branch=@var{TYPE}[+@var{TYPE}...]
494 This option specifies types of branches to align. @var{TYPE} is
495 combination of @samp{jcc}, which aligns conditional jumps,
496 @samp{fused}, which aligns fused conditional jumps, @samp{jmp},
497 which aligns unconditional jumps, @samp{call} which aligns calls,
498 @samp{ret}, which aligns rets, @samp{indirect}, which aligns indirect
499 jumps and calls. The default is @option{-malign-branch=jcc+fused+jmp}.
501 @cindex @samp{-malign-branch-prefix-size=} option, i386
502 @cindex @samp{-malign-branch-prefix-size=} option, x86-64
503 @item -malign-branch-prefix-size=@var{NUM}
504 This option specifies the maximum number of prefixes on an instruction
505 to align branches. @var{NUM} should be between 0 and 5. The default
508 @cindex @samp{-mbranches-within-32B-boundaries} option, i386
509 @cindex @samp{-mbranches-within-32B-boundaries} option, x86-64
510 @item -mbranches-within-32B-boundaries
511 This option aligns conditional jumps, fused conditional jumps and
512 unconditional jumps within 32 byte boundary with up to 5 segment prefixes
513 on an instruction. It is equivalent to
514 @option{-malign-branch-boundary=32}
515 @option{-malign-branch=jcc+fused+jmp}
516 @option{-malign-branch-prefix-size=5}.
517 The default doesn't align branches.
519 @cindex @samp{-mlfence-after-load=} option, i386
520 @cindex @samp{-mlfence-after-load=} option, x86-64
521 @item -mlfence-after-load=@var{no}
522 @itemx -mlfence-after-load=@var{yes}
523 These options control whether the assembler should generate lfence
524 after load instructions. @option{-mlfence-after-load=@var{yes}} will
525 generate lfence. @option{-mlfence-after-load=@var{no}} will not generate
526 lfence, which is the default.
528 @cindex @samp{-mlfence-before-indirect-branch=} option, i386
529 @cindex @samp{-mlfence-before-indirect-branch=} option, x86-64
530 @item -mlfence-before-indirect-branch=@var{none}
531 @item -mlfence-before-indirect-branch=@var{all}
532 @item -mlfence-before-indirect-branch=@var{register}
533 @itemx -mlfence-before-indirect-branch=@var{memory}
534 These options control whether the assembler should generate lfence
535 before indirect near branch instructions.
536 @option{-mlfence-before-indirect-branch=@var{all}} will generate lfence
537 before indirect near branch via register and issue a warning before
538 indirect near branch via memory.
539 It also implicitly sets @option{-mlfence-before-ret=@var{shl}} when
540 there's no explicit @option{-mlfence-before-ret=}.
541 @option{-mlfence-before-indirect-branch=@var{register}} will generate
542 lfence before indirect near branch via register.
543 @option{-mlfence-before-indirect-branch=@var{memory}} will issue a
544 warning before indirect near branch via memory.
545 @option{-mlfence-before-indirect-branch=@var{none}} will not generate
546 lfence nor issue warning, which is the default. Note that lfence won't
547 be generated before indirect near branch via register with
548 @option{-mlfence-after-load=@var{yes}} since lfence will be generated
549 after loading branch target register.
551 @cindex @samp{-mlfence-before-ret=} option, i386
552 @cindex @samp{-mlfence-before-ret=} option, x86-64
553 @item -mlfence-before-ret=@var{none}
554 @item -mlfence-before-ret=@var{shl}
555 @item -mlfence-before-ret=@var{or}
556 @item -mlfence-before-ret=@var{yes}
557 @itemx -mlfence-before-ret=@var{not}
558 These options control whether the assembler should generate lfence
559 before ret. @option{-mlfence-before-ret=@var{or}} will generate
560 generate or instruction with lfence.
561 @option{-mlfence-before-ret=@var{shl/yes}} will generate shl instruction
562 with lfence. @option{-mlfence-before-ret=@var{not}} will generate not
563 instruction with lfence. @option{-mlfence-before-ret=@var{none}} will not
564 generate lfence, which is the default.
566 @cindex @samp{-mx86-used-note=} option, i386
567 @cindex @samp{-mx86-used-note=} option, x86-64
568 @item -mx86-used-note=@var{no}
569 @itemx -mx86-used-note=@var{yes}
570 These options control whether the assembler should generate
571 GNU_PROPERTY_X86_ISA_1_USED and GNU_PROPERTY_X86_FEATURE_2_USED
572 GNU property notes. The default can be controlled by the
573 @option{--enable-x86-used-note} configure option.
575 @cindex @samp{-mevexrcig=} option, i386
576 @cindex @samp{-mevexrcig=} option, x86-64
577 @item -mevexrcig=@var{rne}
578 @itemx -mevexrcig=@var{rd}
579 @itemx -mevexrcig=@var{ru}
580 @itemx -mevexrcig=@var{rz}
581 These options control how the assembler should encode SAE-only
582 EVEX instructions. @option{-mevexrcig=@var{rne}} will encode RC bits
583 of EVEX instruction with 00, which is the default.
584 @option{-mevexrcig=@var{rd}}, @option{-mevexrcig=@var{ru}}
585 and @option{-mevexrcig=@var{rz}} will encode SAE-only EVEX instructions
586 with 01, 10 and 11 RC bits, respectively.
588 @cindex @samp{-mamd64} option, x86-64
589 @cindex @samp{-mintel64} option, x86-64
592 This option specifies that the assembler should accept only AMD64 or
593 Intel64 ISA in 64-bit mode. The default is to accept common, Intel64
596 @cindex @samp{-O0} option, i386
597 @cindex @samp{-O0} option, x86-64
598 @cindex @samp{-O} option, i386
599 @cindex @samp{-O} option, x86-64
600 @cindex @samp{-O1} option, i386
601 @cindex @samp{-O1} option, x86-64
602 @cindex @samp{-O2} option, i386
603 @cindex @samp{-O2} option, x86-64
604 @cindex @samp{-Os} option, i386
605 @cindex @samp{-Os} option, x86-64
606 @item -O0 | -O | -O1 | -O2 | -Os
607 Optimize instruction encoding with smaller instruction size. @samp{-O}
608 and @samp{-O1} encode 64-bit register load instructions with 64-bit
609 immediate as 32-bit register load instructions with 31-bit or 32-bits
610 immediates, encode 64-bit register clearing instructions with 32-bit
611 register clearing instructions, encode 256-bit/512-bit VEX/EVEX vector
612 register clearing instructions with 128-bit VEX vector register
613 clearing instructions, encode 128-bit/256-bit EVEX vector
614 register load/store instructions with VEX vector register load/store
615 instructions, and encode 128-bit/256-bit EVEX packed integer logical
616 instructions with 128-bit/256-bit VEX packed integer logical.
618 @samp{-O2} includes @samp{-O1} optimization plus encodes
619 256-bit/512-bit EVEX vector register clearing instructions with 128-bit
620 EVEX vector register clearing instructions. In 64-bit mode VEX encoded
621 instructions with commutative source operands will also have their
622 source operands swapped if this allows using the 2-byte VEX prefix form
623 instead of the 3-byte one. Certain forms of AND as well as OR with the
624 same (register) operand specified twice will also be changed to TEST.
626 @samp{-Os} includes @samp{-O2} optimization plus encodes 16-bit, 32-bit
627 and 64-bit register tests with immediate as 8-bit register test with
628 immediate. @samp{-O0} turns off this optimization.
633 @node i386-Directives
634 @section x86 specific Directives
636 @cindex machine directives, x86
637 @cindex x86 machine directives
640 @cindex @code{lcomm} directive, COFF
641 @item .lcomm @var{symbol} , @var{length}[, @var{alignment}]
642 Reserve @var{length} (an absolute expression) bytes for a local common
643 denoted by @var{symbol}. The section and value of @var{symbol} are
644 those of the new local common. The addresses are allocated in the bss
645 section, so that at run-time the bytes start off zeroed. Since
646 @var{symbol} is not declared global, it is normally not visible to
647 @code{@value{LD}}. The optional third parameter, @var{alignment},
648 specifies the desired alignment of the symbol in the bss section.
650 This directive is only available for COFF based x86 targets.
652 @cindex @code{largecomm} directive, ELF
653 @item .largecomm @var{symbol} , @var{length}[, @var{alignment}]
654 This directive behaves in the same way as the @code{comm} directive
655 except that the data is placed into the @var{.lbss} section instead of
656 the @var{.bss} section @ref{Comm}.
658 The directive is intended to be used for data which requires a large
659 amount of space, and it is only available for ELF based x86_64
662 @cindex @code{value} directive
663 @item .value @var{expression} [, @var{expression}]
664 This directive behaves in the same way as the @code{.short} directive,
665 taking a series of comma separated expressions and storing them as
666 two-byte wide values into the current section.
668 @cindex @code{insn} directive
669 @item .insn [@var{prefix}[,...]] [@var{encoding}] @var{major-opcode}[@code{+r}|@code{/@var{extension}}] [,@var{operand}[,...]]
670 This directive allows composing instructions which @code{@value{AS}}
671 may not know about yet, or which it has no way of expressing (which
672 can be the case for certain alternative encodings). It assumes certain
673 basic structure in how operands are encoded, and it also only
674 recognizes - with a few extensions as per below - operands otherwise
675 valid for instructions. Therefore there is no guarantee that
676 everything can be expressed (e.g. the original Intel Xeon Phi's MVEX
677 encodings cannot be expressed).
681 @var{prefix} expresses one or more opcode prefixes in the usual way.
682 Legacy encoding prefixes altering meaning (0x66, 0xF2, 0xF3) may be
683 specified as high byte of <major-opcode> (perhaps already including an
684 encoding space prefix). Note that there can only be one such prefix.
685 Segment overrides are better specified in the respective memory
686 operand, as long as there is one.
689 @var{encoding} is used to specify VEX, XOP, or EVEX encodings. The
690 syntax tries to resemble that used in documentation:
692 @item @code{VEX}[@code{.@var{len}}][@code{.@var{prefix}}][@code{.@var{space}}][@code{.@var{w}}]
693 @item @code{EVEX}[@code{.@var{len}}][@code{.@var{prefix}}][@code{.@var{space}}][@code{.@var{w}}]
694 @item @code{XOP}@var{space}[@code{.@var{len}}][@code{.@var{prefix}}][@code{.@var{w}}]
699 @item @var{len} can be @code{LIG}, @code{128}, @code{256}, or (EVEX
700 only) @code{512} as well as @code{L0} / @code{L1} for VEX / XOP and
701 @code{L0}...@code{L3} for EVEX
702 @item @var{prefix} can be @code{NP}, @code{66}, @code{F3}, or @code{F2}
703 @item @var{space} can be
705 @item @code{0f}, @code{0f38}, @code{0f3a}, or @code{M0}...@code{M31}
707 @item @code{08}...@code{1f} for XOP
708 @item @code{0f}, @code{0f38}, @code{0f3a}, or @code{M0}...@code{M15}
711 @item @var{w} can be @code{WIG}, @code{W0}, or @code{W1}
716 @item Omitted @var{len} means "infer from operand size" if there is at
717 least one sized vector operand, or @code{LIG} otherwise. (Obviously
718 @var{len} has to be omitted when there's EVEX rounding control
719 specified later in the operands.)
720 @item Omitted @var{prefix} means @code{NP}.
721 @item Omitted @var{space} (VEX/EVEX only) implies encoding space is
722 taken from @var{major-opcode}.
723 @item Omitted @var{w} means "infer from GPR operand size" in 64-bit
724 code if there is at least one GPR(-like) operand, or @code{WIG}
729 @var{major-opcode} is an absolute expression specifying the instruction
730 opcode. Legacy encoding prefixes altering encoding space (0x0f,
731 0x0f38, 0x0f3a) have to be specified as high byte(s) here.
732 "Degenerate" ModR/M bytes, as present in e.g. certain FPU opcodes or
733 sub-spaces like that of major opcode 0x0f01, generally want encoding as
734 immediate operand (such opcodes wouldn't normally have non-immediate
735 operands); in some cases it may be possible to also encode these as low
736 byte of the major opcode, but there are potential ambiguities. Also
737 note that after stripping encoding prefixes, the residual has to fit in
738 two bytes (16 bits). @code{+r} can be suffixed to the major opcode
739 expression to specify register-only encoding forms not using a ModR/M
740 byte. @code{/@var{extension}} can alternatively be suffixed to the
741 major opcode expression to specify an extension opcode, encoded in bits
742 3-5 of the ModR/M byte.
745 @var{operand} is an instruction operand expressed the usual way.
746 Register operands are primarily used to express register numbers as
747 encoded in ModR/M byte and REX/VEX/XOP/EVEX prefixes. In certain
748 cases the register type (really: size) is also used to derive other
749 encoding attributes, if these aren't specified explicitly. Note that
750 there is no consistency checking among operands, so entirely bogus
751 mixes of operands are possible. Note further that only operands
752 actually encoded in the instruction should be specified. Operands like
753 @samp{%cl} in shift/rotate instructions have to be omitted, or else
754 they'll be encoded as an ordinary (register) operand. Operand order
755 may also not match that of the actual instruction (see below).
758 Encoding of operands: While for a memory operand (of which there can be
759 only one) it is clear how to encode it in the resulting ModR/M byte,
760 register operands are encoded strictly in this order (operand counts do
761 not include immediate ones in the enumeration below, and if there was an
762 extension opcode specified it counts as a register operand; VEX.vvvv
763 is meant to cover XOP and EVEX as well):
766 @item VEX.vvvv for 1-register-operand VEX/XOP/EVEX insns,
767 @item ModR/M.rm, ModR/M.reg for 2-operand insns,
768 @item ModR/M.rm, VEX.vvvv, ModR/M.reg for 3-operand insns, and
769 @item Imm@{4,5@}, ModR/M.rm, VEX.vvvv, ModR/M.reg for 4-operand insns,
772 obviously with the ModR/M.rm slot skipped when there is a memory
773 operand, and obviously with the ModR/M.reg slot skipped when there is
774 an extension opcode. For Intel syntax of course the opposite order
775 applies. With @code{+r} (and hence no ModR/M) there can only be a
776 single register operand for legacy encodings. VEX and alike can have
777 two register operands, where the second (first in Intel syntax) would
780 Immediate operands (including immediate-like displacements, i.e. when
781 not part of ModR/M addressing) are emitted in the order specified,
782 regardless of AT&T or Intel syntax. Since it may not be possible to
783 infer the size of such immediates, they can be suffixed by
784 @code{@{:s@var{n}@}} or @code{@{:u@var{n}@}}, representing signed /
785 unsigned immediates of the given number of bits respectively. When
786 emitting such operands, the number of bits will be rounded up to the
787 smallest suitable of 8, 16, 32, or 64. Immediates wider than 32 bits
788 are permitted in 64-bit code only.
790 For EVEX encoding memory operands with a displacement need to know
791 Disp8 scaling size in order to use an 8-bit displacement. For many
792 instructions this can be inferred from the types of other operands
793 specified. In Intel syntax @samp{DWORD PTR} and alike can be used to
794 specify the respective size. In AT&T syntax the memory operands can
795 be suffixed by @code{@{:d@var{n}@}} to specify the size (in bytes).
796 This can be combined with an embedded broadcast specifier:
797 @samp{8(%eax)@{1to8:d8@}}.
799 @cindex @code{noopt} directive
801 Disable instruction size optimization.
803 @c FIXME: Document other x86 specific directives ? Eg: .code16gcc,
808 @section i386 Syntactical Considerations
810 * i386-Variations:: AT&T Syntax versus Intel Syntax
811 * i386-Chars:: Special Characters
814 @node i386-Variations
815 @subsection AT&T Syntax versus Intel Syntax
817 @cindex i386 intel_syntax pseudo op
818 @cindex intel_syntax pseudo op, i386
819 @cindex i386 att_syntax pseudo op
820 @cindex att_syntax pseudo op, i386
821 @cindex i386 syntax compatibility
822 @cindex syntax compatibility, i386
823 @cindex x86-64 intel_syntax pseudo op
824 @cindex intel_syntax pseudo op, x86-64
825 @cindex x86-64 att_syntax pseudo op
826 @cindex att_syntax pseudo op, x86-64
827 @cindex x86-64 syntax compatibility
828 @cindex syntax compatibility, x86-64
830 @code{@value{AS}} now supports assembly using Intel assembler syntax.
831 @code{.intel_syntax} selects Intel mode, and @code{.att_syntax} switches
832 back to the usual AT&T mode for compatibility with the output of
833 @code{@value{GCC}}. Either of these directives may have an optional
834 argument, @code{prefix}, or @code{noprefix} specifying whether registers
835 require a @samp{%} prefix. AT&T System V/386 assembler syntax is quite
836 different from Intel syntax. We mention these differences because
837 almost all 80386 documents use Intel syntax. Notable differences
838 between the two syntaxes are:
840 @cindex immediate operands, i386
841 @cindex i386 immediate operands
842 @cindex register operands, i386
843 @cindex i386 register operands
844 @cindex jump/call operands, i386
845 @cindex i386 jump/call operands
846 @cindex operand delimiters, i386
848 @cindex immediate operands, x86-64
849 @cindex x86-64 immediate operands
850 @cindex register operands, x86-64
851 @cindex x86-64 register operands
852 @cindex jump/call operands, x86-64
853 @cindex x86-64 jump/call operands
854 @cindex operand delimiters, x86-64
857 AT&T immediate operands are preceded by @samp{$}; Intel immediate
858 operands are undelimited (Intel @samp{push 4} is AT&T @samp{pushl $4}).
859 AT&T register operands are preceded by @samp{%}; Intel register operands
860 are undelimited. AT&T absolute (as opposed to PC relative) jump/call
861 operands are prefixed by @samp{*}; they are undelimited in Intel syntax.
863 @cindex i386 source, destination operands
864 @cindex source, destination operands; i386
865 @cindex x86-64 source, destination operands
866 @cindex source, destination operands; x86-64
868 AT&T and Intel syntax use the opposite order for source and destination
869 operands. Intel @samp{add eax, 4} is @samp{addl $4, %eax}. The
870 @samp{source, dest} convention is maintained for compatibility with
871 previous Unix assemblers. Note that @samp{bound}, @samp{invlpga}, and
872 instructions with 2 immediate operands, such as the @samp{enter}
873 instruction, do @emph{not} have reversed order. @ref{i386-Bugs}.
875 @cindex mnemonic suffixes, i386
876 @cindex sizes operands, i386
877 @cindex i386 size suffixes
878 @cindex mnemonic suffixes, x86-64
879 @cindex sizes operands, x86-64
880 @cindex x86-64 size suffixes
882 In AT&T syntax the size of memory operands is determined from the last
883 character of the instruction mnemonic. Mnemonic suffixes of @samp{b},
884 @samp{w}, @samp{l} and @samp{q} specify byte (8-bit), word (16-bit), long
885 (32-bit) and quadruple word (64-bit) memory references. Mnemonic suffixes
886 of @samp{x}, @samp{y} and @samp{z} specify xmm (128-bit vector), ymm
887 (256-bit vector) and zmm (512-bit vector) memory references, only when there's
888 no other way to disambiguate an instruction. Intel syntax accomplishes this by
889 prefixing memory operands (@emph{not} the instruction mnemonics) with
890 @samp{byte ptr}, @samp{word ptr}, @samp{dword ptr}, @samp{qword ptr},
891 @samp{xmmword ptr}, @samp{ymmword ptr} and @samp{zmmword ptr}. Thus, Intel
892 syntax @samp{mov al, byte ptr @var{foo}} is @samp{movb @var{foo}, %al} in AT&T
893 syntax. In Intel syntax, @samp{fword ptr}, @samp{tbyte ptr} and
894 @samp{oword ptr} specify 48-bit, 80-bit and 128-bit memory references.
896 In 64-bit code, @samp{movabs} can be used to encode the @samp{mov}
897 instruction with the 64-bit displacement or immediate operand.
899 @cindex return instructions, i386
900 @cindex i386 jump, call, return
901 @cindex return instructions, x86-64
902 @cindex x86-64 jump, call, return
904 Immediate form long jumps and calls are
905 @samp{lcall/ljmp $@var{section}, $@var{offset}} in AT&T syntax; the
907 @samp{call/jmp far @var{section}:@var{offset}}. Also, the far return
909 is @samp{lret $@var{stack-adjust}} in AT&T syntax; Intel syntax is
910 @samp{ret far @var{stack-adjust}}.
912 @cindex sections, i386
913 @cindex i386 sections
914 @cindex sections, x86-64
915 @cindex x86-64 sections
917 The AT&T assembler does not provide support for multiple section
918 programs. Unix style systems expect all programs to be single sections.
922 @subsection Special Characters
924 @cindex line comment character, i386
925 @cindex i386 line comment character
926 The presence of a @samp{#} appearing anywhere on a line indicates the
927 start of a comment that extends to the end of that line.
929 If a @samp{#} appears as the first character of a line then the whole
930 line is treated as a comment, but in this case the line can also be a
931 logical line number directive (@pxref{Comments}) or a preprocessor
932 control command (@pxref{Preprocessing}).
934 If the @option{--divide} command-line option has not been specified
935 then the @samp{/} character appearing anywhere on a line also
936 introduces a line comment.
938 @cindex line separator, i386
939 @cindex statement separator, i386
940 @cindex i386 line separator
941 The @samp{;} character can be used to separate statements on the same
945 @section i386-Mnemonics
946 @subsection Instruction Naming
948 @cindex i386 instruction naming
949 @cindex instruction naming, i386
950 @cindex x86-64 instruction naming
951 @cindex instruction naming, x86-64
953 Instruction mnemonics are suffixed with one character modifiers which
954 specify the size of operands. The letters @samp{b}, @samp{w}, @samp{l}
955 and @samp{q} specify byte, word, long and quadruple word operands. If
956 no suffix is specified by an instruction then @code{@value{AS}} tries to
957 fill in the missing suffix based on the destination register operand
958 (the last one by convention). Thus, @samp{mov %ax, %bx} is equivalent
959 to @samp{movw %ax, %bx}; also, @samp{mov $1, %bx} is equivalent to
960 @samp{movw $1, bx}. Note that this is incompatible with the AT&T Unix
961 assembler which assumes that a missing mnemonic suffix implies long
962 operand size. (This incompatibility does not affect compiler output
963 since compilers always explicitly specify the mnemonic suffix.)
965 When there is no sizing suffix and no (suitable) register operands to
966 deduce the size of memory operands, with a few exceptions and where long
967 operand size is possible in the first place, operand size will default
968 to long in 32- and 64-bit modes. Similarly it will default to short in
969 16-bit mode. Noteworthy exceptions are
973 Instructions with an implicit on-stack operand as well as branches,
974 which default to quad in 64-bit mode.
977 Sign- and zero-extending moves, which default to byte size source
981 Floating point insns with integer operands, which default to short (for
982 perhaps historical reasons).
985 CRC32 with a 64-bit destination, which defaults to a quad source
990 @cindex encoding options, i386
991 @cindex encoding options, x86-64
993 Different encoding options can be specified via pseudo prefixes:
997 @samp{@{disp8@}} -- prefer 8-bit displacement.
1000 @samp{@{disp32@}} -- prefer 32-bit displacement.
1003 @samp{@{disp16@}} -- prefer 16-bit displacement.
1006 @samp{@{load@}} -- prefer load-form instruction.
1009 @samp{@{store@}} -- prefer store-form instruction.
1012 @samp{@{vex@}} -- encode with VEX prefix.
1015 @samp{@{vex3@}} -- encode with 3-byte VEX prefix.
1018 @samp{@{evex@}} -- encode with EVEX prefix.
1021 @samp{@{rex@}} -- prefer REX prefix for integer and legacy vector
1022 instructions (x86-64 only). Note that this differs from the @samp{rex}
1023 prefix which generates REX prefix unconditionally.
1026 @samp{@{rex2@}} -- prefer REX2 prefix for integer and legacy vector
1027 instructions (APX_F only).
1030 @samp{@{nooptimize@}} -- disable instruction size optimization.
1033 Mnemonics of Intel VNNI/IFMA instructions are encoded with the EVEX prefix
1034 by default. The pseudo @samp{@{vex@}} prefix can be used to encode
1035 mnemonics of Intel VNNI/IFMA instructions with the VEX prefix.
1037 @cindex conversion instructions, i386
1038 @cindex i386 conversion instructions
1039 @cindex conversion instructions, x86-64
1040 @cindex x86-64 conversion instructions
1041 The Intel-syntax conversion instructions
1045 @samp{cbw} --- sign-extend byte in @samp{%al} to word in @samp{%ax},
1048 @samp{cwde} --- sign-extend word in @samp{%ax} to long in @samp{%eax},
1051 @samp{cwd} --- sign-extend word in @samp{%ax} to long in @samp{%dx:%ax},
1054 @samp{cdq} --- sign-extend dword in @samp{%eax} to quad in @samp{%edx:%eax},
1057 @samp{cdqe} --- sign-extend dword in @samp{%eax} to quad in @samp{%rax}
1061 @samp{cqo} --- sign-extend quad in @samp{%rax} to octuple in
1062 @samp{%rdx:%rax} (x86-64 only),
1066 are called @samp{cbtw}, @samp{cwtl}, @samp{cwtd}, @samp{cltd}, @samp{cltq}, and
1067 @samp{cqto} in AT&T naming. @code{@value{AS}} accepts either naming for these
1070 @cindex extension instructions, i386
1071 @cindex i386 extension instructions
1072 @cindex extension instructions, x86-64
1073 @cindex x86-64 extension instructions
1074 The Intel-syntax extension instructions
1078 @samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg16}.
1081 @samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg32}.
1084 @samp{movsx} --- sign-extend @samp{reg8/mem8} to @samp{reg64}
1088 @samp{movsx} --- sign-extend @samp{reg16/mem16} to @samp{reg32}
1091 @samp{movsx} --- sign-extend @samp{reg16/mem16} to @samp{reg64}
1095 @samp{movsxd} --- sign-extend @samp{reg32/mem32} to @samp{reg64}
1099 @samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg16}.
1102 @samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg32}.
1105 @samp{movzx} --- zero-extend @samp{reg8/mem8} to @samp{reg64}
1109 @samp{movzx} --- zero-extend @samp{reg16/mem16} to @samp{reg32}
1112 @samp{movzx} --- zero-extend @samp{reg16/mem16} to @samp{reg64}
1117 are called @samp{movsbw/movsxb/movsx}, @samp{movsbl/movsxb/movsx},
1118 @samp{movsbq/movsxb/movsx}, @samp{movswl/movsxw}, @samp{movswq/movsxw},
1119 @samp{movslq/movsxl}, @samp{movzbw/movzxb/movzx},
1120 @samp{movzbl/movzxb/movzx}, @samp{movzbq/movzxb/movzx},
1121 @samp{movzwl/movzxw} and @samp{movzwq/movzxw} in AT&T syntax.
1123 @cindex jump instructions, i386
1124 @cindex call instructions, i386
1125 @cindex jump instructions, x86-64
1126 @cindex call instructions, x86-64
1127 Far call/jump instructions are @samp{lcall} and @samp{ljmp} in
1128 AT&T syntax, but are @samp{call far} and @samp{jump far} in Intel
1131 @subsection AT&T Mnemonic versus Intel Mnemonic
1133 @cindex i386 mnemonic compatibility
1134 @cindex mnemonic compatibility, i386
1136 @code{@value{AS}} supports assembly using Intel mnemonic.
1137 @code{.intel_mnemonic} selects Intel mnemonic with Intel syntax, and
1138 @code{.att_mnemonic} switches back to the usual AT&T mnemonic with AT&T
1139 syntax for compatibility with the output of @code{@value{GCC}}.
1140 Several x87 instructions, @samp{fadd}, @samp{fdiv}, @samp{fdivp},
1141 @samp{fdivr}, @samp{fdivrp}, @samp{fmul}, @samp{fsub}, @samp{fsubp},
1142 @samp{fsubr} and @samp{fsubrp}, are implemented in AT&T System V/386
1143 assembler with different mnemonics from those in Intel IA32 specification.
1144 @code{@value{GCC}} generates those instructions with AT&T mnemonic.
1147 @item @samp{movslq} with AT&T mnemonic only accepts 64-bit destination
1148 register. @samp{movsxd} should be used to encode 16-bit or 32-bit
1149 destination register with both AT&T and Intel mnemonics.
1153 @section Register Naming
1155 @cindex i386 registers
1156 @cindex registers, i386
1157 @cindex x86-64 registers
1158 @cindex registers, x86-64
1159 Register operands are always prefixed with @samp{%}. The 80386 registers
1164 the 8 32-bit registers @samp{%eax} (the accumulator), @samp{%ebx},
1165 @samp{%ecx}, @samp{%edx}, @samp{%edi}, @samp{%esi}, @samp{%ebp} (the
1166 frame pointer), and @samp{%esp} (the stack pointer).
1169 the 8 16-bit low-ends of these: @samp{%ax}, @samp{%bx}, @samp{%cx},
1170 @samp{%dx}, @samp{%di}, @samp{%si}, @samp{%bp}, and @samp{%sp}.
1173 the 8 8-bit registers: @samp{%ah}, @samp{%al}, @samp{%bh},
1174 @samp{%bl}, @samp{%ch}, @samp{%cl}, @samp{%dh}, and @samp{%dl} (These
1175 are the high-bytes and low-bytes of @samp{%ax}, @samp{%bx},
1176 @samp{%cx}, and @samp{%dx})
1179 the 6 section registers @samp{%cs} (code section), @samp{%ds}
1180 (data section), @samp{%ss} (stack section), @samp{%es}, @samp{%fs},
1184 the 5 processor control registers @samp{%cr0}, @samp{%cr2},
1185 @samp{%cr3}, @samp{%cr4}, and @samp{%cr8}.
1188 the 6 debug registers @samp{%db0}, @samp{%db1}, @samp{%db2},
1189 @samp{%db3}, @samp{%db6}, and @samp{%db7}.
1192 the 2 test registers @samp{%tr6} and @samp{%tr7}.
1195 the 8 floating point register stack @samp{%st} or equivalently
1196 @samp{%st(0)}, @samp{%st(1)}, @samp{%st(2)}, @samp{%st(3)},
1197 @samp{%st(4)}, @samp{%st(5)}, @samp{%st(6)}, and @samp{%st(7)}.
1198 These registers are overloaded by 8 MMX registers @samp{%mm0},
1199 @samp{%mm1}, @samp{%mm2}, @samp{%mm3}, @samp{%mm4}, @samp{%mm5},
1200 @samp{%mm6} and @samp{%mm7}.
1203 the 8 128-bit SSE registers registers @samp{%xmm0}, @samp{%xmm1}, @samp{%xmm2},
1204 @samp{%xmm3}, @samp{%xmm4}, @samp{%xmm5}, @samp{%xmm6} and @samp{%xmm7}.
1207 The AMD x86-64 architecture extends the register set by:
1211 enhancing the 8 32-bit registers to 64-bit: @samp{%rax} (the
1212 accumulator), @samp{%rbx}, @samp{%rcx}, @samp{%rdx}, @samp{%rdi},
1213 @samp{%rsi}, @samp{%rbp} (the frame pointer), @samp{%rsp} (the stack
1217 the 8 extended registers @samp{%r8}--@samp{%r15}.
1220 the 8 32-bit low ends of the extended registers: @samp{%r8d}--@samp{%r15d}.
1223 the 8 16-bit low ends of the extended registers: @samp{%r8w}--@samp{%r15w}.
1226 the 8 8-bit low ends of the extended registers: @samp{%r8b}--@samp{%r15b}.
1229 the 4 8-bit registers: @samp{%sil}, @samp{%dil}, @samp{%bpl}, @samp{%spl}.
1232 the 8 debug registers: @samp{%db8}--@samp{%db15}.
1235 the 8 128-bit SSE registers: @samp{%xmm8}--@samp{%xmm15}.
1238 With the AVX extensions more registers were made available:
1243 the 16 256-bit SSE @samp{%ymm0}--@samp{%ymm15} (only the first 8
1244 available in 32-bit mode). The bottom 128 bits are overlaid with the
1245 @samp{xmm0}--@samp{xmm15} registers.
1249 The AVX512 extensions added the following registers:
1254 the 32 512-bit registers @samp{%zmm0}--@samp{%zmm31} (only the first 8
1255 available in 32-bit mode). The bottom 128 bits are overlaid with the
1256 @samp{%xmm0}--@samp{%xmm31} registers and the first 256 bits are
1257 overlaid with the @samp{%ymm0}--@samp{%ymm31} registers.
1260 the 8 mask registers @samp{%k0}--@samp{%k7}.
1265 @section Instruction Prefixes
1267 @cindex i386 instruction prefixes
1268 @cindex instruction prefixes, i386
1269 @cindex prefixes, i386
1270 Instruction prefixes are used to modify the following instruction. They
1271 are used to repeat string instructions, to provide section overrides, to
1272 perform bus lock operations, and to change operand and address sizes.
1273 (Most instructions that normally operate on 32-bit operands will use
1274 16-bit operands if the instruction has an ``operand size'' prefix.)
1275 Instruction prefixes are best written on the same line as the instruction
1276 they act upon. For example, the @samp{scas} (scan string) instruction is
1280 repne scas %es:(%edi),%al
1283 You may also place prefixes on the lines immediately preceding the
1284 instruction, but this circumvents checks that @code{@value{AS}} does
1285 with prefixes, and will not work with all prefixes.
1287 Here is a list of instruction prefixes:
1289 @cindex section override prefixes, i386
1292 Section override prefixes @samp{cs}, @samp{ds}, @samp{ss}, @samp{es},
1293 @samp{fs}, @samp{gs}. These are automatically added by specifying
1294 using the @var{section}:@var{memory-operand} form for memory references.
1296 @cindex size prefixes, i386
1298 Operand/Address size prefixes @samp{data16} and @samp{addr16}
1299 change 32-bit operands/addresses into 16-bit operands/addresses,
1300 while @samp{data32} and @samp{addr32} change 16-bit ones (in a
1301 @code{.code16} section) into 32-bit operands/addresses. These prefixes
1302 @emph{must} appear on the same line of code as the instruction they
1303 modify. For example, in a 16-bit @code{.code16} section, you might
1310 @cindex bus lock prefixes, i386
1311 @cindex inhibiting interrupts, i386
1313 The bus lock prefix @samp{lock} inhibits interrupts during execution of
1314 the instruction it precedes. (This is only valid with certain
1315 instructions; see a 80386 manual for details).
1317 @cindex coprocessor wait, i386
1319 The wait for coprocessor prefix @samp{wait} waits for the coprocessor to
1320 complete the current instruction. This should never be needed for the
1321 80386/80387 combination.
1323 @cindex repeat prefixes, i386
1325 The @samp{rep}, @samp{repe}, and @samp{repne} prefixes are added
1326 to string instructions to make them repeat @samp{%ecx} times (@samp{%cx}
1327 times if the current address size is 16-bits).
1328 @cindex REX prefixes, i386
1330 The @samp{rex} family of prefixes is used by x86-64 to encode
1331 extensions to i386 instruction set. The @samp{rex} prefix has four
1332 bits --- an operand size overwrite (@code{64}) used to change operand size
1333 from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the
1336 You may write the @samp{rex} prefixes directly. The @samp{rex64xyz}
1337 instruction emits @samp{rex} prefix with all the bits set. By omitting
1338 the @code{64}, @code{x}, @code{y} or @code{z} you may write other
1339 prefixes as well. Normally, there is no need to write the prefixes
1340 explicitly, since gas will automatically generate them based on the
1341 instruction operands.
1345 @section Memory References
1347 @cindex i386 memory references
1348 @cindex memory references, i386
1349 @cindex x86-64 memory references
1350 @cindex memory references, x86-64
1351 An Intel syntax indirect memory reference of the form
1354 @var{section}:[@var{base} + @var{index}*@var{scale} + @var{disp}]
1358 is translated into the AT&T syntax
1361 @var{section}:@var{disp}(@var{base}, @var{index}, @var{scale})
1365 where @var{base} and @var{index} are the optional 32-bit base and
1366 index registers, @var{disp} is the optional displacement, and
1367 @var{scale}, taking the values 1, 2, 4, and 8, multiplies @var{index}
1368 to calculate the address of the operand. If no @var{scale} is
1369 specified, @var{scale} is taken to be 1. @var{section} specifies the
1370 optional section register for the memory operand, and may override the
1371 default section register (see a 80386 manual for section register
1372 defaults). Note that section overrides in AT&T syntax @emph{must}
1373 be preceded by a @samp{%}. If you specify a section override which
1374 coincides with the default section register, @code{@value{AS}} does @emph{not}
1375 output any section register override prefixes to assemble the given
1376 instruction. Thus, section overrides can be specified to emphasize which
1377 section register is used for a given memory operand.
1379 Here are some examples of Intel and AT&T style memory references:
1382 @item AT&T: @samp{-4(%ebp)}, Intel: @samp{[ebp - 4]}
1383 @var{base} is @samp{%ebp}; @var{disp} is @samp{-4}. @var{section} is
1384 missing, and the default section is used (@samp{%ss} for addressing with
1385 @samp{%ebp} as the base register). @var{index}, @var{scale} are both missing.
1387 @item AT&T: @samp{foo(,%eax,4)}, Intel: @samp{[foo + eax*4]}
1388 @var{index} is @samp{%eax} (scaled by a @var{scale} 4); @var{disp} is
1389 @samp{foo}. All other fields are missing. The section register here
1390 defaults to @samp{%ds}.
1392 @item AT&T: @samp{foo(,1)}; Intel @samp{[foo]}
1393 This uses the value pointed to by @samp{foo} as a memory operand.
1394 Note that @var{base} and @var{index} are both missing, but there is only
1395 @emph{one} @samp{,}. This is a syntactic exception.
1397 @item AT&T: @samp{%gs:foo}; Intel @samp{gs:foo}
1398 This selects the contents of the variable @samp{foo} with section
1399 register @var{section} being @samp{%gs}.
1402 Absolute (as opposed to PC relative) call and jump operands must be
1403 prefixed with @samp{*}. If no @samp{*} is specified, @code{@value{AS}}
1404 always chooses PC relative addressing for jump/call labels.
1406 Any instruction that has a memory operand, but no register operand,
1407 @emph{must} specify its size (byte, word, long, or quadruple) with an
1408 instruction mnemonic suffix (@samp{b}, @samp{w}, @samp{l} or @samp{q},
1411 The x86-64 architecture adds an RIP (instruction pointer relative)
1412 addressing. This addressing mode is specified by using @samp{rip} as a
1413 base register. Only constant offsets are valid. For example:
1416 @item AT&T: @samp{1234(%rip)}, Intel: @samp{[rip + 1234]}
1417 Points to the address 1234 bytes past the end of the current
1420 @item AT&T: @samp{symbol(%rip)}, Intel: @samp{[rip + symbol]}
1421 Points to the @code{symbol} in RIP relative way, this is shorter than
1422 the default absolute addressing.
1425 Other addressing modes remain unchanged in x86-64 architecture, except
1426 registers used are 64-bit instead of 32-bit.
1429 @section Handling of Jump Instructions
1431 @cindex jump optimization, i386
1432 @cindex i386 jump optimization
1433 @cindex jump optimization, x86-64
1434 @cindex x86-64 jump optimization
1435 Jump instructions are always optimized to use the smallest possible
1436 displacements. This is accomplished by using byte (8-bit) displacement
1437 jumps whenever the target is sufficiently close. If a byte displacement
1438 is insufficient a long displacement is used. We do not support
1439 word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump
1440 instruction with the @samp{data16} instruction prefix), since the 80386
1441 insists upon masking @samp{%eip} to 16 bits after the word displacement
1442 is added. (See also @pxref{i386-Arch})
1444 Note that the @samp{jcxz}, @samp{jecxz}, @samp{loop}, @samp{loopz},
1445 @samp{loope}, @samp{loopnz} and @samp{loopne} instructions only come in byte
1446 displacements, so that if you use these instructions (@code{@value{GCC}} does
1447 not use them) you may get an error message (and incorrect code). The AT&T
1448 80386 assembler tries to get around this problem by expanding @samp{jcxz foo}
1459 @section Floating Point
1461 @cindex i386 floating point
1462 @cindex floating point, i386
1463 @cindex x86-64 floating point
1464 @cindex floating point, x86-64
1465 All 80387 floating point types except packed BCD are supported.
1466 (BCD support may be added without much difficulty). These data
1467 types are 16-, 32-, and 64- bit integers, and single (32-bit),
1468 double (64-bit), and extended (80-bit) precision floating point.
1469 Each supported type has an instruction mnemonic suffix and a constructor
1470 associated with it. Instruction mnemonic suffixes specify the operand's
1471 data type. Constructors build these data types into memory.
1473 @cindex @code{float} directive, i386
1474 @cindex @code{single} directive, i386
1475 @cindex @code{double} directive, i386
1476 @cindex @code{tfloat} directive, i386
1477 @cindex @code{hfloat} directive, i386
1478 @cindex @code{bfloat16} directive, i386
1479 @cindex @code{float} directive, x86-64
1480 @cindex @code{single} directive, x86-64
1481 @cindex @code{double} directive, x86-64
1482 @cindex @code{tfloat} directive, x86-64
1483 @cindex @code{hfloat} directive, x86-64
1484 @cindex @code{bfloat16} directive, x86-64
1487 Floating point constructors are @samp{.float} or @samp{.single},
1488 @samp{.double}, @samp{.tfloat}, @samp{.hfloat}, and @samp{.bfloat16} for 32-,
1489 64-, 80-, and 16-bit (two flavors) formats respectively. The former three
1490 correspond to instruction mnemonic suffixes @samp{s}, @samp{l}, and @samp{t}.
1491 @samp{t} stands for 80-bit (ten byte) real. The 80387 only supports this
1492 format via the @samp{fldt} (load 80-bit real to stack top) and @samp{fstpt}
1493 (store 80-bit real and pop stack) instructions.
1495 @cindex @code{word} directive, i386
1496 @cindex @code{long} directive, i386
1497 @cindex @code{int} directive, i386
1498 @cindex @code{quad} directive, i386
1499 @cindex @code{word} directive, x86-64
1500 @cindex @code{long} directive, x86-64
1501 @cindex @code{int} directive, x86-64
1502 @cindex @code{quad} directive, x86-64
1504 Integer constructors are @samp{.word}, @samp{.long} or @samp{.int}, and
1505 @samp{.quad} for the 16-, 32-, and 64-bit integer formats. The
1506 corresponding instruction mnemonic suffixes are @samp{s} (short),
1507 @samp{l} (long), and @samp{q} (quad). As with the 80-bit real format,
1508 the 64-bit @samp{q} format is only present in the @samp{fildq} (load
1509 quad integer to stack top) and @samp{fistpq} (store quad integer and pop
1510 stack) instructions.
1513 Register to register operations should not use instruction mnemonic suffixes.
1514 @samp{fstl %st, %st(1)} will give a warning, and be assembled as if you
1515 wrote @samp{fst %st, %st(1)}, since all register to register operations
1516 use 80-bit floating point operands. (Contrast this with @samp{fstl %st, mem},
1517 which converts @samp{%st} from 80-bit to 64-bit floating point format,
1518 then stores the result in the 4 byte location @samp{mem})
1521 @section Intel's MMX and AMD's 3DNow! SIMD Operations
1524 @cindex 3DNow!, i386
1527 @cindex 3DNow!, x86-64
1528 @cindex SIMD, x86-64
1530 @code{@value{AS}} supports Intel's MMX instruction set (SIMD
1531 instructions for integer data), available on Intel's Pentium MMX
1532 processors and Pentium II processors, AMD's K6 and K6-2 processors,
1533 Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!@:
1534 instruction set (SIMD instructions for 32-bit floating point data)
1535 available on AMD's K6-2 processor and possibly others in the future.
1537 Currently, @code{@value{AS}} does not support Intel's floating point
1540 The eight 64-bit MMX operands, also used by 3DNow!, are called @samp{%mm0},
1541 @samp{%mm1}, ... @samp{%mm7}. They contain eight 8-bit integers, four
1542 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
1543 floating point values. The MMX registers cannot be used at the same time
1544 as the floating point stack.
1546 See Intel and AMD documentation, keeping in mind that the operand order in
1547 instructions is reversed from the Intel syntax.
1550 @section AMD's Lightweight Profiling Instructions
1555 @code{@value{AS}} supports AMD's Lightweight Profiling (LWP)
1556 instruction set, available on AMD's Family 15h (Orochi) processors.
1558 LWP enables applications to collect and manage performance data, and
1559 react to performance events. The collection of performance data
1560 requires no context switches. LWP runs in the context of a thread and
1561 so several counters can be used independently across multiple threads.
1562 LWP can be used in both 64-bit and legacy 32-bit modes.
1564 For detailed information on the LWP instruction set, see the
1565 @cite{AMD Lightweight Profiling Specification} available at
1566 @uref{http://developer.amd.com/cpu/LWP,Lightweight Profiling Specification}.
1569 @section Bit Manipulation Instructions
1574 @code{@value{AS}} supports the Bit Manipulation (BMI) instruction set.
1576 BMI instructions provide several instructions implementing individual
1577 bit manipulation operations such as isolation, masking, setting, or
1580 @c Need to add a specification citation here when available.
1583 @section AMD's Trailing Bit Manipulation Instructions
1588 @code{@value{AS}} supports AMD's Trailing Bit Manipulation (TBM)
1589 instruction set, available on AMD's BDVER2 processors (Trinity and
1592 TBM instructions provide instructions implementing individual bit
1593 manipulation operations such as isolating, masking, setting, resetting,
1594 complementing, and operations on trailing zeros and ones.
1596 @c Need to add a specification citation here when available.
1599 @section Writing 16-bit Code
1601 @cindex i386 16-bit code
1602 @cindex 16-bit code, i386
1603 @cindex real-mode code, i386
1604 @cindex @code{code16gcc} directive, i386
1605 @cindex @code{code16} directive, i386
1606 @cindex @code{code32} directive, i386
1607 @cindex @code{code64} directive, i386
1608 @cindex @code{code64} directive, x86-64
1609 While @code{@value{AS}} normally writes only ``pure'' 32-bit i386 code
1610 or 64-bit x86-64 code depending on the default configuration,
1611 it also supports writing code to run in real mode or in 16-bit protected
1612 mode code segments. To do this, put a @samp{.code16} or
1613 @samp{.code16gcc} directive before the assembly language instructions to
1614 be run in 16-bit mode. You can switch @code{@value{AS}} to writing
1615 32-bit code with the @samp{.code32} directive or 64-bit code with the
1616 @samp{.code64} directive.
1618 @samp{.code16gcc} provides experimental support for generating 16-bit
1619 code from gcc, and differs from @samp{.code16} in that @samp{call},
1620 @samp{ret}, @samp{enter}, @samp{leave}, @samp{push}, @samp{pop},
1621 @samp{pusha}, @samp{popa}, @samp{pushf}, and @samp{popf} instructions
1622 default to 32-bit size. This is so that the stack pointer is
1623 manipulated in the same way over function calls, allowing access to
1624 function parameters at the same stack offsets as in 32-bit mode.
1625 @samp{.code16gcc} also automatically adds address size prefixes where
1626 necessary to use the 32-bit addressing modes that gcc generates.
1628 The code which @code{@value{AS}} generates in 16-bit mode will not
1629 necessarily run on a 16-bit pre-80386 processor. To write code that
1630 runs on such a processor, you must refrain from using @emph{any} 32-bit
1631 constructs which require @code{@value{AS}} to output address or operand
1634 Note that writing 16-bit code instructions by explicitly specifying a
1635 prefix or an instruction mnemonic suffix within a 32-bit code section
1636 generates different machine instructions than those generated for a
1637 16-bit code segment. In a 32-bit code section, the following code
1638 generates the machine opcode bytes @samp{66 6a 04}, which pushes the
1639 value @samp{4} onto the stack, decrementing @samp{%esp} by 2.
1645 The same code in a 16-bit code section would generate the machine
1646 opcode bytes @samp{6a 04} (i.e., without the operand size prefix), which
1647 is correct since the processor default operand size is assumed to be 16
1648 bits in a 16-bit code section.
1651 @section Specifying CPU Architecture
1653 @cindex arch directive, i386
1654 @cindex i386 arch directive
1655 @cindex arch directive, x86-64
1656 @cindex x86-64 arch directive
1658 @code{@value{AS}} may be told to assemble for a particular CPU
1659 (sub-)architecture with the @code{.arch @var{cpu_type}} directive. This
1660 directive enables a warning when gas detects an instruction that is not
1661 supported on the CPU specified. The choices for @var{cpu_type} are:
1663 @multitable @columnfractions .20 .20 .20 .20
1664 @item @samp{default} @tab @samp{push} @tab @samp{pop}
1665 @item @samp{i8086} @tab @samp{i186} @tab @samp{i286} @tab @samp{i386}
1666 @item @samp{i486} @tab @samp{i586} @tab @samp{i686} @tab @samp{pentium}
1667 @item @samp{pentiumpro} @tab @samp{pentiumii} @tab @samp{pentiumiii} @tab @samp{pentium4}
1668 @item @samp{prescott} @tab @samp{nocona} @tab @samp{core} @tab @samp{core2}
1669 @item @samp{corei7} @tab @samp{iamcu}
1670 @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
1671 @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
1672 @item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{znver3}
1673 @item @samp{znver4} @tab @samp{znver5} @tab @samp{btver1} @tab @samp{btver2}
1674 @item @samp{generic32}
1675 @item @samp{generic64} @tab @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx}
1676 @item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} @tab @samp{.sse4a}
1677 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
1678 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
1679 @item @samp{.clflush} @tab @samp{.movbe} @tab @samp{.xsave} @tab @samp{.xsaveopt}
1680 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.fsgsbase}
1681 @item @samp{.rdrnd} @tab @samp{.f16c} @tab @samp{.avx2} @tab @samp{.bmi2}
1682 @item @samp{.lzcnt} @tab @samp{.popcnt} @tab @samp{.invpcid} @tab @samp{.vmfunc}
1683 @item @samp{.monitor} @tab @samp{.hle} @tab @samp{.rtm} @tab @samp{.tsx}
1684 @item @samp{.lahf_sahf} @tab @samp{.adx} @tab @samp{.rdseed} @tab @samp{.prfchw}
1685 @item @samp{.smap} @tab @samp{.mpx} @tab @samp{.sha} @tab @samp{.prefetchwt1}
1686 @item @samp{.clflushopt} @tab @samp{.xsavec} @tab @samp{.xsaves} @tab @samp{.se1}
1687 @item @samp{.avx512f} @tab @samp{.avx512cd} @tab @samp{.avx512er} @tab @samp{.avx512pf}
1688 @item @samp{.avx512vl} @tab @samp{.avx512bw} @tab @samp{.avx512dq} @tab @samp{.avx512ifma}
1689 @item @samp{.avx512vbmi} @tab @samp{.avx512_4fmaps} @tab @samp{.avx512_4vnniw}
1690 @item @samp{.avx512_vpopcntdq} @tab @samp{.avx512_vbmi2} @tab @samp{.avx512_vnni}
1691 @item @samp{.avx512_bitalg} @tab @samp{.avx512_bf16} @tab @samp{.avx512_vp2intersect}
1692 @item @samp{.tdx} @tab @samp{.avx_vnni} @tab @samp{.avx512_fp16} @tab @samp{.avx10.1}
1693 @item @samp{.clwb} @tab @samp{.rdpid} @tab @samp{.ptwrite} @tab @samp{.ibt}
1694 @item @samp{.prefetchi} @tab @samp{.avx_ifma} @tab @samp{.avx_vnni_int8}
1695 @item @samp{.cmpccxadd} @tab @samp{.wrmsrns} @tab @samp{.msrlist}
1696 @item @samp{.avx_ne_convert} @tab @samp{.rao_int} @tab @samp{.fred} @tab @samp{.lkgs}
1697 @item @samp{.avx_vnni_int16} @tab @samp{.sha512} @tab @samp{.sm3} @tab @samp{.sm4}
1698 @item @samp{.pbndkb} @tab @samp{.user_msr} @tab @samp{.msr_imm} @tab @samp{.avx10.2}
1699 @item @samp{.wbnoinvd} @tab @samp{.pconfig} @tab @samp{.waitpkg} @tab @samp{.cldemote}
1700 @item @samp{.shstk} @tab @samp{.gfni} @tab @samp{.vaes} @tab @samp{.vpclmulqdq}
1701 @item @samp{.movdiri} @tab @samp{.movdir64b} @tab @samp{.enqcmd} @tab @samp{.tsxldtrk}
1702 @item @samp{.amx_int8} @tab @samp{.amx_bf16} @tab @samp{.amx_fp16}
1703 @item @samp{.amx_complex} @tab @samp{.amx_tile}
1704 @item @samp{.kl} @tab @samp{.widekl} @tab @samp{.uintr} @tab @samp{.hreset}
1705 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
1706 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme}
1707 @item @samp{.lwp} @tab @samp{.fma4} @tab @samp{.xop} @tab @samp{.cx16}
1708 @item @samp{.padlock} @tab @samp{.clzero} @tab @samp{.mwaitx} @tab @samp{.rdpru}
1709 @item @samp{.mcommit} @tab @samp{.sev_es} @tab @samp{.snp} @tab @samp{.invlpgb}
1710 @item @samp{.tlbsync} @tab @samp{.apx_f} @tab @samp{.gmi}
1714 Apart from the warning, there are only two other effects on
1715 @code{@value{AS}} operation; Firstly, if you specify a CPU other than
1716 @samp{i486}, then shift by one instructions such as @samp{sarl $1, %eax}
1717 will automatically use a two byte opcode sequence. The larger three
1718 byte opcode sequence is used on the 486 (and when no architecture is
1719 specified) because it executes faster on the 486. Note that you can
1720 explicitly request the two byte opcode by writing @samp{sarl %eax}.
1721 Secondly, if you specify @samp{i8086}, @samp{i186}, or @samp{i286},
1722 @emph{and} @samp{.code16} or @samp{.code16gcc} then byte offset
1723 conditional jumps will be promoted when necessary to a two instruction
1724 sequence consisting of a conditional jump of the opposite sense around
1725 an unconditional jump to the target.
1727 Note that the sub-architecture specifiers (starting with a dot) can be prefixed
1728 with @code{no} to revoke the respective (and any dependent) functionality.
1729 Note further that @samp{.avx10.<N>} can be suffixed with a vector length
1730 restriction (@samp{/256} or @samp{/128}, with @samp{/512} simply restoring the
1731 default). Despite these otherwise being "enabling" specifiers, using these
1732 suffixes will disable all insns with wider vector or mask register operands.
1733 On SVR4-derived platforms, the separator character @samp{/} can be replaced by
1736 Following the CPU architecture (but not a sub-architecture, which are those
1737 starting with a dot), you may specify @samp{jumps} or @samp{nojumps} to
1738 control automatic promotion of conditional jumps. @samp{jumps} is the
1739 default, and enables jump promotion; All external jumps will be of the long
1740 variety, and file-local jumps will be promoted as necessary.
1741 (@pxref{i386-Jumps}) @samp{nojumps} leaves external conditional jumps as
1742 byte offset jumps, and warns about file-local conditional jumps that
1743 @code{@value{AS}} promotes.
1744 Unconditional jumps are treated as for @samp{jumps}.
1753 @section AMD64 ISA vs. Intel64 ISA
1755 There are some discrepancies between AMD64 and Intel64 ISAs.
1758 @item For @samp{movsxd} with 16-bit destination register, AMD64
1759 supports 32-bit source operand and Intel64 supports 16-bit source
1762 @item For far branches (with explicit memory operand), both ISAs support
1763 32- and 16-bit operand size. Intel64 additionally supports 64-bit
1764 operand size, encoded as @samp{ljmpq} and @samp{lcallq} in AT&T syntax
1765 and with an explicit @samp{tbyte ptr} operand size specifier in Intel
1768 @item @samp{lfs}, @samp{lgs}, and @samp{lss} similarly allow for 16-
1769 and 32-bit operand size (32- and 48-bit memory operand) in both ISAs,
1770 while Intel64 additionally supports 64-bit operand size (80-bit memory
1776 @section AT&T Syntax bugs
1778 The UnixWare assembler, and probably other AT&T derived ix86 Unix
1779 assemblers, generate floating point instructions with reversed source
1780 and destination registers in certain cases. Unfortunately, gcc and
1781 possibly many other programs use this reversed syntax, so we're stuck
1790 results in @samp{%st(3)} being updated to @samp{%st - %st(3)} rather
1791 than the expected @samp{%st(3) - %st}. This happens with all the
1792 non-commutative arithmetic floating point operations with two register
1793 operands where the source register is @samp{%st} and the destination
1794 register is @samp{%st(i)}.
1799 @cindex i386 @code{mul}, @code{imul} instructions
1800 @cindex @code{mul} instruction, i386
1801 @cindex @code{imul} instruction, i386
1802 @cindex @code{mul} instruction, x86-64
1803 @cindex @code{imul} instruction, x86-64
1804 There is some trickery concerning the @samp{mul} and @samp{imul}
1805 instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding
1806 multiplies (base opcode @samp{0xf6}; extension 4 for @samp{mul} and 5
1807 for @samp{imul}) can be output only in the one operand form. Thus,
1808 @samp{imul %ebx, %eax} does @emph{not} select the expanding multiply;
1809 the expanding multiply would clobber the @samp{%edx} register, and this
1810 would confuse @code{@value{GCC}} output. Use @samp{imul %ebx} to get the
1811 64-bit product in @samp{%edx:%eax}.
1813 We have added a two operand form of @samp{imul} when the first operand
1814 is an immediate mode expression and the second operand is a register.
1815 This is just a shorthand, so that, multiplying @samp{%eax} by 69, for
1816 example, can be done with @samp{imul $69, %eax} rather than @samp{imul