3 #ld
: -melf64ppc
--no
-plt
-align --no
-ld
-generated
-unwind
-info
--emit
-relocs
8 Disassembly of section \
.text
:
11 [0-9a
-f
]*: (49 bf
00 2d|
2d 00 bf
49) bl
.*
12 [0-9a
-f
]*: R_PPC64_REL24 \
.text\
+0x37e003c
13 [0-9a
-f
]*: (60 00 00 00|
00 00 00 60) nop
14 [0-9a
-f
]*: (49 bf
00 19|
19 00 bf
49) bl
.*
15 [0-9a
-f
]*: R_PPC64_REL24 \
.text\
+0x3bf0020
16 [0-9a
-f
]*: (60 00 00 00|
00 00 00 60) nop
17 [0-9a
-f
]*: (49 bf
00 21|
21 00 bf
49) bl
.*
18 [0-9a
-f
]*: R_PPC64_REL24 \
.text\
+0x57e0024
19 [0-9a
-f
]*: (60 00 00 00|
00 00 00 60) nop
20 [0-9a
-f
]*: 00 00 00 00 \
.long 0x0
21 [0-9a
-f
]*: (4b ff ff e4|e4 ff ff
4b) b
.* <_start
>
24 [0-9a
-f
]*<.*plt_branch
.*>:
25 [0-9a
-f
]*: (e9
82 80 e8|e8
80 82 e9
) ld r12
,-32536\
(r2\
)
26 [0-9a
-f
]*: R_PPC64_TOC16_DS \
*ABS\
*\
+0x157f00e8
27 [0-9a
-f
]*: (7d 89 03 a6|a6
03 89 7d) mtctr r12
28 [0-9a
-f
]*: (4e
80 04 20|
20 04 80 4e
) bctr
30 [0-9a
-f
]*<.*long_branch
.*>:
31 [0-9a
-f
]*: (49 bf
00 10|
10 00 bf
49) b
.* <far
>
32 [0-9a
-f
]*: R_PPC64_REL24 \
*ABS\
*\
+0x137e00fc
34 [0-9a
-f
]*<.*plt_branch
.*>:
35 [0-9a
-f
]*: (e9
82 80 f0|f0
80 82 e9
) ld r12
,-32528\
(r2\
)
36 [0-9a
-f
]*: R_PPC64_TOC16_DS \
*ABS\
*\
+0x157f00f0
37 [0-9a
-f
]*: (7d 89 03 a6|a6
03 89 7d) mtctr r12
38 [0-9a
-f
]*: (4e
80 04 20|
20 04 80 4e
) bctr
42 [0-9a
-f
]*: (4e
80 00 20|
20 00 80 4e
) blr
46 [0-9a
-f
]*: (4e
80 00 20|
20 00 80 4e
) blr
50 [0-9a
-f
]*: (4e
80 00 20|
20 00 80 4e
) blr
52 Disassembly of section \
.branch_lt
:
55 [0-9a
-f
]*: (00 00 00 00|e0
00 bf
13) .*
56 [0-9a
-f
]*: R_PPC64_RELATIVE \
*ABS\
*\
+0x13bf00e0
57 [0-9a
-f
]*: (13 bf
00 e0|
00 00 00 00) .*
58 [0-9a
-f
]*: (00 00 00 00|e4
00 7e
15) .*
59 [0-9a
-f
]*: R_PPC64_RELATIVE \
*ABS\
*\
+0x157e00e4
60 [0-9a
-f
]*: (15 7e
00 e4|
00 00 00 00) .*