[PATCH 53/57][Arm][OBJDUMP] Add support for MVE instructions: vand, vbrsr, vcls,...
[binutils-gdb.git] / ld / testsuite / ld-powerpc / tlsopt4_32.d
blob59c0a6aae377fc94d1ea3f8f7969127384c2b9e0
1 #source: tlsopt4_32.s
2 #source: tlslib32.s
3 #as: -a32
4 #ld:
5 #objdump: -dr
6 #target: powerpc*-*-*
8 .*
10 Disassembly of section \.text:
12 0+1800094 <__tls_get_addr>:
13 .*: (4e 80 00 20|20 00 80 4e) blr
15 Disassembly of section \.opt1:
17 0+1800098 <\.opt1>:
18 .*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0
19 .*: (2c 04 00 00|00 00 04 2c) cmpwi r4,0
20 .*: (41 82 00 0c|0c 00 82 41) beq .*
21 .*: (38 63 90 10|10 90 63 38) addi r3,r3,-28656
22 .*: (48 00 00 08|08 00 00 48) b .*
23 .*: (38 63 90 10|10 90 63 38) addi r3,r3,-28656
25 Disassembly of section \.opt2:
27 0+18000b0 <\.opt2>:
28 .*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0
29 .*: (2c 04 00 00|00 00 04 2c) cmpwi r4,0
30 .*: (41 82 00 08|08 00 82 41) beq .*
31 .*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0
32 .*: (38 63 90 10|10 90 63 38) addi r3,r3,-28656
34 Disassembly of section \.opt3:
36 0+18000c4 <\.opt3>:
37 .*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0
38 .*: (48 00 00 0c|0c 00 00 48) b .*
39 .*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0
40 .*: (48 00 00 0c|0c 00 00 48) b .*
41 .*: (38 63 90 10|10 90 63 38) addi r3,r3,-28656
42 .*: (48 00 00 08|08 00 00 48) b .*
43 .*: (38 63 90 08|08 90 63 38) addi r3,r3,-28664
44 #pass