1 /* DO NOT EDIT! -*- buffer-read-only: t -*- vi:set ro: */
2 /* Instruction opcode table for or1k.
4 THIS FILE IS MACHINE GENERATED WITH CGEN.
6 Copyright (C) 1996-2020 Free Software Foundation, Inc.
8 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
10 This file is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3, or (at your option)
15 It is distributed in the hope that it will be useful, but WITHOUT
16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
18 License for more details.
20 You should have received a copy of the GNU General Public License along
21 with this program; if not, write to the Free Software Foundation, Inc.,
22 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
30 #include "or1k-desc.h"
32 #include "libiberty.h"
36 /* Special check to ensure that instruction exists for given machine. */
39 or1k_cgen_insn_supported (CGEN_CPU_DESC cd
, const CGEN_INSN
*insn
)
41 int machs
= CGEN_INSN_ATTR_VALUE (insn
, CGEN_INSN_MACH
);
43 /* No mach attribute? Assume it's supported for all machs. */
47 return ((machs
& cd
->machs
) != 0);
51 /* The hash functions are recorded here to help keep assembler code out of
52 the disassembler and vice versa. */
54 static int asm_hash_insn_p (const CGEN_INSN
*);
55 static unsigned int asm_hash_insn (const char *);
56 static int dis_hash_insn_p (const CGEN_INSN
*);
57 static unsigned int dis_hash_insn (const char *, CGEN_INSN_INT
);
59 /* Instruction formats. */
61 #define F(f) & or1k_cgen_ifld_table[OR1K_##f]
62 static const CGEN_IFMT ifmt_empty ATTRIBUTE_UNUSED
= {
66 static const CGEN_IFMT ifmt_l_j ATTRIBUTE_UNUSED
= {
67 32, 32, 0xfc000000, { { F (F_OPCODE
) }, { F (F_DISP26
) }, { 0 } }
70 static const CGEN_IFMT ifmt_l_adrp ATTRIBUTE_UNUSED
= {
71 32, 32, 0xfc000000, { { F (F_OPCODE
) }, { F (F_R1
) }, { F (F_DISP21
) }, { 0 } }
74 static const CGEN_IFMT ifmt_l_jr ATTRIBUTE_UNUSED
= {
75 32, 32, 0xffff07ff, { { F (F_OPCODE
) }, { F (F_RESV_25_10
) }, { F (F_R3
) }, { F (F_RESV_10_11
) }, { 0 } }
78 static const CGEN_IFMT ifmt_l_trap ATTRIBUTE_UNUSED
= {
79 32, 32, 0xffff0000, { { F (F_OPCODE
) }, { F (F_OP_25_5
) }, { F (F_RESV_20_5
) }, { F (F_UIMM16
) }, { 0 } }
82 static const CGEN_IFMT ifmt_l_msync ATTRIBUTE_UNUSED
= {
83 32, 32, 0xffffffff, { { F (F_OPCODE
) }, { F (F_OP_25_5
) }, { F (F_RESV_20_21
) }, { 0 } }
86 static const CGEN_IFMT ifmt_l_rfe ATTRIBUTE_UNUSED
= {
87 32, 32, 0xffffffff, { { F (F_OPCODE
) }, { F (F_RESV_25_26
) }, { 0 } }
90 static const CGEN_IFMT ifmt_l_nop_imm ATTRIBUTE_UNUSED
= {
91 32, 32, 0xffff0000, { { F (F_OPCODE
) }, { F (F_OP_25_2
) }, { F (F_RESV_23_8
) }, { F (F_UIMM16
) }, { 0 } }
94 static const CGEN_IFMT ifmt_l_movhi ATTRIBUTE_UNUSED
= {
95 32, 32, 0xfc1f0000, { { F (F_OPCODE
) }, { F (F_R1
) }, { F (F_RESV_20_4
) }, { F (F_OP_16_1
) }, { F (F_UIMM16
) }, { 0 } }
98 static const CGEN_IFMT ifmt_l_macrc ATTRIBUTE_UNUSED
= {
99 32, 32, 0xfc1fffff, { { F (F_OPCODE
) }, { F (F_R1
) }, { F (F_RESV_20_4
) }, { F (F_OP_16_1
) }, { F (F_UIMM16
) }, { 0 } }
102 static const CGEN_IFMT ifmt_l_mfspr ATTRIBUTE_UNUSED
= {
103 32, 32, 0xfc000000, { { F (F_OPCODE
) }, { F (F_R1
) }, { F (F_R2
) }, { F (F_UIMM16
) }, { 0 } }
106 static const CGEN_IFMT ifmt_l_mtspr ATTRIBUTE_UNUSED
= {
107 32, 32, 0xfc000000, { { F (F_OPCODE
) }, { F (F_R2
) }, { F (F_R3
) }, { F (F_UIMM16_SPLIT
) }, { 0 } }
110 static const CGEN_IFMT ifmt_l_lwz ATTRIBUTE_UNUSED
= {
111 32, 32, 0xfc000000, { { F (F_OPCODE
) }, { F (F_R1
) }, { F (F_R2
) }, { F (F_SIMM16
) }, { 0 } }
114 static const CGEN_IFMT ifmt_l_sw ATTRIBUTE_UNUSED
= {
115 32, 32, 0xfc000000, { { F (F_OPCODE
) }, { F (F_R2
) }, { F (F_R3
) }, { F (F_SIMM16_SPLIT
) }, { 0 } }
118 static const CGEN_IFMT ifmt_l_swa ATTRIBUTE_UNUSED
= {
119 32, 32, 0xfc000000, { { F (F_OPCODE
) }, { F (F_R2
) }, { F (F_R3
) }, { F (F_SIMM16
) }, { 0 } }
122 static const CGEN_IFMT ifmt_l_sll ATTRIBUTE_UNUSED
= {
123 32, 32, 0xfc0007ff, { { F (F_OPCODE
) }, { F (F_R1
) }, { F (F_R2
) }, { F (F_R3
) }, { F (F_RESV_10_3
) }, { F (F_OP_7_2
) }, { F (F_RESV_5_2
) }, { F (F_OP_3_4
) }, { 0 } }
126 static const CGEN_IFMT ifmt_l_slli ATTRIBUTE_UNUSED
= {
127 32, 32, 0xfc00ffc0, { { F (F_OPCODE
) }, { F (F_R1
) }, { F (F_R2
) }, { F (F_RESV_15_8
) }, { F (F_OP_7_2
) }, { F (F_UIMM6
) }, { 0 } }
130 static const CGEN_IFMT ifmt_l_and ATTRIBUTE_UNUSED
= {
131 32, 32, 0xfc0007ff, { { F (F_OPCODE
) }, { F (F_R1
) }, { F (F_R2
) }, { F (F_R3
) }, { F (F_RESV_10_7
) }, { F (F_OP_3_4
) }, { 0 } }
134 static const CGEN_IFMT ifmt_l_muld ATTRIBUTE_UNUSED
= {
135 32, 32, 0xffe007ff, { { F (F_OPCODE
) }, { F (F_RESV_25_5
) }, { F (F_R2
) }, { F (F_R3
) }, { F (F_RESV_10_7
) }, { F (F_OP_3_4
) }, { 0 } }
138 static const CGEN_IFMT ifmt_l_exths ATTRIBUTE_UNUSED
= {
139 32, 32, 0xfc00ffff, { { F (F_OPCODE
) }, { F (F_R1
) }, { F (F_R2
) }, { F (F_RESV_15_6
) }, { F (F_OP_9_4
) }, { F (F_RESV_5_2
) }, { F (F_OP_3_4
) }, { 0 } }
142 static const CGEN_IFMT ifmt_l_cmov ATTRIBUTE_UNUSED
= {
143 32, 32, 0xfc0007ff, { { F (F_OPCODE
) }, { F (F_R1
) }, { F (F_R2
) }, { F (F_R3
) }, { F (F_RESV_10_1
) }, { F (F_OP_9_2
) }, { F (F_RESV_7_4
) }, { F (F_OP_3_4
) }, { 0 } }
146 static const CGEN_IFMT ifmt_l_sfgts ATTRIBUTE_UNUSED
= {
147 32, 32, 0xffe007ff, { { F (F_OPCODE
) }, { F (F_OP_25_5
) }, { F (F_R2
) }, { F (F_R3
) }, { F (F_RESV_10_11
) }, { 0 } }
150 static const CGEN_IFMT ifmt_l_sfgtsi ATTRIBUTE_UNUSED
= {
151 32, 32, 0xffe00000, { { F (F_OPCODE
) }, { F (F_OP_25_5
) }, { F (F_R2
) }, { F (F_SIMM16
) }, { 0 } }
154 static const CGEN_IFMT ifmt_l_mac ATTRIBUTE_UNUSED
= {
155 32, 32, 0xffe007ff, { { F (F_OPCODE
) }, { F (F_OP_25_5
) }, { F (F_R2
) }, { F (F_R3
) }, { F (F_RESV_10_7
) }, { F (F_OP_3_4
) }, { 0 } }
158 static const CGEN_IFMT ifmt_l_maci ATTRIBUTE_UNUSED
= {
159 32, 32, 0xffe00000, { { F (F_OPCODE
) }, { F (F_RESV_25_5
) }, { F (F_R2
) }, { F (F_SIMM16
) }, { 0 } }
162 static const CGEN_IFMT ifmt_lf_add_s ATTRIBUTE_UNUSED
= {
163 32, 32, 0xfc0007ff, { { F (F_OPCODE
) }, { F (F_R1
) }, { F (F_R2
) }, { F (F_R3
) }, { F (F_RESV_10_3
) }, { F (F_OP_7_8
) }, { 0 } }
166 static const CGEN_IFMT ifmt_lf_add_d32 ATTRIBUTE_UNUSED
= {
167 32, 32, 0xfc0000ff, { { F (F_OPCODE
) }, { F (F_RDD32
) }, { F (F_RAD32
) }, { F (F_RBD32
) }, { F (F_OP_7_8
) }, { 0 } }
170 static const CGEN_IFMT ifmt_lf_itof_s ATTRIBUTE_UNUSED
= {
171 32, 32, 0xfc00ffff, { { F (F_OPCODE
) }, { F (F_R1
) }, { F (F_R2
) }, { F (F_R3
) }, { F (F_RESV_10_3
) }, { F (F_OP_7_8
) }, { 0 } }
174 static const CGEN_IFMT ifmt_lf_itof_d32 ATTRIBUTE_UNUSED
= {
175 32, 32, 0xfc00f9ff, { { F (F_OPCODE
) }, { F (F_R3
) }, { F (F_RDD32
) }, { F (F_RAD32
) }, { F (F_RESV_8_1
) }, { F (F_OP_7_8
) }, { 0 } }
178 static const CGEN_IFMT ifmt_lf_ftoi_s ATTRIBUTE_UNUSED
= {
179 32, 32, 0xfc00ffff, { { F (F_OPCODE
) }, { F (F_R1
) }, { F (F_R2
) }, { F (F_R3
) }, { F (F_RESV_10_3
) }, { F (F_OP_7_8
) }, { 0 } }
182 static const CGEN_IFMT ifmt_lf_ftoi_d32 ATTRIBUTE_UNUSED
= {
183 32, 32, 0xfc00f9ff, { { F (F_OPCODE
) }, { F (F_R3
) }, { F (F_RDD32
) }, { F (F_RAD32
) }, { F (F_RESV_8_1
) }, { F (F_OP_7_8
) }, { 0 } }
186 static const CGEN_IFMT ifmt_lf_sfeq_s ATTRIBUTE_UNUSED
= {
187 32, 32, 0xffe007ff, { { F (F_OPCODE
) }, { F (F_R1
) }, { F (F_R2
) }, { F (F_R3
) }, { F (F_RESV_10_3
) }, { F (F_OP_7_8
) }, { 0 } }
190 static const CGEN_IFMT ifmt_lf_sfeq_d32 ATTRIBUTE_UNUSED
= {
191 32, 32, 0xffe004ff, { { F (F_OPCODE
) }, { F (F_R1
) }, { F (F_RESV_10_1
) }, { F (F_RAD32
) }, { F (F_RBD32
) }, { F (F_OP_7_8
) }, { 0 } }
194 static const CGEN_IFMT ifmt_lf_cust1_s ATTRIBUTE_UNUSED
= {
195 32, 32, 0xffe007ff, { { F (F_OPCODE
) }, { F (F_RESV_25_5
) }, { F (F_R2
) }, { F (F_R3
) }, { F (F_RESV_10_3
) }, { F (F_OP_7_8
) }, { 0 } }
198 static const CGEN_IFMT ifmt_lf_cust1_d32 ATTRIBUTE_UNUSED
= {
199 32, 32, 0xffe004ff, { { F (F_OPCODE
) }, { F (F_RESV_25_5
) }, { F (F_RESV_10_1
) }, { F (F_RAD32
) }, { F (F_RBD32
) }, { F (F_OP_7_8
) }, { 0 } }
204 #define A(a) (1 << CGEN_INSN_##a)
205 #define OPERAND(op) OR1K_OPERAND_##op
206 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
207 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
209 /* The instruction table. */
211 static const CGEN_OPCODE or1k_cgen_insn_opcode_table
[MAX_INSNS
] =
213 /* Special null first entry.
214 A `num' value of zero is thus invalid.
215 Also, the special `invalid' insn resides here. */
216 { { 0, 0, 0, 0 }, {{0}}, 0, {0}},
220 { { MNEM
, ' ', OP (DISP26
), 0 } },
223 /* l.adrp $rD,${disp21} */
226 { { MNEM
, ' ', OP (RD
), ',', OP (DISP21
), 0 } },
227 & ifmt_l_adrp
, { 0x8000000 }
229 /* l.jal ${disp26} */
232 { { MNEM
, ' ', OP (DISP26
), 0 } },
233 & ifmt_l_j
, { 0x4000000 }
238 { { MNEM
, ' ', OP (RB
), 0 } },
239 & ifmt_l_jr
, { 0x44000000 }
244 { { MNEM
, ' ', OP (RB
), 0 } },
245 & ifmt_l_jr
, { 0x48000000 }
247 /* l.bnf ${disp26} */
250 { { MNEM
, ' ', OP (DISP26
), 0 } },
251 & ifmt_l_j
, { 0xc000000 }
256 { { MNEM
, ' ', OP (DISP26
), 0 } },
257 & ifmt_l_j
, { 0x10000000 }
259 /* l.trap ${uimm16} */
262 { { MNEM
, ' ', OP (UIMM16
), 0 } },
263 & ifmt_l_trap
, { 0x21000000 }
265 /* l.sys ${uimm16} */
268 { { MNEM
, ' ', OP (UIMM16
), 0 } },
269 & ifmt_l_trap
, { 0x20000000 }
275 & ifmt_l_msync
, { 0x22000000 }
281 & ifmt_l_msync
, { 0x22800000 }
287 & ifmt_l_msync
, { 0x23000000 }
293 & ifmt_l_rfe
, { 0x24000000 }
295 /* l.nop ${uimm16} */
298 { { MNEM
, ' ', OP (UIMM16
), 0 } },
299 & ifmt_l_nop_imm
, { 0x15000000 }
305 & ifmt_l_nop_imm
, { 0x15000000 }
307 /* l.movhi $rD,$uimm16 */
310 { { MNEM
, ' ', OP (RD
), ',', OP (UIMM16
), 0 } },
311 & ifmt_l_movhi
, { 0x18000000 }
316 { { MNEM
, ' ', OP (RD
), 0 } },
317 & ifmt_l_macrc
, { 0x18010000 }
319 /* l.mfspr $rD,$rA,${uimm16} */
322 { { MNEM
, ' ', OP (RD
), ',', OP (RA
), ',', OP (UIMM16
), 0 } },
323 & ifmt_l_mfspr
, { 0xb4000000 }
325 /* l.mtspr $rA,$rB,${uimm16-split} */
328 { { MNEM
, ' ', OP (RA
), ',', OP (RB
), ',', OP (UIMM16_SPLIT
), 0 } },
329 & ifmt_l_mtspr
, { 0xc0000000 }
331 /* l.lwz $rD,${simm16}($rA) */
334 { { MNEM
, ' ', OP (RD
), ',', OP (SIMM16
), '(', OP (RA
), ')', 0 } },
335 & ifmt_l_lwz
, { 0x84000000 }
337 /* l.lws $rD,${simm16}($rA) */
340 { { MNEM
, ' ', OP (RD
), ',', OP (SIMM16
), '(', OP (RA
), ')', 0 } },
341 & ifmt_l_lwz
, { 0x88000000 }
343 /* l.lwa $rD,${simm16}($rA) */
346 { { MNEM
, ' ', OP (RD
), ',', OP (SIMM16
), '(', OP (RA
), ')', 0 } },
347 & ifmt_l_lwz
, { 0x6c000000 }
349 /* l.lbz $rD,${simm16}($rA) */
352 { { MNEM
, ' ', OP (RD
), ',', OP (SIMM16
), '(', OP (RA
), ')', 0 } },
353 & ifmt_l_lwz
, { 0x8c000000 }
355 /* l.lbs $rD,${simm16}($rA) */
358 { { MNEM
, ' ', OP (RD
), ',', OP (SIMM16
), '(', OP (RA
), ')', 0 } },
359 & ifmt_l_lwz
, { 0x90000000 }
361 /* l.lhz $rD,${simm16}($rA) */
364 { { MNEM
, ' ', OP (RD
), ',', OP (SIMM16
), '(', OP (RA
), ')', 0 } },
365 & ifmt_l_lwz
, { 0x94000000 }
367 /* l.lhs $rD,${simm16}($rA) */
370 { { MNEM
, ' ', OP (RD
), ',', OP (SIMM16
), '(', OP (RA
), ')', 0 } },
371 & ifmt_l_lwz
, { 0x98000000 }
373 /* l.sw ${simm16-split}($rA),$rB */
376 { { MNEM
, ' ', OP (SIMM16_SPLIT
), '(', OP (RA
), ')', ',', OP (RB
), 0 } },
377 & ifmt_l_sw
, { 0xd4000000 }
379 /* l.sb ${simm16-split}($rA),$rB */
382 { { MNEM
, ' ', OP (SIMM16_SPLIT
), '(', OP (RA
), ')', ',', OP (RB
), 0 } },
383 & ifmt_l_sw
, { 0xd8000000 }
385 /* l.sh ${simm16-split}($rA),$rB */
388 { { MNEM
, ' ', OP (SIMM16_SPLIT
), '(', OP (RA
), ')', ',', OP (RB
), 0 } },
389 & ifmt_l_sw
, { 0xdc000000 }
391 /* l.swa ${simm16-split}($rA),$rB */
394 { { MNEM
, ' ', OP (SIMM16_SPLIT
), '(', OP (RA
), ')', ',', OP (RB
), 0 } },
395 & ifmt_l_swa
, { 0xcc000000 }
397 /* l.sll $rD,$rA,$rB */
400 { { MNEM
, ' ', OP (RD
), ',', OP (RA
), ',', OP (RB
), 0 } },
401 & ifmt_l_sll
, { 0xe0000008 }
403 /* l.slli $rD,$rA,${uimm6} */
406 { { MNEM
, ' ', OP (RD
), ',', OP (RA
), ',', OP (UIMM6
), 0 } },
407 & ifmt_l_slli
, { 0xb8000000 }
409 /* l.srl $rD,$rA,$rB */
412 { { MNEM
, ' ', OP (RD
), ',', OP (RA
), ',', OP (RB
), 0 } },
413 & ifmt_l_sll
, { 0xe0000048 }
415 /* l.srli $rD,$rA,${uimm6} */
418 { { MNEM
, ' ', OP (RD
), ',', OP (RA
), ',', OP (UIMM6
), 0 } },
419 & ifmt_l_slli
, { 0xb8000040 }
421 /* l.sra $rD,$rA,$rB */
424 { { MNEM
, ' ', OP (RD
), ',', OP (RA
), ',', OP (RB
), 0 } },
425 & ifmt_l_sll
, { 0xe0000088 }
427 /* l.srai $rD,$rA,${uimm6} */
430 { { MNEM
, ' ', OP (RD
), ',', OP (RA
), ',', OP (UIMM6
), 0 } },
431 & ifmt_l_slli
, { 0xb8000080 }
433 /* l.ror $rD,$rA,$rB */
436 { { MNEM
, ' ', OP (RD
), ',', OP (RA
), ',', OP (RB
), 0 } },
437 & ifmt_l_sll
, { 0xe00000c8 }
439 /* l.rori $rD,$rA,${uimm6} */
442 { { MNEM
, ' ', OP (RD
), ',', OP (RA
), ',', OP (UIMM6
), 0 } },
443 & ifmt_l_slli
, { 0xb80000c0 }
445 /* l.and $rD,$rA,$rB */
448 { { MNEM
, ' ', OP (RD
), ',', OP (RA
), ',', OP (RB
), 0 } },
449 & ifmt_l_and
, { 0xe0000003 }
451 /* l.or $rD,$rA,$rB */
454 { { MNEM
, ' ', OP (RD
), ',', OP (RA
), ',', OP (RB
), 0 } },
455 & ifmt_l_and
, { 0xe0000004 }
457 /* l.xor $rD,$rA,$rB */
460 { { MNEM
, ' ', OP (RD
), ',', OP (RA
), ',', OP (RB
), 0 } },
461 & ifmt_l_and
, { 0xe0000005 }
463 /* l.add $rD,$rA,$rB */
466 { { MNEM
, ' ', OP (RD
), ',', OP (RA
), ',', OP (RB
), 0 } },
467 & ifmt_l_and
, { 0xe0000000 }
469 /* l.sub $rD,$rA,$rB */
472 { { MNEM
, ' ', OP (RD
), ',', OP (RA
), ',', OP (RB
), 0 } },
473 & ifmt_l_and
, { 0xe0000002 }
475 /* l.addc $rD,$rA,$rB */
478 { { MNEM
, ' ', OP (RD
), ',', OP (RA
), ',', OP (RB
), 0 } },
479 & ifmt_l_and
, { 0xe0000001 }
481 /* l.mul $rD,$rA,$rB */
484 { { MNEM
, ' ', OP (RD
), ',', OP (RA
), ',', OP (RB
), 0 } },
485 & ifmt_l_and
, { 0xe0000306 }
490 { { MNEM
, ' ', OP (RA
), ',', OP (RB
), 0 } },
491 & ifmt_l_muld
, { 0xe0000307 }
493 /* l.mulu $rD,$rA,$rB */
496 { { MNEM
, ' ', OP (RD
), ',', OP (RA
), ',', OP (RB
), 0 } },
497 & ifmt_l_and
, { 0xe000030b }
499 /* l.muldu $rA,$rB */
502 { { MNEM
, ' ', OP (RA
), ',', OP (RB
), 0 } },
503 & ifmt_l_muld
, { 0xe000030d }
505 /* l.div $rD,$rA,$rB */
508 { { MNEM
, ' ', OP (RD
), ',', OP (RA
), ',', OP (RB
), 0 } },
509 & ifmt_l_and
, { 0xe0000309 }
511 /* l.divu $rD,$rA,$rB */
514 { { MNEM
, ' ', OP (RD
), ',', OP (RA
), ',', OP (RB
), 0 } },
515 & ifmt_l_and
, { 0xe000030a }
520 { { MNEM
, ' ', OP (RD
), ',', OP (RA
), 0 } },
521 & ifmt_l_and
, { 0xe000000f }
526 { { MNEM
, ' ', OP (RD
), ',', OP (RA
), 0 } },
527 & ifmt_l_and
, { 0xe000010f }
529 /* l.andi $rD,$rA,$uimm16 */
532 { { MNEM
, ' ', OP (RD
), ',', OP (RA
), ',', OP (UIMM16
), 0 } },
533 & ifmt_l_mfspr
, { 0xa4000000 }
535 /* l.ori $rD,$rA,$uimm16 */
538 { { MNEM
, ' ', OP (RD
), ',', OP (RA
), ',', OP (UIMM16
), 0 } },
539 & ifmt_l_mfspr
, { 0xa8000000 }
541 /* l.xori $rD,$rA,$simm16 */
544 { { MNEM
, ' ', OP (RD
), ',', OP (RA
), ',', OP (SIMM16
), 0 } },
545 & ifmt_l_lwz
, { 0xac000000 }
547 /* l.addi $rD,$rA,$simm16 */
550 { { MNEM
, ' ', OP (RD
), ',', OP (RA
), ',', OP (SIMM16
), 0 } },
551 & ifmt_l_lwz
, { 0x9c000000 }
553 /* l.addic $rD,$rA,$simm16 */
556 { { MNEM
, ' ', OP (RD
), ',', OP (RA
), ',', OP (SIMM16
), 0 } },
557 & ifmt_l_lwz
, { 0xa0000000 }
559 /* l.muli $rD,$rA,$simm16 */
562 { { MNEM
, ' ', OP (RD
), ',', OP (RA
), ',', OP (SIMM16
), 0 } },
563 & ifmt_l_lwz
, { 0xb0000000 }
565 /* l.exths $rD,$rA */
568 { { MNEM
, ' ', OP (RD
), ',', OP (RA
), 0 } },
569 & ifmt_l_exths
, { 0xe000000c }
571 /* l.extbs $rD,$rA */
574 { { MNEM
, ' ', OP (RD
), ',', OP (RA
), 0 } },
575 & ifmt_l_exths
, { 0xe000004c }
577 /* l.exthz $rD,$rA */
580 { { MNEM
, ' ', OP (RD
), ',', OP (RA
), 0 } },
581 & ifmt_l_exths
, { 0xe000008c }
583 /* l.extbz $rD,$rA */
586 { { MNEM
, ' ', OP (RD
), ',', OP (RA
), 0 } },
587 & ifmt_l_exths
, { 0xe00000cc }
589 /* l.extws $rD,$rA */
592 { { MNEM
, ' ', OP (RD
), ',', OP (RA
), 0 } },
593 & ifmt_l_exths
, { 0xe000000d }
595 /* l.extwz $rD,$rA */
598 { { MNEM
, ' ', OP (RD
), ',', OP (RA
), 0 } },
599 & ifmt_l_exths
, { 0xe000004d }
601 /* l.cmov $rD,$rA,$rB */
604 { { MNEM
, ' ', OP (RD
), ',', OP (RA
), ',', OP (RB
), 0 } },
605 & ifmt_l_cmov
, { 0xe000000e }
607 /* l.sfgts $rA,$rB */
610 { { MNEM
, ' ', OP (RA
), ',', OP (RB
), 0 } },
611 & ifmt_l_sfgts
, { 0xe5400000 }
613 /* l.sfgtsi $rA,$simm16 */
616 { { MNEM
, ' ', OP (RA
), ',', OP (SIMM16
), 0 } },
617 & ifmt_l_sfgtsi
, { 0xbd400000 }
619 /* l.sfgtu $rA,$rB */
622 { { MNEM
, ' ', OP (RA
), ',', OP (RB
), 0 } },
623 & ifmt_l_sfgts
, { 0xe4400000 }
625 /* l.sfgtui $rA,$simm16 */
628 { { MNEM
, ' ', OP (RA
), ',', OP (SIMM16
), 0 } },
629 & ifmt_l_sfgtsi
, { 0xbc400000 }
631 /* l.sfges $rA,$rB */
634 { { MNEM
, ' ', OP (RA
), ',', OP (RB
), 0 } },
635 & ifmt_l_sfgts
, { 0xe5600000 }
637 /* l.sfgesi $rA,$simm16 */
640 { { MNEM
, ' ', OP (RA
), ',', OP (SIMM16
), 0 } },
641 & ifmt_l_sfgtsi
, { 0xbd600000 }
643 /* l.sfgeu $rA,$rB */
646 { { MNEM
, ' ', OP (RA
), ',', OP (RB
), 0 } },
647 & ifmt_l_sfgts
, { 0xe4600000 }
649 /* l.sfgeui $rA,$simm16 */
652 { { MNEM
, ' ', OP (RA
), ',', OP (SIMM16
), 0 } },
653 & ifmt_l_sfgtsi
, { 0xbc600000 }
655 /* l.sflts $rA,$rB */
658 { { MNEM
, ' ', OP (RA
), ',', OP (RB
), 0 } },
659 & ifmt_l_sfgts
, { 0xe5800000 }
661 /* l.sfltsi $rA,$simm16 */
664 { { MNEM
, ' ', OP (RA
), ',', OP (SIMM16
), 0 } },
665 & ifmt_l_sfgtsi
, { 0xbd800000 }
667 /* l.sfltu $rA,$rB */
670 { { MNEM
, ' ', OP (RA
), ',', OP (RB
), 0 } },
671 & ifmt_l_sfgts
, { 0xe4800000 }
673 /* l.sfltui $rA,$simm16 */
676 { { MNEM
, ' ', OP (RA
), ',', OP (SIMM16
), 0 } },
677 & ifmt_l_sfgtsi
, { 0xbc800000 }
679 /* l.sfles $rA,$rB */
682 { { MNEM
, ' ', OP (RA
), ',', OP (RB
), 0 } },
683 & ifmt_l_sfgts
, { 0xe5a00000 }
685 /* l.sflesi $rA,$simm16 */
688 { { MNEM
, ' ', OP (RA
), ',', OP (SIMM16
), 0 } },
689 & ifmt_l_sfgtsi
, { 0xbda00000 }
691 /* l.sfleu $rA,$rB */
694 { { MNEM
, ' ', OP (RA
), ',', OP (RB
), 0 } },
695 & ifmt_l_sfgts
, { 0xe4a00000 }
697 /* l.sfleui $rA,$simm16 */
700 { { MNEM
, ' ', OP (RA
), ',', OP (SIMM16
), 0 } },
701 & ifmt_l_sfgtsi
, { 0xbca00000 }
706 { { MNEM
, ' ', OP (RA
), ',', OP (RB
), 0 } },
707 & ifmt_l_sfgts
, { 0xe4000000 }
709 /* l.sfeqi $rA,$simm16 */
712 { { MNEM
, ' ', OP (RA
), ',', OP (SIMM16
), 0 } },
713 & ifmt_l_sfgtsi
, { 0xbc000000 }
718 { { MNEM
, ' ', OP (RA
), ',', OP (RB
), 0 } },
719 & ifmt_l_sfgts
, { 0xe4200000 }
721 /* l.sfnei $rA,$simm16 */
724 { { MNEM
, ' ', OP (RA
), ',', OP (SIMM16
), 0 } },
725 & ifmt_l_sfgtsi
, { 0xbc200000 }
730 { { MNEM
, ' ', OP (RA
), ',', OP (RB
), 0 } },
731 & ifmt_l_mac
, { 0xc4000001 }
733 /* l.maci $rA,${simm16} */
736 { { MNEM
, ' ', OP (RA
), ',', OP (SIMM16
), 0 } },
737 & ifmt_l_maci
, { 0x4c000000 }
742 { { MNEM
, ' ', OP (RA
), ',', OP (RB
), 0 } },
743 & ifmt_l_mac
, { 0xc4000003 }
748 { { MNEM
, ' ', OP (RA
), ',', OP (RB
), 0 } },
749 & ifmt_l_mac
, { 0xc4000002 }
754 { { MNEM
, ' ', OP (RA
), ',', OP (RB
), 0 } },
755 & ifmt_l_mac
, { 0xc4000004 }
761 & ifmt_l_rfe
, { 0x70000000 }
767 & ifmt_l_rfe
, { 0x74000000 }
773 & ifmt_l_rfe
, { 0x78000000 }
779 & ifmt_l_rfe
, { 0x7c000000 }
785 & ifmt_l_rfe
, { 0xf0000000 }
791 & ifmt_l_rfe
, { 0xf4000000 }
797 & ifmt_l_rfe
, { 0xf8000000 }
803 & ifmt_l_rfe
, { 0xfc000000 }
805 /* lf.add.s $rDSF,$rASF,$rBSF */
808 { { MNEM
, ' ', OP (RDSF
), ',', OP (RASF
), ',', OP (RBSF
), 0 } },
809 & ifmt_lf_add_s
, { 0xc8000000 }
811 /* lf.add.d $rDD32F,$rAD32F,$rBD32F */
814 { { MNEM
, ' ', OP (RDD32F
), ',', OP (RAD32F
), ',', OP (RBD32F
), 0 } },
815 & ifmt_lf_add_d32
, { 0xc8000010 }
817 /* lf.sub.s $rDSF,$rASF,$rBSF */
820 { { MNEM
, ' ', OP (RDSF
), ',', OP (RASF
), ',', OP (RBSF
), 0 } },
821 & ifmt_lf_add_s
, { 0xc8000001 }
823 /* lf.sub.d $rDD32F,$rAD32F,$rBD32F */
826 { { MNEM
, ' ', OP (RDD32F
), ',', OP (RAD32F
), ',', OP (RBD32F
), 0 } },
827 & ifmt_lf_add_d32
, { 0xc8000011 }
829 /* lf.mul.s $rDSF,$rASF,$rBSF */
832 { { MNEM
, ' ', OP (RDSF
), ',', OP (RASF
), ',', OP (RBSF
), 0 } },
833 & ifmt_lf_add_s
, { 0xc8000002 }
835 /* lf.mul.d $rDD32F,$rAD32F,$rBD32F */
838 { { MNEM
, ' ', OP (RDD32F
), ',', OP (RAD32F
), ',', OP (RBD32F
), 0 } },
839 & ifmt_lf_add_d32
, { 0xc8000012 }
841 /* lf.div.s $rDSF,$rASF,$rBSF */
844 { { MNEM
, ' ', OP (RDSF
), ',', OP (RASF
), ',', OP (RBSF
), 0 } },
845 & ifmt_lf_add_s
, { 0xc8000003 }
847 /* lf.div.d $rDD32F,$rAD32F,$rBD32F */
850 { { MNEM
, ' ', OP (RDD32F
), ',', OP (RAD32F
), ',', OP (RBD32F
), 0 } },
851 & ifmt_lf_add_d32
, { 0xc8000013 }
853 /* lf.rem.s $rDSF,$rASF,$rBSF */
856 { { MNEM
, ' ', OP (RDSF
), ',', OP (RASF
), ',', OP (RBSF
), 0 } },
857 & ifmt_lf_add_s
, { 0xc8000006 }
859 /* lf.rem.d $rDD32F,$rAD32F,$rBD32F */
862 { { MNEM
, ' ', OP (RDD32F
), ',', OP (RAD32F
), ',', OP (RBD32F
), 0 } },
863 & ifmt_lf_add_d32
, { 0xc8000016 }
865 /* lf.itof.s $rDSF,$rA */
868 { { MNEM
, ' ', OP (RDSF
), ',', OP (RA
), 0 } },
869 & ifmt_lf_itof_s
, { 0xc8000004 }
871 /* lf.itof.d $rDD32F,$rADI */
874 { { MNEM
, ' ', OP (RDD32F
), ',', OP (RADI
), 0 } },
875 & ifmt_lf_itof_d32
, { 0xc8000014 }
877 /* lf.ftoi.s $rD,$rASF */
880 { { MNEM
, ' ', OP (RD
), ',', OP (RASF
), 0 } },
881 & ifmt_lf_ftoi_s
, { 0xc8000005 }
883 /* lf.ftoi.d $rDDI,$rAD32F */
886 { { MNEM
, ' ', OP (RDDI
), ',', OP (RAD32F
), 0 } },
887 & ifmt_lf_ftoi_d32
, { 0xc8000015 }
889 /* lf.sfeq.s $rASF,$rBSF */
892 { { MNEM
, ' ', OP (RASF
), ',', OP (RBSF
), 0 } },
893 & ifmt_lf_sfeq_s
, { 0xc8000008 }
895 /* lf.sfeq.d $rAD32F,$rBD32F */
898 { { MNEM
, ' ', OP (RAD32F
), ',', OP (RBD32F
), 0 } },
899 & ifmt_lf_sfeq_d32
, { 0xc8000018 }
901 /* lf.sfne.s $rASF,$rBSF */
904 { { MNEM
, ' ', OP (RASF
), ',', OP (RBSF
), 0 } },
905 & ifmt_lf_sfeq_s
, { 0xc8000009 }
907 /* lf.sfne.d $rAD32F,$rBD32F */
910 { { MNEM
, ' ', OP (RAD32F
), ',', OP (RBD32F
), 0 } },
911 & ifmt_lf_sfeq_d32
, { 0xc8000019 }
913 /* lf.sfge.s $rASF,$rBSF */
916 { { MNEM
, ' ', OP (RASF
), ',', OP (RBSF
), 0 } },
917 & ifmt_lf_sfeq_s
, { 0xc800000b }
919 /* lf.sfge.d $rAD32F,$rBD32F */
922 { { MNEM
, ' ', OP (RAD32F
), ',', OP (RBD32F
), 0 } },
923 & ifmt_lf_sfeq_d32
, { 0xc800001b }
925 /* lf.sfgt.s $rASF,$rBSF */
928 { { MNEM
, ' ', OP (RASF
), ',', OP (RBSF
), 0 } },
929 & ifmt_lf_sfeq_s
, { 0xc800000a }
931 /* lf.sfgt.d $rAD32F,$rBD32F */
934 { { MNEM
, ' ', OP (RAD32F
), ',', OP (RBD32F
), 0 } },
935 & ifmt_lf_sfeq_d32
, { 0xc800001a }
937 /* lf.sflt.s $rASF,$rBSF */
940 { { MNEM
, ' ', OP (RASF
), ',', OP (RBSF
), 0 } },
941 & ifmt_lf_sfeq_s
, { 0xc800000c }
943 /* lf.sflt.d $rAD32F,$rBD32F */
946 { { MNEM
, ' ', OP (RAD32F
), ',', OP (RBD32F
), 0 } },
947 & ifmt_lf_sfeq_d32
, { 0xc800001c }
949 /* lf.sfle.s $rASF,$rBSF */
952 { { MNEM
, ' ', OP (RASF
), ',', OP (RBSF
), 0 } },
953 & ifmt_lf_sfeq_s
, { 0xc800000d }
955 /* lf.sfle.d $rAD32F,$rBD32F */
958 { { MNEM
, ' ', OP (RAD32F
), ',', OP (RBD32F
), 0 } },
959 & ifmt_lf_sfeq_d32
, { 0xc800001d }
961 /* lf.sfueq.s $rASF,$rBSF */
964 { { MNEM
, ' ', OP (RASF
), ',', OP (RBSF
), 0 } },
965 & ifmt_lf_sfeq_s
, { 0xc8000028 }
967 /* lf.sfueq.d $rAD32F,$rBD32F */
970 { { MNEM
, ' ', OP (RAD32F
), ',', OP (RBD32F
), 0 } },
971 & ifmt_lf_sfeq_d32
, { 0xc8000038 }
973 /* lf.sfune.s $rASF,$rBSF */
976 { { MNEM
, ' ', OP (RASF
), ',', OP (RBSF
), 0 } },
977 & ifmt_lf_sfeq_s
, { 0xc8000029 }
979 /* lf.sfune.d $rAD32F,$rBD32F */
982 { { MNEM
, ' ', OP (RAD32F
), ',', OP (RBD32F
), 0 } },
983 & ifmt_lf_sfeq_d32
, { 0xc8000039 }
985 /* lf.sfugt.s $rASF,$rBSF */
988 { { MNEM
, ' ', OP (RASF
), ',', OP (RBSF
), 0 } },
989 & ifmt_lf_sfeq_s
, { 0xc800002a }
991 /* lf.sfugt.d $rAD32F,$rBD32F */
994 { { MNEM
, ' ', OP (RAD32F
), ',', OP (RBD32F
), 0 } },
995 & ifmt_lf_sfeq_d32
, { 0xc800003a }
997 /* lf.sfuge.s $rASF,$rBSF */
1000 { { MNEM
, ' ', OP (RASF
), ',', OP (RBSF
), 0 } },
1001 & ifmt_lf_sfeq_s
, { 0xc800002b }
1003 /* lf.sfuge.d $rAD32F,$rBD32F */
1006 { { MNEM
, ' ', OP (RAD32F
), ',', OP (RBD32F
), 0 } },
1007 & ifmt_lf_sfeq_d32
, { 0xc800003b }
1009 /* lf.sfult.s $rASF,$rBSF */
1012 { { MNEM
, ' ', OP (RASF
), ',', OP (RBSF
), 0 } },
1013 & ifmt_lf_sfeq_s
, { 0xc800002c }
1015 /* lf.sfult.d $rAD32F,$rBD32F */
1018 { { MNEM
, ' ', OP (RAD32F
), ',', OP (RBD32F
), 0 } },
1019 & ifmt_lf_sfeq_d32
, { 0xc800003c }
1021 /* lf.sfule.s $rASF,$rBSF */
1024 { { MNEM
, ' ', OP (RASF
), ',', OP (RBSF
), 0 } },
1025 & ifmt_lf_sfeq_s
, { 0xc800002d }
1027 /* lf.sfule.d $rAD32F,$rBD32F */
1030 { { MNEM
, ' ', OP (RAD32F
), ',', OP (RBD32F
), 0 } },
1031 & ifmt_lf_sfeq_d32
, { 0xc800003d }
1033 /* lf.sfun.s $rASF,$rBSF */
1036 { { MNEM
, ' ', OP (RASF
), ',', OP (RBSF
), 0 } },
1037 & ifmt_lf_sfeq_s
, { 0xc800002e }
1039 /* lf.sfun.d $rAD32F,$rBD32F */
1042 { { MNEM
, ' ', OP (RAD32F
), ',', OP (RBD32F
), 0 } },
1043 & ifmt_lf_sfeq_d32
, { 0xc800003e }
1045 /* lf.madd.s $rDSF,$rASF,$rBSF */
1048 { { MNEM
, ' ', OP (RDSF
), ',', OP (RASF
), ',', OP (RBSF
), 0 } },
1049 & ifmt_lf_add_s
, { 0xc8000007 }
1051 /* lf.madd.d $rDD32F,$rAD32F,$rBD32F */
1054 { { MNEM
, ' ', OP (RDD32F
), ',', OP (RAD32F
), ',', OP (RBD32F
), 0 } },
1055 & ifmt_lf_add_d32
, { 0xc8000017 }
1057 /* lf.cust1.s $rASF,$rBSF */
1060 { { MNEM
, ' ', OP (RASF
), ',', OP (RBSF
), 0 } },
1061 & ifmt_lf_cust1_s
, { 0xc80000d0 }
1067 & ifmt_lf_cust1_d32
, { 0xc80000e0 }
1076 /* Formats for ALIAS macro-insns. */
1078 #define F(f) & or1k_cgen_ifld_table[OR1K_##f]
1081 /* Each non-simple macro entry points to an array of expansion possibilities. */
1083 #define A(a) (1 << CGEN_INSN_##a)
1084 #define OPERAND(op) OR1K_OPERAND_##op
1085 #define MNEM CGEN_SYNTAX_MNEMONIC /* syntax value for mnemonic */
1086 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
1088 /* The macro instruction table. */
1090 static const CGEN_IBASE or1k_cgen_macro_insn_table
[] =
1094 /* The macro instruction opcode table. */
1096 static const CGEN_OPCODE or1k_cgen_macro_insn_opcode_table
[] =
1105 #ifndef CGEN_ASM_HASH_P
1106 #define CGEN_ASM_HASH_P(insn) 1
1109 #ifndef CGEN_DIS_HASH_P
1110 #define CGEN_DIS_HASH_P(insn) 1
1113 /* Return non-zero if INSN is to be added to the hash table.
1114 Targets are free to override CGEN_{ASM,DIS}_HASH_P in the .opc file. */
1117 asm_hash_insn_p (const CGEN_INSN
*insn ATTRIBUTE_UNUSED
)
1119 return CGEN_ASM_HASH_P (insn
);
1123 dis_hash_insn_p (const CGEN_INSN
*insn
)
1125 /* If building the hash table and the NO-DIS attribute is present,
1127 if (CGEN_INSN_ATTR_VALUE (insn
, CGEN_INSN_NO_DIS
))
1129 return CGEN_DIS_HASH_P (insn
);
1132 #ifndef CGEN_ASM_HASH
1133 #define CGEN_ASM_HASH_SIZE 127
1134 #ifdef CGEN_MNEMONIC_OPERANDS
1135 #define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE)
1137 #define CGEN_ASM_HASH(mnem) (*(unsigned char *) (mnem) % CGEN_ASM_HASH_SIZE) /*FIXME*/
1141 /* It doesn't make much sense to provide a default here,
1142 but while this is under development we do.
1143 BUFFER is a pointer to the bytes of the insn, target order.
1144 VALUE is the first base_insn_bitsize bits as an int in host order. */
1146 #ifndef CGEN_DIS_HASH
1147 #define CGEN_DIS_HASH_SIZE 256
1148 #define CGEN_DIS_HASH(buf, value) (*(unsigned char *) (buf))
1151 /* The result is the hash value of the insn.
1152 Targets are free to override CGEN_{ASM,DIS}_HASH in the .opc file. */
1155 asm_hash_insn (const char *mnem
)
1157 return CGEN_ASM_HASH (mnem
);
1160 /* BUF is a pointer to the bytes of the insn, target order.
1161 VALUE is the first base_insn_bitsize bits as an int in host order. */
1164 dis_hash_insn (const char *buf ATTRIBUTE_UNUSED
,
1165 CGEN_INSN_INT value ATTRIBUTE_UNUSED
)
1167 return CGEN_DIS_HASH (buf
, value
);
1170 /* Set the recorded length of the insn in the CGEN_FIELDS struct. */
1173 set_fields_bitsize (CGEN_FIELDS
*fields
, int size
)
1175 CGEN_FIELDS_BITSIZE (fields
) = size
;
1178 /* Function to call before using the operand instance table.
1179 This plugs the opcode entries and macro instructions into the cpu table. */
1182 or1k_cgen_init_opcode_table (CGEN_CPU_DESC cd
)
1185 int num_macros
= (sizeof (or1k_cgen_macro_insn_table
) /
1186 sizeof (or1k_cgen_macro_insn_table
[0]));
1187 const CGEN_IBASE
*ib
= & or1k_cgen_macro_insn_table
[0];
1188 const CGEN_OPCODE
*oc
= & or1k_cgen_macro_insn_opcode_table
[0];
1189 CGEN_INSN
*insns
= xmalloc (num_macros
* sizeof (CGEN_INSN
));
1191 /* This test has been added to avoid a warning generated
1192 if memset is called with a third argument of value zero. */
1193 if (num_macros
>= 1)
1194 memset (insns
, 0, num_macros
* sizeof (CGEN_INSN
));
1195 for (i
= 0; i
< num_macros
; ++i
)
1197 insns
[i
].base
= &ib
[i
];
1198 insns
[i
].opcode
= &oc
[i
];
1199 or1k_cgen_build_insn_regex (& insns
[i
]);
1201 cd
->macro_insn_table
.init_entries
= insns
;
1202 cd
->macro_insn_table
.entry_size
= sizeof (CGEN_IBASE
);
1203 cd
->macro_insn_table
.num_init_entries
= num_macros
;
1205 oc
= & or1k_cgen_insn_opcode_table
[0];
1206 insns
= (CGEN_INSN
*) cd
->insn_table
.init_entries
;
1207 for (i
= 0; i
< MAX_INSNS
; ++i
)
1209 insns
[i
].opcode
= &oc
[i
];
1210 or1k_cgen_build_insn_regex (& insns
[i
]);
1213 cd
->sizeof_fields
= sizeof (CGEN_FIELDS
);
1214 cd
->set_fields_bitsize
= set_fields_bitsize
;
1216 cd
->asm_hash_p
= asm_hash_insn_p
;
1217 cd
->asm_hash
= asm_hash_insn
;
1218 cd
->asm_hash_size
= CGEN_ASM_HASH_SIZE
;
1220 cd
->dis_hash_p
= dis_hash_insn_p
;
1221 cd
->dis_hash
= dis_hash_insn
;
1222 cd
->dis_hash_size
= CGEN_DIS_HASH_SIZE
;