[binutils, ARM, 5/16] BF insns infrastructure with new global reloc R_ARM_THM_BF16
[binutils-gdb.git] / sim / bfin / dv-bfin_dma.h
blobf6d80485d73d26c6c977770ed8121994e0c20b84
1 /* Blackfin Direct Memory Access (DMA) Channel model.
3 Copyright (C) 2010-2019 Free Software Foundation, Inc.
4 Contributed by Analog Devices, Inc.
6 This file is part of simulators.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #ifndef DV_BFIN_DMA_H
22 #define DV_BFIN_DMA_H
24 /* DMA_CONFIG Masks */
25 #define DMAEN 0x0001 /* DMA Channel Enable */
26 #define WNR 0x0002 /* Channel Direction (W/R*) */
27 #define WDSIZE_8 0x0000 /* Transfer Word Size = 8 */
28 #define WDSIZE_16 0x0004 /* Transfer Word Size = 16 */
29 #define WDSIZE_32 0x0008 /* Transfer Word Size = 32 */
30 #define WDSIZE 0x000c /* Transfer Word Size */
31 #define DMA2D 0x0010 /* DMA Mode (2D/1D*) */
32 #define RESTART 0x0020 /* DMA Buffer Clear */
33 #define DI_SEL 0x0040 /* Data Interrupt Timing Select */
34 #define DI_EN 0x0080 /* Data Interrupt Enable */
35 #define NDSIZE_0 0x0000 /* Next Descriptor Size = 0 (Stop/Autobuffer) */
36 #define NDSIZE_1 0x0100 /* Next Descriptor Size = 1 */
37 #define NDSIZE_2 0x0200 /* Next Descriptor Size = 2 */
38 #define NDSIZE_3 0x0300 /* Next Descriptor Size = 3 */
39 #define NDSIZE_4 0x0400 /* Next Descriptor Size = 4 */
40 #define NDSIZE_5 0x0500 /* Next Descriptor Size = 5 */
41 #define NDSIZE_6 0x0600 /* Next Descriptor Size = 6 */
42 #define NDSIZE_7 0x0700 /* Next Descriptor Size = 7 */
43 #define NDSIZE_8 0x0800 /* Next Descriptor Size = 8 */
44 #define NDSIZE_9 0x0900 /* Next Descriptor Size = 9 */
45 #define NDSIZE 0x0f00 /* Next Descriptor Size */
46 #define NDSIZE_SHIFT 8
47 #define DMAFLOW 0x7000 /* Flow Control */
48 #define DMAFLOW_STOP 0x0000 /* Stop Mode */
49 #define DMAFLOW_AUTO 0x1000 /* Autobuffer Mode */
50 #define DMAFLOW_ARRAY 0x4000 /* Descriptor Array Mode */
51 #define DMAFLOW_SMALL 0x6000 /* Small Model Descriptor List Mode */
52 #define DMAFLOW_LARGE 0x7000 /* Large Model Descriptor List Mode */
54 /* DMA_IRQ_STATUS Masks */
55 #define DMA_DONE 0x0001 /* DMA Completion Interrupt Status */
56 #define DMA_ERR 0x0002 /* DMA Error Interrupt Status */
57 #define DFETCH 0x0004 /* DMA Descriptor Fetch Indicator */
58 #define DMA_RUN 0x0008 /* DMA Channel Running Indicator */
60 /* DMA_PERIPHERAL_MAP Masks */
61 #define CTYPE (1 << 6)
63 #endif