opcodes/m32r-dis.c

   1 /* Disassembler interface for targets using CGEN. -*- C -*-
   2    CGEN: Cpu tools GENerator
   3
   4    THIS FILE IS MACHINE GENERATED WITH CGEN.
   5    - the resultant file is machine generated, cgen-dis.in isn't
   6
   7    Copyright (C) 1996-2015 Free Software Foundation, Inc.
   8
   9    This file is part of libopcodes.
  10
  11    This library is free software; you can redistribute it and/or modify
  12    it under the terms of the GNU General Public License as published by
  13    the Free Software Foundation; either version 3, or (at your option)
  14    any later version.
  15
  16    It is distributed in the hope that it will be useful, but WITHOUT
  17    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  18    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  19    License for more details.
  20
  21    You should have received a copy of the GNU General Public License
  22    along with this program; if not, write to the Free Software Foundation, Inc.,
  23    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
  24
  25 /* ??? Eventually more and more of this stuff can go to cpu-independent files.
  26    Keep that in mind.  */
  27
  28 #include "sysdep.h"
  29 #include <stdio.h>
  30 #include "ansidecl.h"
  31 #include "dis-asm.h"
  32 #include "bfd.h"
  33 #include "symcat.h"
  34 #include "libiberty.h"
  35 #include "m32r-desc.h"
  36 #include "m32r-opc.h"
  37 #include "opintl.h"
  38
  39 /* Default text to print if an instruction isn't recognized.  */
  40 #define UNKNOWN_INSN_MSG _("*unknown*")
  41
  42 static void print_normal
  43   (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int);
  44 static void print_address
  45   (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED;
  46 static void print_keyword
  47   (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED;
  48 static void print_insn_normal
  49   (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int);
  50 static int print_insn
  51   (CGEN_CPU_DESC, bfd_vma,  disassemble_info *, bfd_byte *, unsigned);
  52 static int default_print_insn
  53   (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED;
  54 static int read_insn
  55   (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *,
  56    unsigned long *);
  57 \f
  58 /* -- disassembler routines inserted here.  */
  59
  60 /* -- dis.c */
  61
  62 /* Print signed operands with '#' prefixes.  */
  63
  64 static void
  65 print_signed_with_hash_prefix (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
  66                                void * dis_info,
  67                                long value,
  68                                unsigned int attrs ATTRIBUTE_UNUSED,
  69                                bfd_vma pc ATTRIBUTE_UNUSED,
  70                                int length ATTRIBUTE_UNUSED)
  71 {
  72   disassemble_info *info = (disassemble_info *) dis_info;
  73
  74   (*info->fprintf_func) (info->stream, "#");
  75   (*info->fprintf_func) (info->stream, "%ld", value);
  76 }
  77
  78 /* Print unsigned operands with '#' prefixes.  */
  79
  80 static void
  81 print_unsigned_with_hash_prefix (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
  82                                  void * dis_info,
  83                                  long value,
  84                                  unsigned int attrs ATTRIBUTE_UNUSED,
  85                                  bfd_vma pc ATTRIBUTE_UNUSED,
  86                                  int length ATTRIBUTE_UNUSED)
  87 {
  88   disassemble_info *info = (disassemble_info *) dis_info;
  89
  90   (*info->fprintf_func) (info->stream, "#");
  91   (*info->fprintf_func) (info->stream, "0x%lx", value);
  92 }
  93
  94 /* Handle '#' prefixes as operands.  */
  95
  96 static void
  97 print_hash (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
  98             void * dis_info,
  99             long value ATTRIBUTE_UNUSED,
 100             unsigned int attrs ATTRIBUTE_UNUSED,
 101             bfd_vma pc ATTRIBUTE_UNUSED,
 102             int length ATTRIBUTE_UNUSED)
 103 {
 104   disassemble_info *info = (disassemble_info *) dis_info;
 105
 106   (*info->fprintf_func) (info->stream, "#");
 107 }
 108
 109 #undef  CGEN_PRINT_INSN
 110 #define CGEN_PRINT_INSN my_print_insn
 111
 112 static int
 113 my_print_insn (CGEN_CPU_DESC cd,
 114                bfd_vma pc,
 115                disassemble_info *info)
 116 {
 117   bfd_byte buffer[CGEN_MAX_INSN_SIZE];
 118   bfd_byte *buf = buffer;
 119   int status;
 120   int buflen = (pc & 3) == 0 ? 4 : 2;
 121   int big_p = CGEN_CPU_INSN_ENDIAN (cd) == CGEN_ENDIAN_BIG;
 122   bfd_byte *x;
 123
 124   /* Read the base part of the insn.  */
 125
 126   status = (*info->read_memory_func) (pc - ((!big_p && (pc & 3) != 0) ? 2 : 0),
 127                                       buf, buflen, info);
 128   if (status != 0)
 129     {
 130       (*info->memory_error_func) (status, pc, info);
 131       return -1;
 132     }
 133
 134   /* 32 bit insn?  */
 135   x = (big_p ? &buf[0] : &buf[3]);
 136   if ((pc & 3) == 0 && (*x & 0x80) != 0)
 137     return print_insn (cd, pc, info, buf, buflen);
 138
 139   /* Print the first insn.  */
 140   if ((pc & 3) == 0)
 141     {
 142       buf += (big_p ? 0 : 2);
 143       if (print_insn (cd, pc, info, buf, 2) == 0)
 144         (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
 145       buf += (big_p ? 2 : -2);
 146     }
 147
 148   x = (big_p ? &buf[0] : &buf[1]);
 149   if (*x & 0x80)
 150     {
 151       /* Parallel.  */
 152       (*info->fprintf_func) (info->stream, " || ");
 153       *x &= 0x7f;
 154     }
 155   else
 156     (*info->fprintf_func) (info->stream, " -> ");
 157
 158   /* The "& 3" is to pass a consistent address.
 159      Parallel insns arguably both begin on the word boundary.
 160      Also, branch insns are calculated relative to the word boundary.  */
 161   if (print_insn (cd, pc & ~ (bfd_vma) 3, info, buf, 2) == 0)
 162     (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
 163
 164   return (pc & 3) ? 2 : 4;
 165 }
 166
 167 /* -- */
 168
 169 void m32r_cgen_print_operand
 170   (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int);
 171
 172 /* Main entry point for printing operands.
 173    XINFO is a `void *' and not a `disassemble_info *' to not put a requirement
 174    of dis-asm.h on cgen.h.
 175
 176    This function is basically just a big switch statement.  Earlier versions
 177    used tables to look up the function to use, but
 178    - if the table contains both assembler and disassembler functions then
 179      the disassembler contains much of the assembler and vice-versa,
 180    - there's a lot of inlining possibilities as things grow,
 181    - using a switch statement avoids the function call overhead.
 182
 183    This function could be moved into `print_insn_normal', but keeping it
 184    separate makes clear the interface between `print_insn_normal' and each of
 185    the handlers.  */
 186
 187 void
 188 m32r_cgen_print_operand (CGEN_CPU_DESC cd,
 189                            int opindex,
 190                            void * xinfo,
 191                            CGEN_FIELDS *fields,
 192                            void const *attrs ATTRIBUTE_UNUSED,
 193                            bfd_vma pc,
 194                            int length)
 195 {
 196   disassemble_info *info = (disassemble_info *) xinfo;
 197
 198   switch (opindex)
 199     {
 200     case M32R_OPERAND_ACC :
 201       print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_acc, 0);
 202       break;
 203     case M32R_OPERAND_ACCD :
 204       print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_accd, 0);
 205       break;
 206     case M32R_OPERAND_ACCS :
 207       print_keyword (cd, info, & m32r_cgen_opval_h_accums, fields->f_accs, 0);
 208       break;
 209     case M32R_OPERAND_DCR :
 210       print_keyword (cd, info, & m32r_cgen_opval_cr_names, fields->f_r1, 0);
 211       break;
 212     case M32R_OPERAND_DISP16 :
 213       print_address (cd, info, fields->f_disp16, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
 214       break;
 215     case M32R_OPERAND_DISP24 :
 216       print_address (cd, info, fields->f_disp24, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
 217       break;
 218     case M32R_OPERAND_DISP8 :
 219       print_address (cd, info, fields->f_disp8, 0|(1<<CGEN_OPERAND_RELAX)|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length);
 220       break;
 221     case M32R_OPERAND_DR :
 222       print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r1, 0);
 223       break;
 224     case M32R_OPERAND_HASH :
 225       print_hash (cd, info, 0, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
 226       break;
 227     case M32R_OPERAND_HI16 :
 228       print_normal (cd, info, fields->f_hi16, 0|(1<<CGEN_OPERAND_SIGN_OPT), pc, length);
 229       break;
 230     case M32R_OPERAND_IMM1 :
 231       print_unsigned_with_hash_prefix (cd, info, fields->f_imm1, 0, pc, length);
 232       break;
 233     case M32R_OPERAND_SCR :
 234       print_keyword (cd, info, & m32r_cgen_opval_cr_names, fields->f_r2, 0);
 235       break;
 236     case M32R_OPERAND_SIMM16 :
 237       print_signed_with_hash_prefix (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
 238       break;
 239     case M32R_OPERAND_SIMM8 :
 240       print_signed_with_hash_prefix (cd, info, fields->f_simm8, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
 241       break;
 242     case M32R_OPERAND_SLO16 :
 243       print_normal (cd, info, fields->f_simm16, 0|(1<<CGEN_OPERAND_SIGNED), pc, length);
 244       break;
 245     case M32R_OPERAND_SR :
 246       print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r2, 0);
 247       break;
 248     case M32R_OPERAND_SRC1 :
 249       print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r1, 0);
 250       break;
 251     case M32R_OPERAND_SRC2 :
 252       print_keyword (cd, info, & m32r_cgen_opval_gr_names, fields->f_r2, 0);
 253       break;
 254     case M32R_OPERAND_UIMM16 :
 255       print_unsigned_with_hash_prefix (cd, info, fields->f_uimm16, 0, pc, length);
 256       break;
 257     case M32R_OPERAND_UIMM24 :
 258       print_address (cd, info, fields->f_uimm24, 0|(1<<CGEN_OPERAND_RELOC)|(1<<CGEN_OPERAND_ABS_ADDR), pc, length);
 259       break;
 260     case M32R_OPERAND_UIMM3 :
 261       print_unsigned_with_hash_prefix (cd, info, fields->f_uimm3, 0, pc, length);
 262       break;
 263     case M32R_OPERAND_UIMM4 :
 264       print_unsigned_with_hash_prefix (cd, info, fields->f_uimm4, 0, pc, length);
 265       break;
 266     case M32R_OPERAND_UIMM5 :
 267       print_unsigned_with_hash_prefix (cd, info, fields->f_uimm5, 0, pc, length);
 268       break;
 269     case M32R_OPERAND_UIMM8 :
 270       print_unsigned_with_hash_prefix (cd, info, fields->f_uimm8, 0, pc, length);
 271       break;
 272     case M32R_OPERAND_ULO16 :
 273       print_normal (cd, info, fields->f_uimm16, 0, pc, length);
 274       break;
 275
 276     default :
 277       /* xgettext:c-format */
 278       fprintf (stderr, _("Unrecognized field %d while printing insn.\n"),
 279                opindex);
 280     abort ();
 281   }
 282 }
 283
 284 cgen_print_fn * const m32r_cgen_print_handlers[] =
 285 {
 286   print_insn_normal,
 287 };
 288
 289
 290 void
 291 m32r_cgen_init_dis (CGEN_CPU_DESC cd)
 292 {
 293   m32r_cgen_init_opcode_table (cd);
 294   m32r_cgen_init_ibld_table (cd);
 295   cd->print_handlers = & m32r_cgen_print_handlers[0];
 296   cd->print_operand = m32r_cgen_print_operand;
 297 }
 298
 299 \f
 300 /* Default print handler.  */
 301
 302 static void
 303 print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 304               void *dis_info,
 305               long value,
 306               unsigned int attrs,
 307               bfd_vma pc ATTRIBUTE_UNUSED,
 308               int length ATTRIBUTE_UNUSED)
 309 {
 310   disassemble_info *info = (disassemble_info *) dis_info;
 311
 312   /* Print the operand as directed by the attributes.  */
 313   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
 314     ; /* nothing to do */
 315   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
 316     (*info->fprintf_func) (info->stream, "%ld", value);
 317   else
 318     (*info->fprintf_func) (info->stream, "0x%lx", value);
 319 }
 320
 321 /* Default address handler.  */
 322
 323 static void
 324 print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 325                void *dis_info,
 326                bfd_vma value,
 327                unsigned int attrs,
 328                bfd_vma pc ATTRIBUTE_UNUSED,
 329                int length ATTRIBUTE_UNUSED)
 330 {
 331   disassemble_info *info = (disassemble_info *) dis_info;
 332
 333   /* Print the operand as directed by the attributes.  */
 334   if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY))
 335     ; /* Nothing to do.  */
 336   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR))
 337     (*info->print_address_func) (value, info);
 338   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR))
 339     (*info->print_address_func) (value, info);
 340   else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED))
 341     (*info->fprintf_func) (info->stream, "%ld", (long) value);
 342   else
 343     (*info->fprintf_func) (info->stream, "0x%lx", (long) value);
 344 }
 345
 346 /* Keyword print handler.  */
 347
 348 static void
 349 print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 350                void *dis_info,
 351                CGEN_KEYWORD *keyword_table,
 352                long value,
 353                unsigned int attrs ATTRIBUTE_UNUSED)
 354 {
 355   disassemble_info *info = (disassemble_info *) dis_info;
 356   const CGEN_KEYWORD_ENTRY *ke;
 357
 358   ke = cgen_keyword_lookup_value (keyword_table, value);
 359   if (ke != NULL)
 360     (*info->fprintf_func) (info->stream, "%s", ke->name);
 361   else
 362     (*info->fprintf_func) (info->stream, "???");
 363 }
 364 \f
 365 /* Default insn printer.
 366
 367    DIS_INFO is defined as `void *' so the disassembler needn't know anything
 368    about disassemble_info.  */
 369
 370 static void
 371 print_insn_normal (CGEN_CPU_DESC cd,
 372                    void *dis_info,
 373                    const CGEN_INSN *insn,
 374                    CGEN_FIELDS *fields,
 375                    bfd_vma pc,
 376                    int length)
 377 {
 378   const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn);
 379   disassemble_info *info = (disassemble_info *) dis_info;
 380   const CGEN_SYNTAX_CHAR_TYPE *syn;
 381
 382   CGEN_INIT_PRINT (cd);
 383
 384   for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn)
 385     {
 386       if (CGEN_SYNTAX_MNEMONIC_P (*syn))
 387         {
 388           (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn));
 389           continue;
 390         }
 391       if (CGEN_SYNTAX_CHAR_P (*syn))
 392         {
 393           (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn));
 394           continue;
 395         }
 396
 397       /* We have an operand.  */
 398       m32r_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info,
 399                                  fields, CGEN_INSN_ATTRS (insn), pc, length);
 400     }
 401 }
 402 \f
 403 /* Subroutine of print_insn. Reads an insn into the given buffers and updates
 404    the extract info.
 405    Returns 0 if all is well, non-zero otherwise.  */
 406
 407 static int
 408 read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED,
 409            bfd_vma pc,
 410            disassemble_info *info,
 411            bfd_byte *buf,
 412            int buflen,
 413            CGEN_EXTRACT_INFO *ex_info,
 414            unsigned long *insn_value)
 415 {
 416   int status = (*info->read_memory_func) (pc, buf, buflen, info);
 417
 418   if (status != 0)
 419     {
 420       (*info->memory_error_func) (status, pc, info);
 421       return -1;
 422     }
 423
 424   ex_info->dis_info = info;
 425   ex_info->valid = (1 << buflen) - 1;
 426   ex_info->insn_bytes = buf;
 427
 428   *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG);
 429   return 0;
 430 }
 431
 432 /* Utility to print an insn.
 433    BUF is the base part of the insn, target byte order, BUFLEN bytes long.
 434    The result is the size of the insn in bytes or zero for an unknown insn
 435    or -1 if an error occurs fetching data (memory_error_func will have
 436    been called).  */
 437
 438 static int
 439 print_insn (CGEN_CPU_DESC cd,
 440             bfd_vma pc,
 441             disassemble_info *info,
 442             bfd_byte *buf,
 443             unsigned int buflen)
 444 {
 445   CGEN_INSN_INT insn_value;
 446   const CGEN_INSN_LIST *insn_list;
 447   CGEN_EXTRACT_INFO ex_info;
 448   int basesize;
 449
 450   /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */
 451   basesize = cd->base_insn_bitsize < buflen * 8 ?
 452                                      cd->base_insn_bitsize : buflen * 8;
 453   insn_value = cgen_get_insn_value (cd, buf, basesize);
 454
 455
 456   /* Fill in ex_info fields like read_insn would.  Don't actually call
 457      read_insn, since the incoming buffer is already read (and possibly
 458      modified a la m32r).  */
 459   ex_info.valid = (1 << buflen) - 1;
 460   ex_info.dis_info = info;
 461   ex_info.insn_bytes = buf;
 462
 463   /* The instructions are stored in hash lists.
 464      Pick the first one and keep trying until we find the right one.  */
 465
 466   insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value);
 467   while (insn_list != NULL)
 468     {
 469       const CGEN_INSN *insn = insn_list->insn;
 470       CGEN_FIELDS fields;
 471       int length;
 472       unsigned long insn_value_cropped;
 473
 474 #ifdef CGEN_VALIDATE_INSN_SUPPORTED
 475       /* Not needed as insn shouldn't be in hash lists if not supported.  */
 476       /* Supported by this cpu?  */
 477       if (! m32r_cgen_insn_supported (cd, insn))
 478         {
 479           insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 480           continue;
 481         }
 482 #endif
 483
 484       /* Basic bit mask must be correct.  */
 485       /* ??? May wish to allow target to defer this check until the extract
 486          handler.  */
 487
 488       /* Base size may exceed this instruction's size.  Extract the
 489          relevant part from the buffer. */
 490       if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen &&
 491           (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
 492         insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn),
 493                                            info->endian == BFD_ENDIAN_BIG);
 494       else
 495         insn_value_cropped = insn_value;
 496
 497       if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn))
 498           == CGEN_INSN_BASE_VALUE (insn))
 499         {
 500           /* Printing is handled in two passes.  The first pass parses the
 501              machine insn and extracts the fields.  The second pass prints
 502              them.  */
 503
 504           /* Make sure the entire insn is loaded into insn_value, if it
 505              can fit.  */
 506           if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) &&
 507               (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long))
 508             {
 509               unsigned long full_insn_value;
 510               int rc = read_insn (cd, pc, info, buf,
 511                                   CGEN_INSN_BITSIZE (insn) / 8,
 512                                   & ex_info, & full_insn_value);
 513               if (rc != 0)
 514                 return rc;
 515               length = CGEN_EXTRACT_FN (cd, insn)
 516                 (cd, insn, &ex_info, full_insn_value, &fields, pc);
 517             }
 518           else
 519             length = CGEN_EXTRACT_FN (cd, insn)
 520               (cd, insn, &ex_info, insn_value_cropped, &fields, pc);
 521
 522           /* Length < 0 -> error.  */
 523           if (length < 0)
 524             return length;
 525           if (length > 0)
 526             {
 527               CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length);
 528               /* Length is in bits, result is in bytes.  */
 529               return length / 8;
 530             }
 531         }
 532
 533       insn_list = CGEN_DIS_NEXT_INSN (insn_list);
 534     }
 535
 536   return 0;
 537 }
 538
 539 /* Default value for CGEN_PRINT_INSN.
 540    The result is the size of the insn in bytes or zero for an unknown insn
 541    or -1 if an error occured fetching bytes.  */
 542
 543 #ifndef CGEN_PRINT_INSN
 544 #define CGEN_PRINT_INSN default_print_insn
 545 #endif
 546
 547 static int
 548 default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info)
 549 {
 550   bfd_byte buf[CGEN_MAX_INSN_SIZE];
 551   int buflen;
 552   int status;
 553
 554   /* Attempt to read the base part of the insn.  */
 555   buflen = cd->base_insn_bitsize / 8;
 556   status = (*info->read_memory_func) (pc, buf, buflen, info);
 557
 558   /* Try again with the minimum part, if min < base.  */
 559   if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize))
 560     {
 561       buflen = cd->min_insn_bitsize / 8;
 562       status = (*info->read_memory_func) (pc, buf, buflen, info);
 563     }
 564
 565   if (status != 0)
 566     {
 567       (*info->memory_error_func) (status, pc, info);
 568       return -1;
 569     }
 570
 571   return print_insn (cd, pc, info, buf, buflen);
 572 }
 573
 574 /* Main entry point.
 575    Print one instruction from PC on INFO->STREAM.
 576    Return the size of the instruction (in bytes).  */
 577
 578 typedef struct cpu_desc_list
 579 {
 580   struct cpu_desc_list *next;
 581   CGEN_BITSET *isa;
 582   int mach;
 583   int endian;
 584   CGEN_CPU_DESC cd;
 585 } cpu_desc_list;
 586
 587 int
 588 print_insn_m32r (bfd_vma pc, disassemble_info *info)
 589 {
 590   static cpu_desc_list *cd_list = 0;
 591   cpu_desc_list *cl = 0;
 592   static CGEN_CPU_DESC cd = 0;
 593   static CGEN_BITSET *prev_isa;
 594   static int prev_mach;
 595   static int prev_endian;
 596   int length;
 597   CGEN_BITSET *isa;
 598   int mach;
 599   int endian = (info->endian == BFD_ENDIAN_BIG
 600                 ? CGEN_ENDIAN_BIG
 601                 : CGEN_ENDIAN_LITTLE);
 602   enum bfd_architecture arch;
 603
 604   /* ??? gdb will set mach but leave the architecture as "unknown" */
 605 #ifndef CGEN_BFD_ARCH
 606 #define CGEN_BFD_ARCH bfd_arch_m32r
 607 #endif
 608   arch = info->arch;
 609   if (arch == bfd_arch_unknown)
 610     arch = CGEN_BFD_ARCH;
 611
 612   /* There's no standard way to compute the machine or isa number
 613      so we leave it to the target.  */
 614 #ifdef CGEN_COMPUTE_MACH
 615   mach = CGEN_COMPUTE_MACH (info);
 616 #else
 617   mach = info->mach;
 618 #endif
 619
 620 #ifdef CGEN_COMPUTE_ISA
 621   {
 622     static CGEN_BITSET *permanent_isa;
 623
 624     if (!permanent_isa)
 625       permanent_isa = cgen_bitset_create (MAX_ISAS);
 626     isa = permanent_isa;
 627     cgen_bitset_clear (isa);
 628     cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info));
 629   }
 630 #else
 631   isa = info->insn_sets;
 632 #endif
 633
 634   /* If we've switched cpu's, try to find a handle we've used before */
 635   if (cd
 636       && (cgen_bitset_compare (isa, prev_isa) != 0
 637           || mach != prev_mach
 638           || endian != prev_endian))
 639     {
 640       cd = 0;
 641       for (cl = cd_list; cl; cl = cl->next)
 642         {
 643           if (cgen_bitset_compare (cl->isa, isa) == 0 &&
 644               cl->mach == mach &&
 645               cl->endian == endian)
 646             {
 647               cd = cl->cd;
 648               prev_isa = cd->isas;
 649               break;
 650             }
 651         }
 652     }
 653
 654   /* If we haven't initialized yet, initialize the opcode table.  */
 655   if (! cd)
 656     {
 657       const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach);
 658       const char *mach_name;
 659
 660       if (!arch_type)
 661         abort ();
 662       mach_name = arch_type->printable_name;
 663
 664       prev_isa = cgen_bitset_copy (isa);
 665       prev_mach = mach;
 666       prev_endian = endian;
 667       cd = m32r_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa,
 668                                  CGEN_CPU_OPEN_BFDMACH, mach_name,
 669                                  CGEN_CPU_OPEN_ENDIAN, prev_endian,
 670                                  CGEN_CPU_OPEN_END);
 671       if (!cd)
 672         abort ();
 673
 674       /* Save this away for future reference.  */
 675       cl = xmalloc (sizeof (struct cpu_desc_list));
 676       cl->cd = cd;
 677       cl->isa = prev_isa;
 678       cl->mach = mach;
 679       cl->endian = endian;
 680       cl->next = cd_list;
 681       cd_list = cl;
 682
 683       m32r_cgen_init_dis (cd);
 684     }
 685
 686   /* We try to have as much common code as possible.
 687      But at this point some targets need to take over.  */
 688   /* ??? Some targets may need a hook elsewhere.  Try to avoid this,
 689      but if not possible try to move this hook elsewhere rather than
 690      have two hooks.  */
 691   length = CGEN_PRINT_INSN (cd, pc, info);
 692   if (length > 0)
 693     return length;
 694   if (length < 0)
 695     return -1;
 696
 697   (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG);
 698   return cd->default_insn_bitsize / 8;
 699 }