| blob | 6376cf8d0699b7e49323c941a0d422b37e7b646c |
1 /* Target-dependent code for the IA-64 for GDB, the GNU debugger.
3 Copyright (C) 1999-2024 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
42 #ifdef HAVE_LIBUNWIND_IA64_H
46 /* Note: KERNEL_START is supposed to be an address which is not going
47 to ever contain any valid unwind info. For ia64 linux, the choice
48 of 0xc000000000000000 is fairly safe since that's uncached space.
50 We use KERNEL_START as follows: after obtaining the kernel's
51 unwind table via getunwind(), we project its unwind data into
52 address-range KERNEL_START-(KERNEL_START+ktab_size) and then
53 when ia64_access_mem() sees a memory access to this
54 address-range, we redirect it to ktab instead.
56 None of this hackery is needed with a modern kernel/libcs
57 which uses the kernel virtual DSO to provide access to the
58 kernel's unwind info. In that case, ktab_size remains 0 and
59 hence the value of KERNEL_START doesn't matter. */
61 #define KERNEL_START 0xc000000000000000ULL
64 struct ia64_table_entry
65 {
69 };
74 #endif
76 /* An enumeration of the different IA-64 instruction types. */
78 enum ia64_instruction_type
79 {
87 undefined /* undefined or reserved */
88 };
90 /* We represent IA-64 PC addresses as the value of the instruction
91 pointer or'd with some bit combination in the low nibble which
92 represents the slot number in the bundle addressed by the
93 instruction pointer. The problem is that the Linux kernel
94 multiplies its slot numbers (for exceptions) by one while the
95 disassembler multiplies its slot numbers by 6. In addition, I've
96 heard it said that the simulator uses 1 as the multiplier.
98 I've fixed the disassembler so that the bytes_per_line field will
99 be the slot multiplier. If bytes_per_line comes in as zero, it
100 is set to six (which is how it was set up initially). -- objdump
101 displays pretty disassembly dumps with this value. For our purposes,
102 we'll set bytes_per_line to SLOT_MULTIPLIER. This is okay since we
103 never want to also display the raw bytes the way objdump does. */
105 #define SLOT_MULTIPLIER 1
107 /* Length in bytes of an instruction bundle. */
109 #define BUNDLE_LEN 16
111 /* See the saved memory layout comment for ia64_memory_insert_breakpoint. */
113 #if BREAKPOINT_MAX < BUNDLE_LEN - 2
115 #endif
125 CORE_ADDR faddr);
127 #define NUM_IA64_RAW_REGS 462
129 /* Big enough to hold a FP register in bytes. */
130 #define IA64_FP_REGISTER_SIZE 16
134 /* NOTE: we treat the register stack registers r32-r127 as
135 pseudo-registers because they may not be accessible via the ptrace
136 register get/set interfaces. */
144 /* Array of register names; There should be ia64_num_regs strings in
145 the initializer. */
254 };
256 struct ia64_frame_cache
257 {
268 cfm value). */
269 CORE_ADDR after_prologue;
270 /* Address of first instruction after the last
271 prologue instruction; Note that there may
272 be instructions from the function's body
273 intermingled with the prologue. */
275 /* Size of the memory stack frame (may be zero),
276 or -1 if it has not been determined yet. */
278 for this frame. 0 if no register is being used
279 as the frame pointer. */
281 /* Saved registers. */
284 };
286 static int
288 {
290 }
293 {
296 };
299 {
302 };
305 {
307 &floatformat_ia64_ext_little
308 };
312 {
316 {
318 tdep->ia64_ext_type
320 floatformats_ia64_ext);
321 }
324 }
326 static int
329 {
347 }
351 {
353 }
357 {
360 else
362 }
364 static int
366 {
370 }
373 /* Extract ``len'' bits from an instruction bundle starting at
374 bit ``from''. */
376 static long long
378 {
395 {
398 }
401 {
405 }
408 }
410 /* Replace the specified bits in an instruction bundle. */
412 static void
414 {
422 {
431 }
432 else
433 {
442 {
446 }
449 {
455 }
456 }
457 }
459 /* Return the contents of slot N (for N = 0, 1, or 2) in
460 and instruction bundle. */
462 static long long
464 {
466 }
468 /* Store an instruction in an instruction bundle. */
470 static void
472 {
474 }
477 {
510 };
512 /* Fetch and (partially) decode an instruction at ADDR and return the
513 address of the next instruction to fetch. */
515 static CORE_ADDR
517 {
523 /* Warn about slot numbers greater than 2. We used to generate
524 an error here on the assumption that the user entered an invalid
525 address. But, sometimes GDB itself requests an invalid address.
526 This can (easily) happen when execution stops in a function for
527 which there are no symbols. The prologue scanner will attempt to
528 find the beginning of the function - if the nearest symbol
529 happens to not be aligned on a bundle boundary (16 bytes), the
530 resulting starting address will cause GDB to think that the slot
531 number is too large.
533 So we warn about it and set the slot number to zero. It is
534 not necessarily a fatal condition, particularly if debugging
535 at the assembly language level. */
537 {
541 }
556 else
560 }
562 /* There are 5 different break instructions (break.i, break.b,
563 break.m, break.f, and break.x), but they all have the same
564 encoding. (The five bit template in the low five bits of the
565 instruction bundle distinguishes one from another.)
567 The runtime architecture manual specifies that break instructions
568 used for debugging purposes must have the upper two bits of the 21
569 bit immediate set to a 0 and a 1 respectively. A breakpoint
570 instruction encodes the most significant bit of its 21 bit
571 immediate at bit 36 of the 41 bit instruction. The penultimate msb
572 is at bit 25 which leads to the pattern below.
574 Originally, I had this set up to do, e.g, a "break.i 0x80000" But
575 it turns out that 0x80000 was used as the syscall break in the early
576 simulators. So I changed the pattern slightly to do "break.i 0x080001"
577 instead. But that didn't work either (I later found out that this
578 pattern was used by the simulator that I was using.) So I ended up
579 using the pattern seen below.
581 SHADOW_CONTENTS has byte-based addressing (PLACED_ADDRESS and SHADOW_LEN)
582 while we need bit-based addressing as the instructions length is 41 bits and
583 we must not modify/corrupt the adjacent slots in the same bundle.
584 Fortunately we may store larger memory incl. the adjacent bits with the
585 original memory content (not the possibly already stored breakpoints there).
586 We need to be careful in ia64_memory_remove_breakpoint to always restore
587 only the specific bits of this instruction ignoring any adjacent stored
588 bits.
590 We use the original addressing with the low nibble in the range <0..2> which
591 gets incorrectly interpreted by generic non-ia64 breakpoint_restore_shadows
592 as the direct byte offset of SHADOW_CONTENTS. We store whole BUNDLE_LEN
593 bytes just without these two possibly skipped bytes to not to exceed to the
594 next bundle.
596 If we would like to store the whole bundle to SHADOW_CONTENTS we would have
597 to store already the base address (`address & ~0x0f') into PLACED_ADDRESS.
598 In such case there is no other place where to store
599 SLOTNUM (`adress & 0x0f', value in the range <0..2>). We need to know
600 SLOTNUM in ia64_memory_remove_breakpoint.
602 There is one special case where we need to be extra careful:
603 L-X instructions, which are instructions that occupy 2 slots
604 (The L part is always in slot 1, and the X part is always in
605 slot 2). We must refuse to insert breakpoints for an address
606 that points at slot 2 of a bundle where an L-X instruction is
607 present, since there is logically no instruction at that address.
608 However, to make things more interesting, the opcode of L-X
609 instructions is located in slot 2. This means that, to insert
610 a breakpoint at an address that points to slot 1, we actually
611 need to write the breakpoint in slot 2! Slot 1 is actually
612 the extended operand, so writing the breakpoint there would not
613 have the desired effect. Another side-effect of this issue
614 is that we need to make sure that the shadow contents buffer
615 does save byte 15 of our instruction bundle (this is the tail
616 end of slot 2, which wouldn't be saved if we were to insert
617 the breakpoint in slot 1).
619 ia64 16-byte bundle layout:
620 | 5 bits | slot 0 with 41 bits | slot 1 with 41 bits | slot 2 with 41 bits |
622 The current addressing used by the code below:
623 original PC placed_address placed_size required covered
624 == bp_tgt->shadow_len reqd \subset covered
625 0xABCDE0 0xABCDE0 0x10 <0x0...0x5> <0x0..0xF>
626 0xABCDE1 0xABCDE1 0xF <0x5...0xA> <0x1..0xF>
627 0xABCDE2 0xABCDE2 0xE <0xA...0xF> <0x2..0xF>
629 L-X instructions are treated a little specially, as explained above:
630 0xABCDE1 0xABCDE1 0xF <0xA...0xF> <0x1..0xF>
632 `objdump -d' and some other tools show a bit unjustified offsets:
633 original PC byte where starts the instruction objdump offset
634 0xABCDE0 0xABCDE0 0xABCDE0
635 0xABCDE1 0xABCDE5 0xABCDE6
636 0xABCDE2 0xABCDEA 0xABCDEC
637 */
639 #define IA64_BREAKPOINT 0x00003333300LL
641 static int
644 {
657 /* Enable the automatic memory restoration from breakpoints while
658 we read our instruction bundle for the purpose of SHADOW_CONTENTS.
659 Otherwise, we could possibly store into the shadow parts of the adjacent
660 placed breakpoints. It is due to our SHADOW_CONTENTS overlapping the real
661 breakpoint instruction bits region. */
662 scoped_restore restore_memory_0
668 /* SHADOW_SLOTNUM saves the original slot number as expected by the caller
669 for addressing the SHADOW_CONTENTS placement. */
672 /* Always cover the last byte of the bundle in case we are inserting
673 a breakpoint on an L-X instruction. */
678 {
679 /* X unit types can only be used in slot 2, and are actually
680 part of a 2-slot L-X instruction. We cannot break at this
681 address, as this is the second half of an instruction that
682 lives in slot 1 of that bundle. */
685 }
687 {
688 /* L unit types can only be used in slot 1. But the associated
689 opcode for that instruction is in slot 2, so bump the slot number
690 accordingly. */
693 }
695 /* Store the whole bundle, except for the initial skipped bytes by the slot
696 number interpreted as bytes offset in PLACED_ADDRESS. */
700 /* Re-read the same bundle as above except that, this time, read it in order
701 to compute the new bundle inside which we will be inserting the
702 breakpoint. Therefore, disable the automatic memory restoration from
703 breakpoints while we read our instruction bundle. Otherwise, the general
704 restoration mechanism kicks in and we would possibly remove parts of the
705 adjacent placed breakpoints. It is due to our SHADOW_CONTENTS overlapping
706 the real breakpoint instruction bits region. */
707 scoped_restore restore_memory_1
713 /* Breakpoints already present in the code will get detected and not get
714 reinserted by bp_loc_is_permanent. Multiple breakpoints at the same
715 location cannot induce the internal error as they are optimized into
716 a single instance by update_global_location_list. */
727 }
729 static int
732 {
742 /* Disable the automatic memory restoration from breakpoints while
743 we read our instruction bundle. Otherwise, the general restoration
744 mechanism kicks in and we would possibly remove parts of the adjacent
745 placed breakpoints. It is due to our SHADOW_CONTENTS overlapping the real
746 breakpoint instruction bits region. */
747 scoped_restore restore_memory_1
753 /* SHADOW_SLOTNUM saves the original slot number as expected by the caller
754 for addressing the SHADOW_CONTENTS placement. */
759 {
760 /* X unit types can only be used in slot 2, and are actually
761 part of a 2-slot L-X instruction. We refuse to insert
762 breakpoints at this address, so there should be no reason
763 for us attempting to remove one there, except if the program's
764 code somehow got modified in memory. */
770 }
772 {
773 /* L unit types can only be used in slot 1. But the breakpoint
774 was actually saved using slot 2, so update the slot number
775 accordingly. */
778 }
784 {
789 }
791 /* Extract the original saved instruction from SLOTNUM normalizing its
792 bit-shift for INSTR_SAVED. */
798 /* In BUNDLE_MEM, be careful to modify only the bits belonging to SLOTNUM
799 and not any of the other ones that are stored in SHADOW_CONTENTS. */
804 }
806 /* Implement the breakpoint_kind_from_pc gdbarch method. */
808 static int
810 {
811 /* A place holder of gdbarch method breakpoint_kind_from_pc. */
813 }
815 /* As gdbarch_breakpoint_from_pc ranges have byte granularity and ia64
816 instruction slots ranges are bit-granular (41 bits) we have to provide an
817 extended range as described for ia64_memory_insert_breakpoint. We also take
818 care of preserving the `break' instruction 21-bit (or 62-bit) parameter to
819 make a match for permanent breakpoints. */
824 {
837 /* Enable the automatic memory restoration from breakpoints while
838 we read our instruction bundle to match bp_loc_is_permanent. */
839 {
840 scoped_restore restore_memory_0
843 }
845 /* The memory might be unreachable. This can happen, for instance,
846 when the user inserts a breakpoint at an invalid address. */
850 /* SHADOW_SLOTNUM saves the original slot number as expected by the caller
851 for addressing the SHADOW_CONTENTS placement. */
854 /* Cover always the last byte of the bundle for the L-X slot case. */
857 /* Check for L type instruction in slot 1, if present then bump up the slot
858 number to the slot 2. */
861 {
864 }
866 {
869 }
871 /* A break instruction has its all its opcode bits cleared except for
872 the parameter value. For L+X slot pair we are at the X slot (slot 2) so
873 we should not touch the L slot - the upper 41 bits of the parameter. */
879 }
881 static CORE_ADDR
883 {
892 }
894 void
896 {
898 ULONGEST psr_value;
908 }
910 #define IS_NaT_COLLECTION_ADDR(addr) ((((addr) >> 3) & 0x3f) == 0x3f)
912 /* Returns the address of the slot that's NSLOTS slots away from
913 the address ADDR. NSLOTS may be positive or negative. */
914 static CORE_ADDR
916 {
917 CORE_ADDR new_addr;
930 }
932 static enum register_status
935 {
940 {
941 #ifdef HAVE_LIBUNWIND_IA64_H
942 /* First try and use the libunwind special reg accessor,
943 otherwise fallback to standard logic. */
946 #endif
947 {
948 /* The fallback position is to assume that r32-r127 are
949 found sequentially in memory starting at $bof. This
950 isn't always true, but without libunwind, this is the
951 best we can do. */
952 ULONGEST cfm;
953 ULONGEST bsp;
954 CORE_ADDR reg;
964 /* The bsp points at the end of the register frame so we
965 subtract the size of frame from it to get start of
966 register frame. */
970 {
975 }
976 else
979 }
980 }
982 {
983 ULONGEST unatN_val;
984 ULONGEST unat;
992 }
994 {
996 ULONGEST bsp;
997 ULONGEST cfm;
1008 /* The bsp points at the end of the register frame so we
1009 subtract the size of frame from it to get start of register frame. */
1016 {
1017 /* Compute address of nat collection bits. */
1019 ULONGEST nat_collection;
1021 /* If our nat collection address is bigger than bsp, we have to get
1022 the nat collection from rnat. Otherwise, we fetch the nat
1023 collection from the computed address. */
1026 else
1030 }
1034 }
1036 {
1037 /* A virtual register frame start is provided for user convenience.
1038 It can be calculated as the bsp - sof (sizeof frame). */
1040 ULONGEST cfm;
1049 /* The bsp points at the end of the register frame so we
1050 subtract the size of frame from it to get beginning of frame. */
1054 }
1056 {
1057 ULONGEST pr;
1058 ULONGEST cfm;
1059 ULONGEST prN_val;
1069 {
1070 /* Fetch predicate register rename base from current frame
1071 marker for this frame. */
1074 /* Adjust the register number to account for register rotation. */
1075 regnum = VP16_REGNUM
1077 }
1081 }
1082 else
1086 }
1088 static void
1091 {
1095 {
1096 ULONGEST bsp;
1097 ULONGEST cfm;
1104 {
1107 }
1108 }
1110 {
1114 regnum),
1115 byte_order);
1122 }
1124 {
1125 ULONGEST natN_val;
1126 ULONGEST bsp;
1127 ULONGEST cfm;
1132 /* The bsp points at the end of the register frame so we
1133 subtract the size of frame from it to get start of register frame. */
1140 regnum),
1141 byte_order);
1144 {
1145 /* Compute address of nat collection bits. */
1147 CORE_ADDR nat_collection;
1150 /* If our nat collection address is bigger than bsp, we have to get
1151 the nat collection from rnat. Otherwise, we fetch the nat
1152 collection from the computed address. */
1154 {
1156 IA64_RNAT_REGNUM,
1160 else
1163 nat_collection);
1164 }
1165 else
1166 {
1171 else
1176 }
1177 }
1178 }
1180 {
1181 ULONGEST pr;
1182 ULONGEST cfm;
1183 ULONGEST prN_val;
1184 ULONGEST prN_mask;
1190 {
1191 /* Fetch predicate register rename base from current frame
1192 marker for this frame. */
1195 /* Adjust the register number to account for register rotation. */
1196 regnum = VP16_REGNUM
1198 }
1200 byte_order);
1207 }
1208 }
1210 /* The ia64 needs to convert between various ieee floating-point formats
1211 and the special ia64 floating point register format. */
1213 static int
1215 {
1219 }
1221 static int
1225 {
1229 /* Convert to TYPE. */
1233 unavailablep))
1239 }
1241 static void
1244 {
1251 }
1254 /* Limit the number of skipped non-prologue instructions since examining
1255 of the prologue is expensive. */
1258 /* Given PC representing the starting address of a function, and
1259 LIM_PC which is the (sloppy) limit to which to scan when looking
1260 for a prologue, attempt to further refine this limit by using
1261 the line data in the symbol table. If successful, a better guess
1262 on where the prologue ends is returned, otherwise the previous
1263 value of lim_pc is returned. TRUST_LIMIT is a pointer to a flag
1264 which will be set to indicate whether the returned limit may be
1265 used with no further scanning in the event that the function is
1266 frameless. */
1268 /* FIXME: cagney/2004-02-14: This function and logic have largely been
1269 superseded by skip_prologue_using_sal. */
1271 static CORE_ADDR
1273 {
1276 CORE_ADDR end_pc;
1278 /* The prologue can not possibly go past the function end itself,
1279 so we can already adjust LIM_PC accordingly. */
1283 /* Start off not trusting the limit. */
1288 {
1292 /* Handle the case in which compiler's optimizer/scheduler
1293 has moved instructions into the prologue. We scan ahead
1294 in the function looking for address ranges whose corresponding
1295 line number is less than or equal to the first one that we
1296 found for the function. (It can be less than when the
1297 scheduler puts a body instruction before the first prologue
1298 instruction.) */
1301 i--)
1302 {
1310 {
1312 }
1314 }
1317 {
1321 }
1322 }
1324 }
1326 #define isScratch(_regnum_) ((_regnum_) == 2 || (_regnum_) == 3 \
1327 || (8 <= (_regnum_) && (_regnum_) <= 11) \
1328 || (14 <= (_regnum_) && (_regnum_) <= 31))
1329 #define imm9(_instr_) \
1330 ( ((((_instr_) & 0x01000000000LL) ? -1 : 0) << 8) \
1331 | (((_instr_) & 0x00008000000LL) >> 20) \
1332 | (((_instr_) & 0x00000001fc0LL) >> 6))
1334 /* Allocate and initialize a frame cache. */
1338 {
1344 /* Base address. */
1360 }
1362 static CORE_ADDR
1366 {
1367 CORE_ADDR next_pc;
1369 ia64_instruction_type it;
1385 CORE_ADDR addr;
1400 /* We want to check if we have a recognizable function start before we
1401 look ahead for a prologue. */
1404 {
1405 /* alloc - start of a regular function. */
1410 /* Verify that the current cfm matches what we think is the
1411 function start. If we have somehow jumped within a function,
1412 we do not want to interpret the prologue and calculate the
1413 addresses of various registers such as the return address.
1414 We will instead treat the frame as frameless. */
1423 }
1424 else
1425 {
1426 /* Look for a leaf routine. */
1430 {
1431 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1439 {
1440 /* mov r2, r12 - beginning of leaf routine. */
1443 }
1444 }
1446 /* If we don't recognize a regular function or leaf routine, we are
1447 done. */
1449 {
1453 }
1454 }
1456 /* Loop, looking for prologue instructions, keeping track of
1457 where preserved registers were spilled. */
1459 {
1465 {
1466 /* Exit loop upon hitting a non-nop branch instruction. */
1470 }
1473 {
1474 /* Exit loop upon hitting a predicated instruction if
1475 we already have the return register or if we are frameless. */
1479 }
1481 {
1482 /* Move from BR */
1488 {
1491 }
1492 }
1495 {
1496 /* adds rN = imm14, rM (or mov rN, rM when imm14 is 0) */
1505 {
1506 /* mov rN, r12 */
1509 }
1511 {
1512 /* adds r12, -mem_stack_frame_size, r12 */
1515 }
1518 {
1520 /* adds r2, spilloffset, rFramePointer
1521 or
1522 adds r2, spilloffset, r12
1524 Get ready for stf.spill or st8.spill instructions.
1525 The address to start spilling at is loaded into r2.
1526 FIXME: Why r2? That's what gcc currently uses; it
1527 could well be different for other compilers. */
1529 /* Hmm... whether or not this will work will depend on
1530 where the pc is. If it's still early in the prologue
1531 this'll be wrong. FIXME */
1534 sp_regnum);
1535 spill_addr = saved_sp
1540 }
1543 {
1544 /* mov rN, rM where rM is an input register. */
1547 }
1550 {
1551 /* mov r12, r2 */
1554 }
1555 }
1559 {
1560 /* stf.spill [rN] = fM, imm9
1561 or
1562 stf.spill [rN] = fM */
1570 {
1575 else
1578 }
1579 }
1582 {
1583 /* mov.m rN = arM
1584 or
1585 mov.i rN = arM */
1591 {
1592 /* We have something like "mov.m r3 = ar.unat". Remember the
1593 r3 (or whatever) and watch for a store of this register... */
1596 }
1597 }
1599 {
1600 /* mov rN = pr */
1604 {
1607 }
1608 }
1612 {
1613 /* st8 [rN] = rM
1614 or
1615 st8 [rN] = rM, imm9 */
1622 {
1623 /* We've found a spill of either the UNAT register or the PR
1624 register. (Well, not exactly; what we've actually found is
1625 a spill of the register that UNAT or PR was moved to).
1626 Record that fact and move on... */
1628 {
1629 /* Track UNAT register. */
1632 }
1633 else
1634 {
1635 /* Track PR register. */
1638 }
1640 /* st8 [rN] = rM, imm9 */
1642 else
1645 }
1647 {
1648 /* Allow up to one store of each input register. */
1651 }
1654 {
1655 /* Allow an indirect store of an input register. */
1658 }
1659 }
1661 {
1662 /* One of
1663 st1 [rN] = rM
1664 st2 [rN] = rM
1665 st4 [rN] = rM
1666 st8 [rN] = rM
1667 Note that the st8 case is handled in the clause above.
1669 Advance over stores of input registers. One store per input
1670 register is permitted. */
1675 {
1678 }
1681 {
1682 /* Allow an indirect store of an input register. */
1685 }
1686 }
1688 {
1689 /* Either
1690 stfs [rN] = fM
1691 or
1692 stfd [rN] = fM
1694 Advance over stores of floating point input registers. Again
1695 one store per register is permitted. */
1699 {
1702 }
1703 }
1707 {
1708 /* st8.spill [rN] = rM
1709 or
1710 st8.spill [rN] = rM, imm9 */
1715 {
1716 /* We've found a spill of one of the preserved general purpose
1717 regs. Record the spill address and advance the spill
1718 register if appropriate. */
1721 /* st8.spill [rN] = rM, imm9 */
1723 else
1726 }
1727 }
1730 }
1732 /* If not frameless and we aren't called by skip_prologue, then we need
1733 to calculate registers for the previous frame which will be needed
1734 later. */
1737 {
1741 /* Extract the size of the rotating portion of the stack
1742 frame and the register rename base from the current
1743 frame marker. */
1750 /* Find the bof (beginning of frame). */
1756 {
1758 {
1760 }
1767 }
1769 /* For the previous argument registers we require the previous bof.
1770 If we can't find the previous cfm, then we can do nothing. */
1773 {
1776 }
1778 {
1781 }
1785 {
1791 /* The previous bof only requires subtraction of the sol (size of
1792 locals) due to the overlap between output and input of
1793 subsequent frames. */
1799 {
1801 {
1803 }
1808 else
1810 }
1812 }
1813 }
1815 /* Try and trust the lim_pc value whenever possible. */
1825 }
1827 CORE_ADDR
1829 {
1836 /* Call examine_prologue with - as third argument since we don't
1837 have a next frame pointer to send. */
1839 }
1842 /* Normal frames. */
1846 {
1851 CORE_ADDR cfm;
1862 /* We always want the bsp to point to the end of frame.
1863 This way, we can always get the beginning of frame (bof)
1864 by subtracting frame size. */
1887 }
1889 static void
1892 {
1897 /* If outermost frame, mark with null frame id. */
1902 "regular frame id: code %s, stack %s, "
1908 }
1913 {
1928 {
1932 /* We want to calculate the previous bsp as the end of the previous
1933 register stack frame. This corresponds to what the hardware bsp
1934 register will be if we pop the frame back which is why we might
1935 have been called. We know the beginning of the current frame is
1936 cache->bsp - cache->sof. This value in the previous frame points
1937 to the start of the output registers. We can calculate the end of
1938 that frame by adding the size of output:
1939 (sof (size of frame) - sol (size of locals)). */
1944 prev_bsp =
1948 }
1951 {
1962 IA64_PFS_REGNUM);
1964 }
1967 {
1968 /* If the function in question uses an automatic register (r32-r127)
1969 for the frame pointer, it'll be found by ia64_find_saved_register()
1970 above. If the function lacks one of these frame pointers, we can
1971 still provide a value since we know the size of the frame. */
1973 }
1976 {
1978 ULONGEST prN;
1981 IA64_PR_REGNUM);
1983 {
1984 /* Fetch predicate register rename base from current frame
1985 marker for this frame. */
1988 /* Adjust the register number to account for register rotation. */
1990 }
1994 }
1997 {
1999 ULONGEST unatN;
2001 IA64_UNAT_REGNUM);
2005 }
2008 {
2010 /* Find address of general register corresponding to nat bit we're
2011 interested in. */
2012 CORE_ADDR gr_addr;
2017 {
2018 /* Compute address of nat collection bits. */
2020 CORE_ADDR bsp;
2021 CORE_ADDR nat_collection;
2024 /* If our nat collection address is bigger than bsp, we have to get
2025 the nat collection from rnat. Otherwise, we fetch the nat
2026 collection from the computed address. */
2030 {
2033 }
2034 else
2038 }
2041 }
2044 {
2049 {
2052 }
2054 {
2057 }
2060 }
2063 {
2064 /* We don't know how to get the complete previous PSR, but we need it
2065 for the slot information when we unwind the pc (pc is formed of IP
2066 register plus slot information from PSR). To get the previous
2067 slot information, we mask it off the return address. */
2077 {
2080 }
2082 {
2085 }
2090 }
2093 {
2100 }
2104 {
2114 {
2118 /* FIXME: brobecker/2008-05-01: Doesn't this seem redundant
2119 with the same code above? */
2123 IA64_CFM_REGNUM);
2124 prev_cfm = extract_unsigned_integer
2127 IA64_BSP_REGNUM);
2128 prev_bsp = extract_unsigned_integer
2134 }
2137 }
2140 {
2144 {
2145 /* Fetch floating point register rename base from current
2146 frame marker for this frame. */
2149 /* Adjust the floating point register number to account for
2150 register rotation. */
2151 regnum = IA64_FR32_REGNUM
2153 }
2155 /* If we have stored a memory address, access the register. */
2159 /* Otherwise, punt and get the current value of the register. */
2160 else
2162 }
2163 }
2166 {
2168 NORMAL_FRAME,
2169 default_frame_unwind_stop_reason,
2172 NULL,
2173 default_frame_sniffer
2174 };
2176 /* Signal trampolines. */
2178 static void
2181 {
2186 {
2191 IA64_IP_REGNUM);
2194 IA64_CFM_REGNUM);
2197 IA64_PSR_REGNUM);
2200 IA64_BSP_REGNUM);
2203 IA64_RNAT_REGNUM);
2206 IA64_CCV_REGNUM);
2209 IA64_UNAT_REGNUM);
2212 IA64_FPSR_REGNUM);
2215 IA64_PFS_REGNUM);
2218 IA64_LC_REGNUM);
2229 }
2230 }
2234 {
2246 /* Note that frame size is hard-coded below. We cannot calculate it
2247 via prologue examination. */
2261 }
2263 static void
2266 {
2276 "sigtramp frame id: code %s, stack %s, "
2282 }
2287 {
2297 {
2302 {
2306 }
2309 }
2313 {
2323 }
2326 {
2333 }
2334 }
2336 static int
2340 {
2344 {
2349 }
2352 }
2355 {
2357 SIGTRAMP_FRAME,
2358 default_frame_unwind_stop_reason,
2359 ia64_sigtramp_frame_this_id,
2360 ia64_sigtramp_frame_prev_register,
2361 NULL,
2362 ia64_sigtramp_frame_sniffer
2363 };
2365 \f
2367 static CORE_ADDR
2369 {
2373 }
2376 {
2378 ia64_frame_base_address,
2379 ia64_frame_base_address,
2380 ia64_frame_base_address
2381 };
2383 #ifdef HAVE_LIBUNWIND_IA64_H
2385 struct ia64_unwind_table_entry
2386 {
2387 unw_word_t start_offset;
2388 unw_word_t end_offset;
2389 unw_word_t info_offset;
2390 };
2394 {
2396 }
2398 /* Skip over a designated number of registers in the backing
2399 store, remembering every 64th position is for NAT. */
2402 {
2408 }
2410 /* Gdb ia64-libunwind-tdep callback function to convert from an ia64 gdb
2411 register number to a libunwind register number. */
2412 static int
2414 {
2439 else
2441 }
2443 /* Gdb ia64-libunwind-tdep callback function to convert from a libunwind
2444 register number to a ia64 gdb register number. */
2445 static int
2447 {
2470 else
2472 }
2474 /* Gdb ia64-libunwind-tdep callback function to reveal if register is
2475 a float register or not. */
2476 static int
2478 {
2480 }
2482 /* Libunwind callback accessor function for general registers. */
2483 static int
2486 {
2493 /* We never call any libunwind routines that need to write registers. */
2497 {
2499 /* Libunwind expects to see the pc value which means the slot number
2500 from the psr must be merged with the ip word address. */
2507 /* Libunwind expects to see the beginning of the current
2508 register frame so we must account for the fact that
2509 ptrace() will return a value for bsp that points *after*
2510 the current register frame. */
2518 /* Libunwind wants bspstore to be after the current register frame.
2519 This is what ptrace() and gdb treats as the regular bsp value. */
2524 /* For all other registers, just unwind the value directly. */
2527 }
2536 }
2538 /* Libunwind callback accessor function for floating-point registers. */
2539 static int
2542 {
2546 /* We never call any libunwind routines that need to write registers. */
2552 }
2554 /* Libunwind callback accessor function for top-level rse registers. */
2555 static int
2558 {
2564 /* We never call any libunwind routines that need to write registers. */
2568 {
2570 /* Libunwind expects to see the pc value which means the slot number
2571 from the psr must be merged with the ip word address. */
2578 /* Libunwind expects to see the beginning of the current
2579 register frame so we must account for the fact that
2580 ptrace() will return a value for bsp that points *after*
2581 the current register frame. */
2589 /* Libunwind wants bspstore to be after the current register frame.
2590 This is what ptrace() and gdb treats as the regular bsp value. */
2595 /* For all other registers, just unwind the value directly. */
2598 }
2608 }
2610 /* Libunwind callback accessor function for top-level fp registers. */
2611 static int
2614 {
2618 /* We never call any libunwind routines that need to write registers. */
2624 }
2626 /* Libunwind callback accessor function for accessing memory. */
2627 static int
2631 {
2633 {
2639 else
2642 }
2644 /* XXX do we need to normalize byte-order here? */
2647 else
2649 }
2651 /* Call low-level function to access the kernel unwind table. */
2654 {
2655 /* FIXME drow/2005-09-10: This code used to call
2656 ia64_linux_xfer_unwind_table directly to fetch the unwind table
2657 for the currently running ia64-linux kernel. That data should
2658 come from the core file and be accessed via the auxv vector; if
2659 we want to preserve fall back to the running kernel's table, then
2660 we should find a way to override the corefile layer's
2661 xfer_partial method. */
2665 }
2667 /* Get the kernel unwind table. */
2668 static int
2670 {
2674 {
2684 }
2706 }
2708 /* Find the unwind table entry for a specified address. */
2709 static int
2712 {
2716 CORE_ADDR load_base;
2728 {
2730 {
2743 }
2744 }
2749 /* Verify that the segment that contains the IP also contains
2750 the static unwind table. If not, we may be in the Linux kernel's
2751 DSO gate page in which case the unwind table is another segment.
2752 Otherwise, we are dealing with runtime-generated code, for which we
2753 have no info here. */
2757 {
2760 {
2763 {
2765 /* Get the segbase from the section containing the
2766 libunwind table. */
2768 }
2769 }
2772 }
2784 }
2786 /* Libunwind callback accessor function to acquire procedure unwind-info. */
2787 static int
2790 {
2792 unw_dyn_info_t di;
2797 {
2798 /* XXX This only works if the host and the target architecture are
2799 both ia64 and if the have (more or less) the same kernel
2800 version. */
2806 "(name=`%s',segbase=%s,start=%s,end=%s,gp=%s,"
2814 }
2815 else
2816 {
2823 "(name=`%s',segbase=%s,start=%s,end=%s,gp=%s,"
2831 }
2834 arg);
2836 /* We no longer need the dyn info storage so free it. */
2840 }
2842 /* Libunwind callback accessor function for cleanup. */
2843 static void
2846 {
2847 /* Nothing required for now. */
2848 }
2850 /* Libunwind callback accessor function to get head of the dynamic
2851 unwind-info registration list. */
2852 static int
2855 {
2858 unw_dyn_info_t di;
2865 {
2872 {
2874 /* We no longer need the dyn info storage so free it. */
2878 {
2881 "dynamic unwind table in objfile %s "
2887 }
2888 }
2889 }
2891 }
2894 /* Frame interface functions for libunwind. */
2896 static void
2899 {
2904 CORE_ADDR bsp;
2908 {
2911 }
2913 /* We must add the bsp as the special address for frame comparison
2914 purposes. */
2922 "libunwind frame id: code %s, stack %s, "
2928 }
2933 {
2944 /* Let libunwind do most of the work. */
2948 {
2949 ULONGEST prN_val;
2952 {
2954 ULONGEST cfm;
2956 /* Fetch predicate register rename base from current frame
2957 marker for this frame. */
2961 /* Adjust the register number to account for register rotation. */
2963 }
2967 }
2970 {
2971 ULONGEST unatN_val;
2976 }
2979 {
2983 /* We want to calculate the previous bsp as the end of the previous
2984 register stack frame. This corresponds to what the hardware bsp
2985 register will be if we pop the frame back which is why we might
2986 have been called. We know that libunwind will pass us back the
2987 beginning of the current frame so we should just add sof to it. */
2991 IA64_CFM_REGNUM);
2997 }
2998 else
3000 }
3002 static int
3006 {
3012 }
3015 {
3017 NORMAL_FRAME,
3018 default_frame_unwind_stop_reason,
3019 ia64_libunwind_frame_this_id,
3020 ia64_libunwind_frame_prev_register,
3021 NULL,
3022 ia64_libunwind_frame_sniffer,
3023 libunwind_frame_dealloc_cache
3024 };
3026 static void
3030 {
3034 CORE_ADDR bsp;
3039 {
3042 }
3044 /* We must add the bsp as the special address for frame comparison
3045 purposes. */
3049 /* For a sigtramp frame, we don't make the check for previous ip being 0. */
3054 "libunwind sigtramp frame id: code %s, "
3060 }
3065 {
3069 CORE_ADDR prev_ip;
3071 /* If the previous frame pc value is 0, then we want to use the SIGCONTEXT
3072 method of getting previous registers. */
3074 IA64_IP_REGNUM);
3079 {
3082 regnum);
3083 }
3084 else
3086 }
3088 static int
3092 {
3094 {
3098 }
3099 else
3101 }
3104 {
3106 SIGTRAMP_FRAME,
3107 default_frame_unwind_stop_reason,
3108 ia64_libunwind_sigtramp_frame_this_id,
3109 ia64_libunwind_sigtramp_frame_prev_register,
3110 NULL,
3111 ia64_libunwind_sigtramp_frame_sniffer
3112 };
3114 /* Set of libunwind callback acccessor functions. */
3115 unw_accessors_t ia64_unw_accessors =
3116 {
3117 ia64_find_proc_info_x,
3118 ia64_put_unwind_info,
3119 ia64_get_dyn_info_list,
3120 ia64_access_mem,
3121 ia64_access_reg,
3122 ia64_access_fpreg,
3123 /* resume */
3124 /* get_proc_name */
3125 };
3127 /* Set of special libunwind callback acccessor functions specific for accessing
3128 the rse registers. At the top of the stack, we want libunwind to figure out
3129 how to read r32 - r127. Though usually they are found sequentially in
3130 memory starting from $bof, this is not always true. */
3131 unw_accessors_t ia64_unw_rse_accessors =
3132 {
3133 ia64_find_proc_info_x,
3134 ia64_put_unwind_info,
3135 ia64_get_dyn_info_list,
3136 ia64_access_mem,
3137 ia64_access_rse_reg,
3138 ia64_access_rse_fpreg,
3139 /* resume */
3140 /* get_proc_name */
3141 };
3143 /* Set of ia64-libunwind-tdep gdb callbacks and data for generic
3144 ia64-libunwind-tdep code to use. */
3146 {
3147 ia64_gdb2uw_regnum,
3148 ia64_uw2gdb_regnum,
3149 ia64_is_fpreg,
3152 };
3156 static int
3158 {
3161 /* Don't use the struct convention for anything but structure,
3162 union, or array types. */
3168 /* HFAs are structures (or arrays) consisting entirely of floating
3169 point values of the same length. Up to 8 of these are returned
3170 in registers. Don't use the struct convention when this is the
3171 case. */
3177 /* Other structs of length 32 or less are returned in r8-r11.
3178 Don't use the struct convention for those either. */
3180 }
3182 /* Return non-zero if TYPE is a structure or union type. */
3184 static int
3186 {
3189 }
3191 static void
3194 {
3200 {
3207 {
3212 regnum++;
3213 }
3214 }
3216 {
3217 /* This is an integral value, and its size is less than 8 bytes.
3218 These values are LSB-aligned, so extract the relevant bytes,
3219 and copy them into VALBUF. */
3220 /* brobecker/2005-12-30: Actually, all integral values are LSB aligned,
3221 so I suppose we should also add handling here for integral values
3222 whose size is greater than 8. But I wasn't able to create such
3223 a type, neither in C nor in Ada, so not worrying about these yet. */
3225 ULONGEST val;
3229 }
3230 else
3231 {
3232 ULONGEST val;
3240 {
3241 ULONGEST regval;
3245 regnum++;
3246 }
3249 {
3252 }
3253 }
3254 }
3256 static void
3259 {
3265 {
3272 {
3277 regnum++;
3278 }
3279 }
3280 else
3281 {
3289 {
3290 ULONGEST val;
3294 regnum++;
3295 }
3298 {
3299 ULONGEST val;
3302 }
3303 }
3304 }
3306 static enum return_value_convention
3310 {
3314 {
3317 }
3320 {
3323 }
3327 else
3329 }
3331 static int
3333 {
3335 {
3339 else
3340 {
3343 }
3346 return
3348 etp);
3351 {
3359 }
3363 }
3366 }
3368 /* Determine if the given type is one of the floating point types or
3369 and HFA (which is a struct, array, or combination thereof whose
3370 bottom-most elements are all of the same floating point type). */
3374 {
3378 }
3381 /* Return 1 if the alignment of T is such that the next even slot
3382 should be used. Return 0, if the next available slot should
3383 be used. (See section 8.5.1 of the IA-64 Software Conventions
3384 and Runtime manual). */
3386 static int
3388 {
3390 {
3395 else
3398 return
3401 {
3409 }
3412 }
3413 }
3415 /* Attempt to find (and return) the global pointer for the given
3416 function.
3418 This is a rather nasty bit of code searchs for the .dynamic section
3419 in the objfile corresponding to the pc of the function we're trying
3420 to call. Once it finds the addresses at which the .dynamic section
3421 lives in the child process, it scans the Elf64_Dyn entries for a
3422 DT_PLTGOT tag. If it finds one of these, the corresponding
3423 d_un.d_ptr value is the global pointer. */
3425 static CORE_ADDR
3427 CORE_ADDR faddr)
3428 {
3434 {
3436 {
3438 {
3443 {
3445 LONGEST tag;
3454 {
3455 CORE_ADDR global_pointer;
3461 global_pointer
3463 byte_order);
3465 /* The payoff... */
3467 }
3473 }
3476 }
3477 }
3478 }
3480 }
3482 /* Attempt to find (and return) the global pointer for the given
3483 function. We first try the find_global_pointer_from_solib routine
3484 from the gdbarch tdep vector, if provided. And if that does not
3485 work, then we try ia64_find_global_pointer_from_dynamic_section. */
3487 static CORE_ADDR
3489 {
3498 }
3500 /* Given a function's address, attempt to find (and return) the
3501 corresponding (canonical) function descriptor. Return 0 if
3502 not found. */
3503 static CORE_ADDR
3505 {
3509 /* Return early if faddr is already a function descriptor. */
3515 {
3517 {
3519 {
3524 {
3526 LONGEST faddr2;
3538 }
3541 }
3542 }
3543 }
3545 }
3547 /* Attempt to find a function descriptor corresponding to the
3548 given address. If none is found, construct one on the
3549 stack using the address at fdaptr. */
3551 static CORE_ADDR
3553 {
3556 CORE_ADDR fdesc;
3561 {
3562 ULONGEST global_pointer;
3578 }
3581 }
3583 /* Use the following routine when printing out function pointers
3584 so the user can see the function address rather than just the
3585 function descriptor. */
3586 static CORE_ADDR
3589 {
3596 /* check if ADDR points to a function descriptor. */
3600 /* Normally, functions live inside a section that is executable.
3601 So, if ADDR points to a non-executable section, then treat it
3602 as a function descriptor and return the target address iff
3603 the target address itself points to a section that is executable.
3604 Check first the memory of the whole length of 8 bytes is readable. */
3607 {
3613 }
3615 /* There are also descriptors embedded in vtables. */
3617 {
3625 }
3628 }
3630 static CORE_ADDR
3632 {
3634 }
3636 /* The default "allocate_new_rse_frame" ia64_infcall_ops routine for ia64. */
3638 static void
3640 {
3656 }
3658 /* The default "store_argument_in_slot" ia64_infcall_ops routine for
3659 ia64. */
3661 static void
3664 {
3666 }
3668 /* The default "set_function_addr" ia64_infcall_ops routine for ia64. */
3670 static void
3672 {
3673 /* Nothing needed. */
3674 }
3676 static CORE_ADDR
3680 function_call_return_method return_method,
3681 CORE_ADDR struct_addr)
3682 {
3691 ULONGEST bsp;
3697 /* Count the number of slots needed for the arguments. */
3699 {
3705 nslots++;
3708 nfuncargs++;
3711 }
3713 /* Divvy up the slots between the RSE and the memory stack. */
3717 /* Allocate a new RSE frame. */
3721 /* We will attempt to find function descriptors in the .opd segment,
3722 but if we can't we'll construct them ourselves. That being the
3723 case, we'll need to reserve space on the stack for them. */
3727 /* Adjust the stack pointer to it's new value. The calling conventions
3728 require us to have 16 bytes of scratch, plus whatever space is
3729 necessary for the memory slots and our function descriptors. */
3733 /* Place the arguments where they belong. The arguments will be
3734 either placed in the RSE backing store or on the memory stack.
3735 In addition, floating point arguments or HFAs are placed in
3736 floating point registers. */
3740 {
3747 /* Special handling for function parameters. */
3751 {
3753 ULONGEST faddr = extract_unsigned_integer
3761 else
3763 slotnum++;
3765 }
3767 /* Normal slots. */
3769 /* Skip odd slot if necessary... */
3771 slotnum++;
3775 {
3780 {
3781 /* Integral types are LSB-aligned, so we have to be careful
3782 to insert the argument on the correct side of the buffer.
3783 This is why we use store_unsigned_integer. */
3784 store_unsigned_integer
3787 byte_order));
3788 }
3789 else
3790 {
3791 /* This is either an 8bit integral type, or an aggregate.
3792 For 8bit integral type, there is no problem, we just
3793 copy the value over.
3795 For aggregates, the only potentially tricky portion
3796 is to write the last one if it is less than 8 bytes.
3797 In this case, the data is Byte0-aligned. Happy news,
3798 this means that we don't need to differentiate the
3799 handling of 8byte blocks and less-than-8bytes blocks. */
3802 }
3807 else
3812 slotnum++;
3813 }
3815 /* Handle floating point types (including HFAs). */
3818 {
3822 {
3828 floatreg++;
3831 }
3832 }
3833 }
3835 /* Store the struct return value in r8 if necessary. */
3845 /* The following is not necessary on HP-UX, because we're using
3846 a dummy code sequence pushed on the stack to make the call, and
3847 this sequence doesn't need b0 to be set in order for our dummy
3848 breakpoint to be hit. Nonetheless, this doesn't interfere, and
3849 it's needed for other OSes, so we do this unconditionaly. */
3857 }
3860 {
3861 ia64_allocate_new_rse_frame,
3862 ia64_store_argument_in_slot,
3863 ia64_set_function_addr
3864 };
3866 static struct frame_id
3868 {
3886 }
3888 static CORE_ADDR
3890 {
3902 }
3904 static int
3906 {
3909 }
3911 /* The default "size_of_register_frame" gdbarch_tdep routine for ia64. */
3913 static int
3915 {
3917 }
3921 {
3922 /* If there is already a candidate, use it. */
3927 gdbarch *gdbarch
3933 /* According to the ia64 specs, instructions that store long double
3934 floats in memory use a long-double format different than that
3935 used in the floating registers. The memory format matches the
3936 x86 extended float format which is 80 bits. An OS may choose to
3937 use this format (e.g. GNU/Linux) or choose to use a different
3938 format for storing long doubles (e.g. HPUX). In the latter case,
3939 the setting of the format may be moved/overridden in an
3940 OS-specific tdep file. */
3963 ia64_pseudo_register_write);
3975 ia64_memory_insert_breakpoint);
3977 ia64_memory_remove_breakpoint);
3983 /* Settings for calling functions in the inferior. */
3990 #ifdef HAVE_LIBUNWIND_IA64_H
3996 #else
3998 #endif
4002 /* Settings that should be unnecessary. */
4007 ia64_convert_from_func_ptr_addr);
4009 /* The virtual table contains 16-byte descriptors, not pointers to
4010 descriptors. */
4013 /* Hook in ABI-specific overrides, if they have been registered. */
4017 }
4020 void
4022 {
4024 }