bfd/verilog.c

   1 /* BFD back-end for verilog hex memory dump files.
   2    Copyright (C) 2009-2022 Free Software Foundation, Inc.
   3    Written by Anthony Green <green@moxielogic.com>
   4
   5    This file is part of BFD, the Binary File Descriptor library.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; if not, write to the Free Software
  19    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  20    MA 02110-1301, USA.  */
  21
  22
  23 /* SUBSECTION
  24         Verilog hex memory file handling
  25
  26    DESCRIPTION
  27
  28         Verilog hex memory files cannot hold anything but addresses
  29         and data, so that's all that we implement.
  30
  31         The syntax of the text file is described in the IEEE standard
  32         for Verilog.  Briefly, the file contains two types of tokens:
  33         data and optional addresses.  The tokens are separated by
  34         whitespace and comments.  Comments may be single line or
  35         multiline, using syntax similar to C++.  Addresses are
  36         specified by a leading "at" character (@) and are always
  37         hexadecimal strings.  Data and addresses may contain
  38         underscore (_) characters.
  39
  40         If no address is specified, the data is assumed to start at
  41         address 0.  Similarly, if data exists before the first
  42         specified address, then that data is assumed to start at
  43         address 0.
  44
  45
  46    EXAMPLE
  47         @1000
  48         01 ae 3f 45 12
  49
  50    DESCRIPTION
  51         @1000 specifies the starting address for the memory data.
  52         The following characters describe the 5 bytes at 0x1000.  */
  53
  54
  55 #include "sysdep.h"
  56 #include "bfd.h"
  57 #include "libbfd.h"
  58 #include "libiberty.h"
  59 #include "safe-ctype.h"
  60
  61 /* Modified by obcopy.c
  62    Data width in bytes.  */
  63 unsigned int VerilogDataWidth = 1;
  64
  65 /* Macros for converting between hex and binary.  */
  66
  67 static const char digs[] = "0123456789ABCDEF";
  68
  69 #define NIBBLE(x)    hex_value (x)
  70 #define HEX(buffer) ((NIBBLE ((buffer)[0]) << 4) + NIBBLE ((buffer)[1]))
  71 #define TOHEX(d, x) \
  72         d[1] = digs[(x) & 0xf]; \
  73         d[0] = digs[((x) >> 4) & 0xf];
  74
  75 /* When writing a verilog memory dump file, we write them in the order
  76    in which they appear in memory. This structure is used to hold them
  77    in memory.  */
  78
  79 struct verilog_data_list_struct
  80 {
  81   struct verilog_data_list_struct *next;
  82   bfd_byte * data;
  83   bfd_vma where;
  84   bfd_size_type size;
  85 };
  86
  87 typedef struct verilog_data_list_struct verilog_data_list_type;
  88
  89 /* The verilog tdata information.  */
  90
  91 typedef struct verilog_data_struct
  92 {
  93   verilog_data_list_type *head;
  94   verilog_data_list_type *tail;
  95 }
  96 tdata_type;
  97
  98 static bool
  99 verilog_set_arch_mach (bfd *abfd, enum bfd_architecture arch, unsigned long mach)
 100 {
 101   if (arch != bfd_arch_unknown)
 102     return bfd_default_set_arch_mach (abfd, arch, mach);
 103
 104   abfd->arch_info = & bfd_default_arch_struct;
 105   return true;
 106 }
 107
 108 /* We have to save up all the outpu for a splurge before output.  */
 109
 110 static bool
 111 verilog_set_section_contents (bfd *abfd,
 112                               sec_ptr section,
 113                               const void * location,
 114                               file_ptr offset,
 115                               bfd_size_type bytes_to_do)
 116 {
 117   tdata_type *tdata = abfd->tdata.verilog_data;
 118   verilog_data_list_type *entry;
 119
 120   entry = (verilog_data_list_type *) bfd_alloc (abfd, sizeof (* entry));
 121   if (entry == NULL)
 122     return false;
 123
 124   if (bytes_to_do
 125       && (section->flags & SEC_ALLOC)
 126       && (section->flags & SEC_LOAD))
 127     {
 128       bfd_byte *data;
 129
 130       data = (bfd_byte *) bfd_alloc (abfd, bytes_to_do);
 131       if (data == NULL)
 132         return false;
 133       memcpy ((void *) data, location, (size_t) bytes_to_do);
 134
 135       entry->data = data;
 136       entry->where = section->lma + offset;
 137       entry->size = bytes_to_do;
 138
 139       /* Sort the records by address.  Optimize for the common case of
 140          adding a record to the end of the list.  */
 141       if (tdata->tail != NULL
 142           && entry->where >= tdata->tail->where)
 143         {
 144           tdata->tail->next = entry;
 145           entry->next = NULL;
 146           tdata->tail = entry;
 147         }
 148       else
 149         {
 150           verilog_data_list_type **look;
 151
 152           for (look = &tdata->head;
 153                *look != NULL && (*look)->where < entry->where;
 154                look = &(*look)->next)
 155             ;
 156           entry->next = *look;
 157           *look = entry;
 158           if (entry->next == NULL)
 159             tdata->tail = entry;
 160         }
 161     }
 162   return true;
 163 }
 164
 165 static bool
 166 verilog_write_address (bfd *abfd, bfd_vma address)
 167 {
 168   char buffer[20];
 169   char *dst = buffer;
 170   bfd_size_type wrlen;
 171
 172   /* Write the address.  */
 173   *dst++ = '@';
 174 #ifdef BFD64
 175   if (address >= (bfd_vma)1 << 32)
 176     {
 177       TOHEX (dst, (address >> 56));
 178       dst += 2;
 179       TOHEX (dst, (address >> 48));
 180       dst += 2;
 181       TOHEX (dst, (address >> 40));
 182       dst += 2;
 183       TOHEX (dst, (address >> 32));
 184       dst += 2;
 185     }
 186 #endif
 187   TOHEX (dst, (address >> 24));
 188   dst += 2;
 189   TOHEX (dst, (address >> 16));
 190   dst += 2;
 191   TOHEX (dst, (address >> 8));
 192   dst += 2;
 193   TOHEX (dst, (address));
 194   dst += 2;
 195   *dst++ = '\r';
 196   *dst++ = '\n';
 197   wrlen = dst - buffer;
 198
 199   return bfd_bwrite ((void *) buffer, wrlen, abfd) == wrlen;
 200 }
 201
 202 /* Write a record of type, of the supplied number of bytes. The
 203    supplied bytes and length don't have a checksum.  That's worked
 204    out here.  */
 205
 206 static bool
 207 verilog_write_record (bfd *abfd,
 208                       const bfd_byte *data,
 209                       const bfd_byte *end)
 210 {
 211   char buffer[52];
 212   const bfd_byte *src = data;
 213   char *dst = buffer;
 214   bfd_size_type wrlen;
 215
 216   /* Paranoia - check that we will not overflow "buffer".  */
 217   if (((end - data) * 2) /* Number of hex characters we want to emit.  */
 218       + ((end - data) / VerilogDataWidth) /* Number of spaces we want to emit.  */
 219       + 2 /* The carriage return & line feed characters.  */
 220       > (long) sizeof (buffer))
 221     {
 222       /* FIXME: Should we generate an error message ?  */
 223       return false;
 224     }
 225
 226   /* Write the data.
 227      FIXME: Under some circumstances we can emit a space at the end of
 228      the line.  This is not really necessary, but catching these cases
 229      would make the code more complicated.  */
 230   if (VerilogDataWidth == 1)
 231     {
 232       for (src = data; src < end;)
 233         {
 234           TOHEX (dst, *src);
 235           dst += 2;
 236           src ++;
 237           if (src < end)
 238             *dst++ = ' ';
 239         }
 240     }
 241   else if (bfd_little_endian (abfd))
 242     {
 243       /* If the input byte stream contains:
 244            05 04 03 02 01 00
 245          and VerilogDataWidth is 4 then we want to emit:
 246            02030405 0001  */
 247       int i;
 248
 249       for (src = data; src < (end - VerilogDataWidth); src += VerilogDataWidth)
 250         {
 251           for (i = VerilogDataWidth - 1; i >= 0; i--)
 252             {
 253               TOHEX (dst, src[i]);
 254               dst += 2;
 255             }
 256           *dst++ = ' ';
 257         }
 258
 259       /* Emit any remaining bytes.  Be careful not to read beyond "end".  */
 260       while (end > src)
 261         {
 262           -- end;
 263           TOHEX (dst, *end);
 264           dst += 2;
 265         }
 266     }
 267   else
 268     {
 269       for (src = data; src < end;)
 270         {
 271           TOHEX (dst, *src);
 272           dst += 2;
 273           ++ src;
 274           if ((src - data) % VerilogDataWidth == 0)
 275             *dst++ = ' ';
 276         }
 277     }
 278
 279   *dst++ = '\r';
 280   *dst++ = '\n';
 281   wrlen = dst - buffer;
 282
 283   return bfd_bwrite ((void *) buffer, wrlen, abfd) == wrlen;
 284 }
 285
 286 static bool
 287 verilog_write_section (bfd *abfd,
 288                        tdata_type *tdata ATTRIBUTE_UNUSED,
 289                        verilog_data_list_type *list)
 290 {
 291   unsigned int octets_written = 0;
 292   bfd_byte *location = list->data;
 293
 294   verilog_write_address (abfd, list->where);
 295   while (octets_written < list->size)
 296     {
 297       unsigned int octets_this_chunk = list->size - octets_written;
 298
 299       if (octets_this_chunk > 16)
 300         octets_this_chunk = 16;
 301
 302       if (! verilog_write_record (abfd,
 303                                   location,
 304                                   location + octets_this_chunk))
 305         return false;
 306
 307       octets_written += octets_this_chunk;
 308       location += octets_this_chunk;
 309     }
 310
 311   return true;
 312 }
 313
 314 static bool
 315 verilog_write_object_contents (bfd *abfd)
 316 {
 317   tdata_type *tdata = abfd->tdata.verilog_data;
 318   verilog_data_list_type *list;
 319
 320   /* Now wander though all the sections provided and output them.  */
 321   list = tdata->head;
 322
 323   while (list != (verilog_data_list_type *) NULL)
 324     {
 325       if (! verilog_write_section (abfd, tdata, list))
 326         return false;
 327       list = list->next;
 328     }
 329   return true;
 330 }
 331
 332 /* Initialize by filling in the hex conversion array.  */
 333
 334 static void
 335 verilog_init (void)
 336 {
 337   static bool inited = false;
 338
 339   if (! inited)
 340     {
 341       inited = true;
 342       hex_init ();
 343     }
 344 }
 345
 346 /* Set up the verilog tdata information.  */
 347
 348 static bool
 349 verilog_mkobject (bfd *abfd)
 350 {
 351   tdata_type *tdata;
 352
 353   verilog_init ();
 354
 355   tdata = (tdata_type *) bfd_alloc (abfd, sizeof (tdata_type));
 356   if (tdata == NULL)
 357     return false;
 358
 359   abfd->tdata.verilog_data = tdata;
 360   tdata->head = NULL;
 361   tdata->tail = NULL;
 362
 363   return true;
 364 }
 365
 366 #define verilog_close_and_cleanup                    _bfd_generic_close_and_cleanup
 367 #define verilog_bfd_free_cached_info                 _bfd_generic_bfd_free_cached_info
 368 #define verilog_new_section_hook                     _bfd_generic_new_section_hook
 369 #define verilog_bfd_is_target_special_symbol         _bfd_bool_bfd_asymbol_false
 370 #define verilog_bfd_is_local_label_name              bfd_generic_is_local_label_name
 371 #define verilog_get_lineno                           _bfd_nosymbols_get_lineno
 372 #define verilog_find_nearest_line                    _bfd_nosymbols_find_nearest_line
 373 #define verilog_find_nearest_line_with_alt           _bfd_nosymbols_find_nearest_line_with_alt
 374 #define verilog_find_inliner_info                    _bfd_nosymbols_find_inliner_info
 375 #define verilog_make_empty_symbol                    _bfd_generic_make_empty_symbol
 376 #define verilog_bfd_make_debug_symbol                _bfd_nosymbols_bfd_make_debug_symbol
 377 #define verilog_read_minisymbols                     _bfd_generic_read_minisymbols
 378 #define verilog_minisymbol_to_symbol                 _bfd_generic_minisymbol_to_symbol
 379 #define verilog_get_section_contents_in_window       _bfd_generic_get_section_contents_in_window
 380 #define verilog_bfd_get_relocated_section_contents   bfd_generic_get_relocated_section_contents
 381 #define verilog_bfd_relax_section                    bfd_generic_relax_section
 382 #define verilog_bfd_gc_sections                      bfd_generic_gc_sections
 383 #define verilog_bfd_merge_sections                   bfd_generic_merge_sections
 384 #define verilog_bfd_is_group_section                 bfd_generic_is_group_section
 385 #define verilog_bfd_group_name                       bfd_generic_group_name
 386 #define verilog_bfd_discard_group                    bfd_generic_discard_group
 387 #define verilog_section_already_linked               _bfd_generic_section_already_linked
 388 #define verilog_bfd_link_hash_table_create           _bfd_generic_link_hash_table_create
 389 #define verilog_bfd_link_add_symbols                 _bfd_generic_link_add_symbols
 390 #define verilog_bfd_link_just_syms                   _bfd_generic_link_just_syms
 391 #define verilog_bfd_final_link                       _bfd_generic_final_link
 392 #define verilog_bfd_link_split_section               _bfd_generic_link_split_section
 393
 394 const bfd_target verilog_vec =
 395 {
 396   "verilog",                    /* Name.  */
 397   bfd_target_verilog_flavour,
 398   BFD_ENDIAN_UNKNOWN,           /* Target byte order.  */
 399   BFD_ENDIAN_UNKNOWN,           /* Target headers byte order.  */
 400   (HAS_RELOC | EXEC_P |         /* Object flags.  */
 401    HAS_LINENO | HAS_DEBUG |
 402    HAS_SYMS | HAS_LOCALS | WP_TEXT | D_PAGED),
 403   (SEC_CODE | SEC_DATA | SEC_ROM | SEC_HAS_CONTENTS
 404    | SEC_ALLOC | SEC_LOAD | SEC_RELOC), /* Section flags.  */
 405   0,                            /* Leading underscore.  */
 406   ' ',                          /* AR_pad_char.  */
 407   16,                           /* AR_max_namelen.  */
 408   0,                            /* match priority.  */
 409   TARGET_KEEP_UNUSED_SECTION_SYMBOLS, /* keep unused section symbols.  */
 410   bfd_getb64, bfd_getb_signed_64, bfd_putb64,
 411   bfd_getb32, bfd_getb_signed_32, bfd_putb32,
 412   bfd_getb16, bfd_getb_signed_16, bfd_putb16,   /* Data.  */
 413   bfd_getb64, bfd_getb_signed_64, bfd_putb64,
 414   bfd_getb32, bfd_getb_signed_32, bfd_putb32,
 415   bfd_getb16, bfd_getb_signed_16, bfd_putb16,   /* Hdrs.  */
 416
 417   {
 418     _bfd_dummy_target,
 419     _bfd_dummy_target,
 420     _bfd_dummy_target,
 421     _bfd_dummy_target,
 422   },
 423   {
 424     _bfd_bool_bfd_false_error,
 425     verilog_mkobject,
 426     _bfd_bool_bfd_false_error,
 427     _bfd_bool_bfd_false_error,
 428   },
 429   {                             /* bfd_write_contents.  */
 430     _bfd_bool_bfd_false_error,
 431     verilog_write_object_contents,
 432     _bfd_bool_bfd_false_error,
 433     _bfd_bool_bfd_false_error,
 434   },
 435
 436   BFD_JUMP_TABLE_GENERIC (_bfd_generic),
 437   BFD_JUMP_TABLE_COPY (_bfd_generic),
 438   BFD_JUMP_TABLE_CORE (_bfd_nocore),
 439   BFD_JUMP_TABLE_ARCHIVE (_bfd_noarchive),
 440   BFD_JUMP_TABLE_SYMBOLS (_bfd_nosymbols),
 441   BFD_JUMP_TABLE_RELOCS (_bfd_norelocs),
 442   BFD_JUMP_TABLE_WRITE (verilog),
 443   BFD_JUMP_TABLE_LINK (_bfd_nolink),
 444   BFD_JUMP_TABLE_DYNAMIC (_bfd_nodynamic),
 445
 446   NULL,
 447
 448   NULL
 449 };