opcodes/tic30-dis.c

   1 /* Disassembly routines for TMS320C30 architecture
   2    Copyright (C) 1998 Free Software Foundation, Inc.
   3    Contributed by Steven Haworth (steve@pm.cse.rmit.edu.au)
   4
   5    This program is free software; you can redistribute it and/or modify
   6    it under the terms of the GNU General Public License as published by
   7    the Free Software Foundation; either version 2 of the License, or
   8    (at your option) any later version.
   9
  10    This program is distributed in the hope that it will be useful,
  11    but WITHOUT ANY WARRANTY; without even the implied warranty of
  12    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13    GNU General Public License for more details.
  14
  15    You should have received a copy of the GNU General Public License
  16    along with this program; if not, write to the Free Software
  17    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA
  18    02111-1307, USA.  */
  19
  20 #include <errno.h>
  21 #include <math.h>
  22 #include <stdlib.h>
  23 #include <string.h>
  24 #include "dis-asm.h"
  25 #include "opcode/tic30.h"
  26
  27 #define NORMAL_INSN   1
  28 #define PARALLEL_INSN 2
  29
  30 /* Gets the type of instruction based on the top 2 or 3 bits of the
  31    instruction word. */
  32 #define GET_TYPE(insn) (insn & 0x80000000 ? insn & 0xC0000000 : insn & 0xE0000000)
  33
  34 /* Instruction types. */
  35 #define TWO_OPERAND_1 0x00000000
  36 #define TWO_OPERAND_2 0x40000000
  37 #define THREE_OPERAND 0x20000000
  38 #define PAR_STORE     0xC0000000
  39 #define MUL_ADDS      0x80000000
  40 #define BRANCHES      0x60000000
  41
  42 /* Specific instruction id bits. */
  43 #define NORMAL_IDEN    0x1F800000
  44 #define PAR_STORE_IDEN 0x3E000000
  45 #define MUL_ADD_IDEN   0x2C000000
  46 #define BR_IMM_IDEN    0x1F000000
  47 #define BR_COND_IDEN   0x1C3F0000
  48
  49 /* Addressing modes. */
  50 #define AM_REGISTER 0x00000000
  51 #define AM_DIRECT   0x00200000
  52 #define AM_INDIRECT 0x00400000
  53 #define AM_IMM      0x00600000
  54
  55 #define P_FIELD 0x03000000
  56
  57 #define REG_AR0 0x08
  58 #define LDP_INSN 0x08700000
  59
  60 /* TMS320C30 program counter for current instruction. */
  61 static unsigned int _pc;
  62
  63 struct instruction
  64   {
  65     int type;
  66     template *tm;
  67     partemplate *ptm;
  68   };
  69
  70 int get_tic30_instruction PARAMS ((unsigned long, struct instruction *));
  71 int print_two_operand
  72   PARAMS ((disassemble_info *, unsigned long, struct instruction *));
  73 int print_three_operand
  74   PARAMS ((disassemble_info *, unsigned long, struct instruction *));
  75 int print_par_insn
  76   PARAMS ((disassemble_info *, unsigned long, struct instruction *));
  77 int print_branch
  78   PARAMS ((disassemble_info *, unsigned long, struct instruction *));
  79 int get_indirect_operand PARAMS ((unsigned short, int, char *));
  80 int get_register_operand PARAMS ((unsigned char, char *));
  81 int cnvt_tmsfloat_ieee PARAMS ((unsigned long, int, float *));
  82
  83 int
  84 print_insn_tic30 (pc, info)
  85      bfd_vma pc;
  86      disassemble_info *info;
  87 {
  88   unsigned long insn_word;
  89   struct instruction insn =
  90   {0, NULL, NULL};
  91   bfd_vma bufaddr = pc - info->buffer_vma;
  92   /* Obtain the current instruction word from the buffer. */
  93   insn_word = (*(info->buffer + bufaddr) << 24) | (*(info->buffer + bufaddr + 1) << 16) |
  94     (*(info->buffer + bufaddr + 2) << 8) | *(info->buffer + bufaddr + 3);
  95   _pc = pc / 4;
  96   /* Get the instruction refered to by the current instruction word
  97      and print it out based on its type. */
  98   if (!get_tic30_instruction (insn_word, &insn))
  99     return -1;
 100   switch (GET_TYPE (insn_word))
 101     {
 102     case TWO_OPERAND_1:
 103     case TWO_OPERAND_2:
 104       if (!print_two_operand (info, insn_word, &insn))
 105         return -1;
 106       break;
 107     case THREE_OPERAND:
 108       if (!print_three_operand (info, insn_word, &insn))
 109         return -1;
 110       break;
 111     case PAR_STORE:
 112     case MUL_ADDS:
 113       if (!print_par_insn (info, insn_word, &insn))
 114         return -1;
 115       break;
 116     case BRANCHES:
 117       if (!print_branch (info, insn_word, &insn))
 118         return -1;
 119       break;
 120     }
 121   return 4;
 122 }
 123
 124 int
 125 get_tic30_instruction (insn_word, insn)
 126      unsigned long insn_word;
 127      struct instruction *insn;
 128 {
 129   switch (GET_TYPE (insn_word))
 130     {
 131     case TWO_OPERAND_1:
 132     case TWO_OPERAND_2:
 133     case THREE_OPERAND:
 134       insn->type = NORMAL_INSN;
 135       {
 136         template *current_optab = (template *) tic30_optab;
 137         for (; current_optab < tic30_optab_end; current_optab++)
 138           {
 139             if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word))
 140               {
 141                 if (current_optab->operands == 0)
 142                   {
 143                     if (current_optab->base_opcode == insn_word)
 144                       {
 145                         insn->tm = current_optab;
 146                         break;
 147                       }
 148                   }
 149                 else if ((current_optab->base_opcode & NORMAL_IDEN) == (insn_word & NORMAL_IDEN))
 150                   {
 151                     insn->tm = current_optab;
 152                     break;
 153                   }
 154               }
 155           }
 156       }
 157       break;
 158     case PAR_STORE:
 159       insn->type = PARALLEL_INSN;
 160       {
 161         partemplate *current_optab = (partemplate *) tic30_paroptab;
 162         for (; current_optab < tic30_paroptab_end; current_optab++)
 163           {
 164             if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word))
 165               {
 166                 if ((current_optab->base_opcode & PAR_STORE_IDEN) == (insn_word & PAR_STORE_IDEN))
 167                   {
 168                     insn->ptm = current_optab;
 169                     break;
 170                   }
 171               }
 172           }
 173       }
 174       break;
 175     case MUL_ADDS:
 176       insn->type = PARALLEL_INSN;
 177       {
 178         partemplate *current_optab = (partemplate *) tic30_paroptab;
 179         for (; current_optab < tic30_paroptab_end; current_optab++)
 180           {
 181             if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word))
 182               {
 183                 if ((current_optab->base_opcode & MUL_ADD_IDEN) == (insn_word & MUL_ADD_IDEN))
 184                   {
 185                     insn->ptm = current_optab;
 186                     break;
 187                   }
 188               }
 189           }
 190       }
 191       break;
 192     case BRANCHES:
 193       insn->type = NORMAL_INSN;
 194       {
 195         template *current_optab = (template *) tic30_optab;
 196         for (; current_optab < tic30_optab_end; current_optab++)
 197           {
 198             if (GET_TYPE (current_optab->base_opcode) == GET_TYPE (insn_word))
 199               {
 200                 if (current_optab->operand_types[0] & Imm24)
 201                   {
 202                     if ((current_optab->base_opcode & BR_IMM_IDEN) == (insn_word & BR_IMM_IDEN))
 203                       {
 204                         insn->tm = current_optab;
 205                         break;
 206                       }
 207                   }
 208                 else if (current_optab->operands > 0)
 209                   {
 210                     if ((current_optab->base_opcode & BR_COND_IDEN) == (insn_word & BR_COND_IDEN))
 211                       {
 212                         insn->tm = current_optab;
 213                         break;
 214                       }
 215                   }
 216                 else
 217                   {
 218                     if ((current_optab->base_opcode & (BR_COND_IDEN | 0x00800000)) == (insn_word & (BR_COND_IDEN | 0x00800000)))
 219                       {
 220                         insn->tm = current_optab;
 221                         break;
 222                       }
 223                   }
 224               }
 225           }
 226       }
 227       break;
 228     default:
 229       return 0;
 230     }
 231   return 1;
 232 }
 233
 234 int
 235 print_two_operand (info, insn_word, insn)
 236      disassemble_info *info;
 237      unsigned long insn_word;
 238      struct instruction *insn;
 239 {
 240   char name[12];
 241   char operand[2][13] =
 242   {
 243     {0},
 244     {0}};
 245   float f_number;
 246
 247   if (insn->tm == NULL)
 248     return 0;
 249   strcpy (name, insn->tm->name);
 250   if (insn->tm->opcode_modifier == AddressMode)
 251     {
 252       int src_op, dest_op;
 253       /* Determine whether instruction is a store or a normal instruction. */
 254       if ((insn->tm->operand_types[1] & (Direct | Indirect)) == (Direct | Indirect))
 255         {
 256           src_op = 1;
 257           dest_op = 0;
 258         }
 259       else
 260         {
 261           src_op = 0;
 262           dest_op = 1;
 263         }
 264       /* Get the destination register. */
 265       if (insn->tm->operands == 2)
 266         get_register_operand ((insn_word & 0x001F0000) >> 16, operand[dest_op]);
 267       /* Get the source operand based on addressing mode. */
 268       switch (insn_word & AddressMode)
 269         {
 270         case AM_REGISTER:
 271           /* Check for the NOP instruction before getting the operand. */
 272           if ((insn->tm->operand_types[0] & NotReq) == 0)
 273             get_register_operand ((insn_word & 0x0000001F), operand[src_op]);
 274           break;
 275         case AM_DIRECT:
 276           sprintf (operand[src_op], "@0x%lX", (insn_word & 0x0000FFFF));
 277           break;
 278         case AM_INDIRECT:
 279           get_indirect_operand ((insn_word & 0x0000FFFF), 2, operand[src_op]);
 280           break;
 281         case AM_IMM:
 282           /* Get the value of the immediate operand based on variable type. */
 283           switch (insn->tm->imm_arg_type)
 284             {
 285             case Imm_Float:
 286               cnvt_tmsfloat_ieee ((insn_word & 0x0000FFFF), 2, &f_number);
 287               sprintf (operand[src_op], "%2.2f", f_number);
 288               break;
 289             case Imm_SInt:
 290               sprintf (operand[src_op], "%d", (short) (insn_word & 0x0000FFFF));
 291               break;
 292             case Imm_UInt:
 293               sprintf (operand[src_op], "%lu", (insn_word & 0x0000FFFF));
 294               break;
 295             default:
 296               return 0;
 297             }
 298           /* Handle special case for LDP instruction. */
 299           if ((insn_word & 0xFFFFFF00) == LDP_INSN)
 300             {
 301               strcpy (name, "ldp");
 302               sprintf (operand[0], "0x%06lX", (insn_word & 0x000000FF) << 16);
 303               operand[1][0] = '\0';
 304             }
 305         }
 306     }
 307   /* Handle case for stack and rotate instructions. */
 308   else if (insn->tm->operands == 1)
 309     {
 310       if (insn->tm->opcode_modifier == StackOp)
 311         {
 312           get_register_operand ((insn_word & 0x001F0000) >> 16, operand[0]);
 313         }
 314     }
 315   /* Output instruction to stream. */
 316   info->fprintf_func (info->stream, "   %s %s%c%s", name,
 317                       operand[0][0] ? operand[0] : "",
 318                       operand[1][0] ? ',' : ' ',
 319                       operand[1][0] ? operand[1] : "");
 320   return 1;
 321 }
 322
 323 int
 324 print_three_operand (info, insn_word, insn)
 325      disassemble_info *info;
 326      unsigned long insn_word;
 327      struct instruction *insn;
 328 {
 329   char operand[3][13] =
 330   {
 331     {0},
 332     {0},
 333     {0}};
 334
 335   if (insn->tm == NULL)
 336     return 0;
 337   switch (insn_word & AddressMode)
 338     {
 339     case AM_REGISTER:
 340       get_register_operand ((insn_word & 0x000000FF), operand[0]);
 341       get_register_operand ((insn_word & 0x0000FF00) >> 8, operand[1]);
 342       break;
 343     case AM_DIRECT:
 344       get_register_operand ((insn_word & 0x000000FF), operand[0]);
 345       get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1]);
 346       break;
 347     case AM_INDIRECT:
 348       get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0]);
 349       get_register_operand ((insn_word & 0x0000FF00) >> 8, operand[1]);
 350       break;
 351     case AM_IMM:
 352       get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0]);
 353       get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1]);
 354       break;
 355     default:
 356       return 0;
 357     }
 358   if (insn->tm->operands == 3)
 359     get_register_operand ((insn_word & 0x001F0000) >> 16, operand[2]);
 360   info->fprintf_func (info->stream, "   %s %s,%s%c%s", insn->tm->name,
 361                       operand[0], operand[1],
 362                       operand[2][0] ? ',' : ' ',
 363                       operand[2][0] ? operand[2] : "");
 364   return 1;
 365 }
 366
 367 int
 368 print_par_insn (info, insn_word, insn)
 369      disassemble_info *info;
 370      unsigned long insn_word;
 371      struct instruction *insn;
 372 {
 373   int i;
 374   char *name1, *name2;
 375   char operand[2][3][13] =
 376   {
 377     {
 378       {0},
 379       {0},
 380       {0}},
 381     {
 382       {0},
 383       {0},
 384       {0}}};
 385
 386   if (insn->ptm == NULL)
 387     return 0;
 388   /* Parse out the names of each of the parallel instructions from the
 389      q_insn1_insn2 format. */
 390   name1 = (char *) strdup (insn->ptm->name + 2);
 391   for (i = 0; i < strlen (name1); i++)
 392     {
 393       if (name1[i] == '_')
 394         {
 395           name2 = &name1[i + 1];
 396           name1[i] = '\0';
 397           break;
 398         }
 399     }
 400   /* Get the operands of the instruction based on the operand order. */
 401   switch (insn->ptm->oporder)
 402     {
 403     case OO_4op1:
 404       get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]);
 405       get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]);
 406       get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
 407       get_register_operand ((insn_word >> 22) & 0x07, operand[0][1]);
 408       break;
 409     case OO_4op2:
 410       get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]);
 411       get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][0]);
 412       get_register_operand ((insn_word >> 19) & 0x07, operand[1][1]);
 413       get_register_operand ((insn_word >> 22) & 0x07, operand[0][1]);
 414       break;
 415     case OO_4op3:
 416       get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]);
 417       get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]);
 418       get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
 419       get_register_operand ((insn_word >> 22) & 0x07, operand[0][0]);
 420       break;
 421     case OO_5op1:
 422       get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][0]);
 423       get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]);
 424       get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
 425       get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]);
 426       get_register_operand ((insn_word >> 22) & 0x07, operand[0][2]);
 427       break;
 428     case OO_5op2:
 429       get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]);
 430       get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][1]);
 431       get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
 432       get_register_operand ((insn_word >> 19) & 0x07, operand[0][0]);
 433       get_register_operand ((insn_word >> 22) & 0x07, operand[0][2]);
 434       break;
 435     case OO_PField:
 436       if (insn_word & 0x00800000)
 437         get_register_operand (0x01, operand[0][2]);
 438       else
 439         get_register_operand (0x00, operand[0][2]);
 440       if (insn_word & 0x00400000)
 441         get_register_operand (0x03, operand[1][2]);
 442       else
 443         get_register_operand (0x02, operand[1][2]);
 444       switch (insn_word & P_FIELD)
 445         {
 446         case 0x00000000:
 447           get_indirect_operand ((insn_word & 0x000000FF), 1, operand[0][1]);
 448           get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]);
 449           get_register_operand ((insn_word >> 16) & 0x07, operand[1][1]);
 450           get_register_operand ((insn_word >> 19) & 0x07, operand[1][0]);
 451           break;
 452         case 0x01000000:
 453           get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][0]);
 454           get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]);
 455           get_register_operand ((insn_word >> 16) & 0x07, operand[1][1]);
 456           get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]);
 457           break;
 458         case 0x02000000:
 459           get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][1]);
 460           get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[1][0]);
 461           get_register_operand ((insn_word >> 16) & 0x07, operand[0][1]);
 462           get_register_operand ((insn_word >> 19) & 0x07, operand[0][0]);
 463           break;
 464         case 0x03000000:
 465           get_indirect_operand ((insn_word & 0x000000FF), 1, operand[1][1]);
 466           get_indirect_operand ((insn_word & 0x0000FF00) >> 8, 1, operand[0][0]);
 467           get_register_operand ((insn_word >> 16) & 0x07, operand[1][0]);
 468           get_register_operand ((insn_word >> 19) & 0x07, operand[0][1]);
 469           break;
 470         }
 471       break;
 472     default:
 473       return 0;
 474     }
 475   info->fprintf_func (info->stream, "   %s %s,%s%c%s", name1,
 476                       operand[0][0], operand[0][1],
 477                       operand[0][2][0] ? ',' : ' ',
 478                       operand[0][2][0] ? operand[0][2] : "");
 479   info->fprintf_func (info->stream, "\n\t\t\t|| %s %s,%s%c%s", name2,
 480                       operand[1][0], operand[1][1],
 481                       operand[1][2][0] ? ',' : ' ',
 482                       operand[1][2][0] ? operand[1][2] : "");
 483   free (name1);
 484   return 1;
 485 }
 486
 487 int
 488 print_branch (info, insn_word, insn)
 489      disassemble_info *info;
 490      unsigned long insn_word;
 491      struct instruction *insn;
 492 {
 493   char operand[2][13] =
 494   {
 495     {0},
 496     {0}};
 497   unsigned long address;
 498   int print_label = 0;
 499
 500   if (insn->tm == NULL)
 501     return 0;
 502   /* Get the operands for 24-bit immediate jumps. */
 503   if (insn->tm->operand_types[0] & Imm24)
 504     {
 505       address = insn_word & 0x00FFFFFF;
 506       sprintf (operand[0], "0x%lX", address);
 507       print_label = 1;
 508     }
 509   /* Get the operand for the trap instruction. */
 510   else if (insn->tm->operand_types[0] & IVector)
 511     {
 512       address = insn_word & 0x0000001F;
 513       sprintf (operand[0], "0x%lX", address);
 514     }
 515   else
 516     {
 517       address = insn_word & 0x0000FFFF;
 518       /* Get the operands for the DB instructions. */
 519       if (insn->tm->operands == 2)
 520         {
 521           get_register_operand (((insn_word & 0x01C00000) >> 22) + REG_AR0, operand[0]);
 522           if (insn_word & PCRel)
 523             {
 524               sprintf (operand[1], "%d", (short) address);
 525               print_label = 1;
 526             }
 527           else
 528             get_register_operand (insn_word & 0x0000001F, operand[1]);
 529         }
 530       /* Get the operands for the standard branches. */
 531       else if (insn->tm->operands == 1)
 532         {
 533           if (insn_word & PCRel)
 534             {
 535               address = (short) address;
 536               sprintf (operand[0], "%ld", address);
 537               print_label = 1;
 538             }
 539           else
 540             get_register_operand (insn_word & 0x0000001F, operand[0]);
 541         }
 542     }
 543   info->fprintf_func (info->stream, "   %s %s%c%s", insn->tm->name,
 544                       operand[0][0] ? operand[0] : "",
 545                       operand[1][0] ? ',' : ' ',
 546                       operand[1][0] ? operand[1] : "");
 547   /* Print destination of branch in relation to current symbol. */
 548   if (print_label && info->symbol)
 549     {
 550       if ((insn->tm->opcode_modifier == PCRel) && (insn_word & PCRel))
 551         {
 552           address = (_pc + 1 + (short) address) - ((info->symbol->section->vma + info->symbol->value) / 4);
 553           /* Check for delayed instruction, if so adjust destination. */
 554           if (insn_word & 0x00200000)
 555             address += 2;
 556         }
 557       else
 558         {
 559           address -= ((info->symbol->section->vma + info->symbol->value) / 4);
 560         }
 561       if (address == 0)
 562         info->fprintf_func (info->stream, " <%s>", info->symbol->name);
 563       else
 564         info->fprintf_func (info->stream, " <%s %c %d>", info->symbol->name,
 565                             ((short) address < 0) ? '-' : '+',
 566                             abs (address));
 567     }
 568   return 1;
 569 }
 570
 571 int
 572 get_indirect_operand (fragment, size, buffer)
 573      unsigned short fragment;
 574      int size;
 575      char *buffer;
 576 {
 577   unsigned char mod;
 578   unsigned arnum;
 579   unsigned char disp;
 580
 581   if (buffer == NULL)
 582     return 0;
 583   /* Determine which bits identify the sections of the indirect operand based on the
 584      size in bytes. */
 585   switch (size)
 586     {
 587     case 1:
 588       mod = (fragment & 0x00F8) >> 3;
 589       arnum = (fragment & 0x0007);
 590       disp = 0;
 591       break;
 592     case 2:
 593       mod = (fragment & 0xF800) >> 11;
 594       arnum = (fragment & 0x0700) >> 8;
 595       disp = (fragment & 0x00FF);
 596       break;
 597     default:
 598       return 0;
 599     }
 600   {
 601     const ind_addr_type *current_ind = tic30_indaddr_tab;
 602     for (; current_ind < tic30_indaddrtab_end; current_ind++)
 603       {
 604         if (current_ind->modfield == mod)
 605           {
 606             if (current_ind->displacement == IMPLIED_DISP && size == 2)
 607               {
 608                 continue;
 609               }
 610             else
 611               {
 612                 int i, bufcnt;
 613                 for (i = 0, bufcnt = 0; i < strlen (current_ind->syntax); i++, bufcnt++)
 614                   {
 615                     buffer[bufcnt] = current_ind->syntax[i];
 616                     if (buffer[bufcnt - 1] == 'a' && buffer[bufcnt] == 'r')
 617                       buffer[++bufcnt] = arnum + '0';
 618                     if (buffer[bufcnt] == '(' && current_ind->displacement == DISP_REQUIRED)
 619                       {
 620                         sprintf (&buffer[bufcnt + 1], "%u", disp);
 621                         bufcnt += strlen (&buffer[bufcnt + 1]);
 622                       }
 623                   }
 624                 buffer[bufcnt + 1] = '\0';
 625                 break;
 626               }
 627           }
 628       }
 629   }
 630   return 1;
 631 }
 632
 633 int
 634 get_register_operand (fragment, buffer)
 635      unsigned char fragment;
 636      char *buffer;
 637 {
 638   const reg *current_reg = tic30_regtab;
 639
 640   if (buffer == NULL)
 641     return 0;
 642   for (; current_reg < tic30_regtab_end; current_reg++)
 643     {
 644       if ((fragment & 0x1F) == current_reg->opcode)
 645         {
 646           strcpy (buffer, current_reg->name);
 647           return 1;
 648         }
 649     }
 650   return 0;
 651 }
 652
 653 int
 654 cnvt_tmsfloat_ieee (tmsfloat, size, ieeefloat)
 655      unsigned long tmsfloat;
 656      int size;
 657      float *ieeefloat;
 658 {
 659   unsigned long exp, sign, mant;
 660
 661   if (size == 2)
 662     {
 663       if ((tmsfloat & 0x0000F000) == 0x00008000)
 664         tmsfloat = 0x80000000;
 665       else
 666         {
 667           tmsfloat <<= 16;
 668           tmsfloat = (long) tmsfloat >> 4;
 669         }
 670     }
 671   exp = tmsfloat & 0xFF000000;
 672   if (exp == 0x80000000)
 673     {
 674       *ieeefloat = 0.0;
 675       return 1;
 676     }
 677   exp += 0x7F000000;
 678   sign = (tmsfloat & 0x00800000) << 8;
 679   mant = tmsfloat & 0x007FFFFF;
 680   if (exp == 0xFF000000)
 681     {
 682       if (mant == 0)
 683         *ieeefloat = ERANGE;
 684       if (sign == 0)
 685         *ieeefloat = 1.0 / 0.0;
 686       else
 687         *ieeefloat = -1.0 / 0.0;
 688       return 1;
 689     }
 690   exp >>= 1;
 691   if (sign)
 692     {
 693       mant = (~mant) & 0x007FFFFF;
 694       mant += 1;
 695       exp += mant & 0x00800000;
 696       exp &= 0x7F800000;
 697       mant &= 0x007FFFFF;
 698     }
 699   if (tmsfloat == 0x80000000)
 700     sign = mant = exp = 0;
 701   tmsfloat = sign | exp | mant;
 702   *ieeefloat = *((float *) &tmsfloat);
 703   return 1;
 704 }